2 * QEMU IDE Emulation: PCI cmd646 support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
28 #include "hw/pci/pci.h"
29 #include "qemu/module.h"
30 #include "hw/isa/isa.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
34 #include "hw/ide/pci.h"
39 #define CFR_INTR_CH0 0x04
41 #define CNTRL_EN_CH0 0x04
42 #define CNTRL_EN_CH1 0x08
44 #define ARTTIM23_INTR_CH1 0x10
46 #define MRDMODE_INTR_CH0 0x04
47 #define MRDMODE_INTR_CH1 0x08
48 #define MRDMODE_BLK_CH0 0x10
49 #define MRDMODE_BLK_CH1 0x20
50 #define UDIDETCR0 0x73
51 #define UDIDETCR1 0x7B
53 static void cmd646_update_irq(PCIDevice
*pd
);
55 static void cmd646_update_dma_interrupts(PCIDevice
*pd
)
57 /* Sync DMA interrupt status from UDMA interrupt status */
58 if (pd
->config
[MRDMODE
] & MRDMODE_INTR_CH0
) {
59 pd
->config
[CFR
] |= CFR_INTR_CH0
;
61 pd
->config
[CFR
] &= ~CFR_INTR_CH0
;
64 if (pd
->config
[MRDMODE
] & MRDMODE_INTR_CH1
) {
65 pd
->config
[ARTTIM23
] |= ARTTIM23_INTR_CH1
;
67 pd
->config
[ARTTIM23
] &= ~ARTTIM23_INTR_CH1
;
71 static void cmd646_update_udma_interrupts(PCIDevice
*pd
)
73 /* Sync UDMA interrupt status from DMA interrupt status */
74 if (pd
->config
[CFR
] & CFR_INTR_CH0
) {
75 pd
->config
[MRDMODE
] |= MRDMODE_INTR_CH0
;
77 pd
->config
[MRDMODE
] &= ~MRDMODE_INTR_CH0
;
80 if (pd
->config
[ARTTIM23
] & ARTTIM23_INTR_CH1
) {
81 pd
->config
[MRDMODE
] |= MRDMODE_INTR_CH1
;
83 pd
->config
[MRDMODE
] &= ~MRDMODE_INTR_CH1
;
87 static uint64_t bmdma_read(void *opaque
, hwaddr addr
,
90 BMDMAState
*bm
= opaque
;
91 PCIDevice
*pci_dev
= PCI_DEVICE(bm
->pci_dev
);
95 return ((uint64_t)1 << (size
* 8)) - 1;
103 val
= pci_dev
->config
[MRDMODE
];
109 if (bm
== &bm
->pci_dev
->bmdma
[0]) {
110 val
= pci_dev
->config
[UDIDETCR0
];
112 val
= pci_dev
->config
[UDIDETCR1
];
120 trace_bmdma_read_cmd646(addr
, val
);
124 static void bmdma_write(void *opaque
, hwaddr addr
,
125 uint64_t val
, unsigned size
)
127 BMDMAState
*bm
= opaque
;
128 PCIDevice
*pci_dev
= PCI_DEVICE(bm
->pci_dev
);
134 trace_bmdma_write_cmd646(addr
, val
);
137 bmdma_cmd_writeb(bm
, val
);
140 pci_dev
->config
[MRDMODE
] =
141 (pci_dev
->config
[MRDMODE
] & ~0x30) | (val
& 0x30);
142 cmd646_update_dma_interrupts(pci_dev
);
143 cmd646_update_irq(pci_dev
);
146 bm
->status
= (val
& 0x60) | (bm
->status
& 1) | (bm
->status
& ~val
& 0x06);
149 if (bm
== &bm
->pci_dev
->bmdma
[0]) {
150 pci_dev
->config
[UDIDETCR0
] = val
;
152 pci_dev
->config
[UDIDETCR1
] = val
;
158 static const MemoryRegionOps cmd646_bmdma_ops
= {
160 .write
= bmdma_write
,
163 static void bmdma_setup_bar(PCIIDEState
*d
)
168 memory_region_init(&d
->bmdma_bar
, OBJECT(d
), "cmd646-bmdma", 16);
169 for(i
= 0;i
< 2; i
++) {
171 memory_region_init_io(&bm
->extra_io
, OBJECT(d
), &cmd646_bmdma_ops
, bm
,
172 "cmd646-bmdma-bus", 4);
173 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8, &bm
->extra_io
);
174 memory_region_init_io(&bm
->addr_ioport
, OBJECT(d
),
175 &bmdma_addr_ioport_ops
, bm
,
176 "cmd646-bmdma-ioport", 4);
177 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8 + 4, &bm
->addr_ioport
);
181 static void cmd646_update_irq(PCIDevice
*pd
)
185 pci_level
= ((pd
->config
[MRDMODE
] & MRDMODE_INTR_CH0
) &&
186 !(pd
->config
[MRDMODE
] & MRDMODE_BLK_CH0
)) ||
187 ((pd
->config
[MRDMODE
] & MRDMODE_INTR_CH1
) &&
188 !(pd
->config
[MRDMODE
] & MRDMODE_BLK_CH1
));
189 pci_set_irq(pd
, pci_level
);
192 /* the PCI irq level is the logical OR of the two channels */
193 static void cmd646_set_irq(void *opaque
, int channel
, int level
)
195 PCIIDEState
*d
= opaque
;
196 PCIDevice
*pd
= PCI_DEVICE(d
);
199 irq_mask
= MRDMODE_INTR_CH0
<< channel
;
201 pd
->config
[MRDMODE
] |= irq_mask
;
203 pd
->config
[MRDMODE
] &= ~irq_mask
;
205 cmd646_update_dma_interrupts(pd
);
206 cmd646_update_irq(pd
);
209 static void cmd646_reset(void *opaque
)
211 PCIIDEState
*d
= opaque
;
214 for (i
= 0; i
< 2; i
++) {
215 ide_bus_reset(&d
->bus
[i
]);
219 static uint32_t cmd646_pci_config_read(PCIDevice
*d
,
220 uint32_t address
, int len
)
222 return pci_default_read_config(d
, address
, len
);
225 static void cmd646_pci_config_write(PCIDevice
*d
, uint32_t addr
, uint32_t val
,
230 pci_default_write_config(d
, addr
, val
, l
);
232 for (i
= addr
; i
< addr
+ l
; i
++) {
236 cmd646_update_udma_interrupts(d
);
239 cmd646_update_dma_interrupts(d
);
244 cmd646_update_irq(d
);
247 /* CMD646 PCI IDE controller */
248 static void pci_cmd646_ide_realize(PCIDevice
*dev
, Error
**errp
)
250 PCIIDEState
*d
= PCI_IDE(dev
);
251 uint8_t *pci_conf
= dev
->config
;
255 pci_conf
[PCI_CLASS_PROG
] = 0x8f;
257 pci_conf
[CNTRL
] = CNTRL_EN_CH0
; // enable IDE0
259 /* XXX: if not enabled, really disable the seconday IDE controller */
260 pci_conf
[CNTRL
] |= CNTRL_EN_CH1
; /* enable IDE1 */
263 /* Set write-to-clear interrupt bits */
264 dev
->wmask
[CFR
] = 0x0;
265 dev
->w1cmask
[CFR
] = CFR_INTR_CH0
;
266 dev
->wmask
[ARTTIM23
] = 0x0;
267 dev
->w1cmask
[ARTTIM23
] = ARTTIM23_INTR_CH1
;
268 dev
->wmask
[MRDMODE
] = 0x0;
269 dev
->w1cmask
[MRDMODE
] = MRDMODE_INTR_CH0
| MRDMODE_INTR_CH1
;
271 memory_region_init_io(&d
->data_bar
[0], OBJECT(d
), &pci_ide_data_le_ops
,
272 &d
->bus
[0], "cmd646-data0", 8);
273 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_SPACE_IO
, &d
->data_bar
[0]);
275 memory_region_init_io(&d
->cmd_bar
[0], OBJECT(d
), &pci_ide_cmd_le_ops
,
276 &d
->bus
[0], "cmd646-cmd0", 4);
277 pci_register_bar(dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &d
->cmd_bar
[0]);
279 memory_region_init_io(&d
->data_bar
[1], OBJECT(d
), &pci_ide_data_le_ops
,
280 &d
->bus
[1], "cmd646-data1", 8);
281 pci_register_bar(dev
, 2, PCI_BASE_ADDRESS_SPACE_IO
, &d
->data_bar
[1]);
283 memory_region_init_io(&d
->cmd_bar
[1], OBJECT(d
), &pci_ide_cmd_le_ops
,
284 &d
->bus
[1], "cmd646-cmd1", 4);
285 pci_register_bar(dev
, 3, PCI_BASE_ADDRESS_SPACE_IO
, &d
->cmd_bar
[1]);
288 pci_register_bar(dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &d
->bmdma_bar
);
290 /* TODO: RST# value should be 0 */
291 pci_conf
[PCI_INTERRUPT_PIN
] = 0x01; // interrupt on pin 1
293 irq
= qemu_allocate_irqs(cmd646_set_irq
, d
, 2);
294 for (i
= 0; i
< 2; i
++) {
295 ide_bus_new(&d
->bus
[i
], sizeof(d
->bus
[i
]), DEVICE(dev
), i
, 2);
296 ide_init2(&d
->bus
[i
], irq
[i
]);
298 bmdma_init(&d
->bus
[i
], &d
->bmdma
[i
], d
);
299 d
->bmdma
[i
].bus
= &d
->bus
[i
];
300 ide_register_restart_cb(&d
->bus
[i
]);
303 vmstate_register(DEVICE(dev
), 0, &vmstate_ide_pci
, d
);
304 qemu_register_reset(cmd646_reset
, d
);
307 static void pci_cmd646_ide_exitfn(PCIDevice
*dev
)
309 PCIIDEState
*d
= PCI_IDE(dev
);
312 for (i
= 0; i
< 2; ++i
) {
313 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].extra_io
);
314 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].addr_ioport
);
318 void pci_cmd646_ide_init(PCIBus
*bus
, DriveInfo
**hd_table
,
319 int secondary_ide_enabled
)
323 dev
= pci_create(bus
, -1, "cmd646-ide");
324 qdev_prop_set_uint32(&dev
->qdev
, "secondary", secondary_ide_enabled
);
325 qdev_init_nofail(&dev
->qdev
);
327 pci_ide_create_devs(dev
, hd_table
);
330 static Property cmd646_ide_properties
[] = {
331 DEFINE_PROP_UINT32("secondary", PCIIDEState
, secondary
, 0),
332 DEFINE_PROP_END_OF_LIST(),
335 static void cmd646_ide_class_init(ObjectClass
*klass
, void *data
)
337 DeviceClass
*dc
= DEVICE_CLASS(klass
);
338 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
340 k
->realize
= pci_cmd646_ide_realize
;
341 k
->exit
= pci_cmd646_ide_exitfn
;
342 k
->vendor_id
= PCI_VENDOR_ID_CMD
;
343 k
->device_id
= PCI_DEVICE_ID_CMD_646
;
345 k
->class_id
= PCI_CLASS_STORAGE_IDE
;
346 k
->config_read
= cmd646_pci_config_read
;
347 k
->config_write
= cmd646_pci_config_write
;
348 dc
->props
= cmd646_ide_properties
;
349 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
352 static const TypeInfo cmd646_ide_info
= {
353 .name
= "cmd646-ide",
354 .parent
= TYPE_PCI_IDE
,
355 .class_init
= cmd646_ide_class_init
,
358 static void cmd646_ide_register_types(void)
360 type_register_static(&cmd646_ide_info
);
363 type_init(cmd646_ide_register_types
)