2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "qemu/error-report.h"
15 #include "target/ppc/cpu.h"
16 #include "sysemu/cpus.h"
17 #include "monitor/monitor.h"
18 #include "hw/ppc/fdt.h"
19 #include "hw/ppc/spapr.h"
20 #include "hw/ppc/spapr_cpu_core.h"
21 #include "hw/ppc/spapr_xive.h"
22 #include "hw/ppc/xive.h"
23 #include "hw/ppc/xive_regs.h"
26 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
27 * use for the ESB pages and the TIMA pages
29 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
30 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
33 * The allocation of VP blocks is a complex operation in OPAL and the
34 * VP identifiers have a relation with the number of HW chips, the
35 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
36 * controller model does not have the same constraints and can use a
37 * simple mapping scheme of the CPU vcpu_id
39 * These identifiers are never returned to the OS.
42 #define SPAPR_XIVE_NVT_BASE 0x400
45 * sPAPR NVT and END indexing helpers
47 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
49 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
52 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
53 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
58 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
62 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
66 static int spapr_xive_target_to_nvt(uint32_t target
,
67 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
69 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
75 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
80 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
83 int spapr_xive_end_to_target(uint8_t end_blk
, uint32_t end_idx
,
84 uint32_t *out_server
, uint8_t *out_prio
)
87 assert(end_blk
== SPAPR_XIVE_BLOCK_ID
);
90 *out_server
= end_idx
>> 3;
94 *out_prio
= end_idx
& 0x7;
99 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
100 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
105 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
109 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
113 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
114 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
116 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
122 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
127 * On sPAPR machines, use a simplified output for the XIVE END
128 * structure dumping only the information related to the OS EQ.
130 static void spapr_xive_end_pic_print_info(SpaprXive
*xive
, XiveEND
*end
,
133 uint64_t qaddr_base
= xive_end_qaddr(end
);
134 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
135 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
136 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
137 uint32_t qentries
= 1 << (qsize
+ 10);
138 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
139 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
141 monitor_printf(mon
, "%3d/%d % 6d/%5d @%"PRIx64
" ^%d",
142 spapr_xive_nvt_to_target(0, nvt
),
143 priority
, qindex
, qentries
, qaddr_base
, qgen
);
145 xive_end_queue_pic_print_info(end
, 6, mon
);
146 monitor_printf(mon
, "]");
149 void spapr_xive_pic_print_info(SpaprXive
*xive
, Monitor
*mon
)
151 XiveSource
*xsrc
= &xive
->source
;
154 if (kvm_irqchip_in_kernel()) {
155 Error
*local_err
= NULL
;
157 kvmppc_xive_synchronize_state(xive
, &local_err
);
159 error_report_err(local_err
);
164 monitor_printf(mon
, " LISN PQ EISN CPU/PRIO EQ\n");
166 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
167 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
168 XiveEAS
*eas
= &xive
->eat
[i
];
170 if (!xive_eas_is_valid(eas
)) {
174 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
175 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
176 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
177 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
178 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
179 xive_eas_is_masked(eas
) ? "M" : " ",
180 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
182 if (!xive_eas_is_masked(eas
)) {
183 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
186 assert(end_idx
< xive
->nr_ends
);
187 end
= &xive
->endt
[end_idx
];
189 if (xive_end_is_valid(end
)) {
190 spapr_xive_end_pic_print_info(xive
, end
, mon
);
193 monitor_printf(mon
, "\n");
197 void spapr_xive_map_mmio(SpaprXive
*xive
)
199 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
200 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
201 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
204 void spapr_xive_mmio_set_enabled(SpaprXive
*xive
, bool enable
)
206 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
207 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
209 /* Disable the END ESBs until a guest OS makes use of them */
210 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
214 * When a Virtual Processor is scheduled to run on a HW thread, the
215 * hypervisor pushes its identifier in the OS CAM line. Emulate the
216 * same behavior under QEMU.
218 void spapr_xive_set_tctx_os_cam(XiveTCTX
*tctx
)
224 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx
->cs
), &nvt_blk
, &nvt_idx
);
226 nvt_cam
= cpu_to_be32(TM_QW1W2_VO
| xive_nvt_cam_line(nvt_blk
, nvt_idx
));
227 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &nvt_cam
, 4);
230 static void spapr_xive_end_reset(XiveEND
*end
)
232 memset(end
, 0, sizeof(*end
));
234 /* switch off the escalation and notification ESBs */
235 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
238 static void spapr_xive_reset(void *dev
)
240 SpaprXive
*xive
= SPAPR_XIVE(dev
);
244 * The XiveSource has its own reset handler, which mask off all
248 /* Mask all valid EASs in the IRQ number space. */
249 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
250 XiveEAS
*eas
= &xive
->eat
[i
];
251 if (xive_eas_is_valid(eas
)) {
252 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
259 for (i
= 0; i
< xive
->nr_ends
; i
++) {
260 spapr_xive_end_reset(&xive
->endt
[i
]);
264 static void spapr_xive_instance_init(Object
*obj
)
266 SpaprXive
*xive
= SPAPR_XIVE(obj
);
268 object_initialize_child(obj
, "source", &xive
->source
, sizeof(xive
->source
),
269 TYPE_XIVE_SOURCE
, &error_abort
, NULL
);
271 object_initialize_child(obj
, "end_source", &xive
->end_source
,
272 sizeof(xive
->end_source
), TYPE_XIVE_END_SOURCE
,
275 /* Not connected to the KVM XIVE device */
279 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
281 SpaprXive
*xive
= SPAPR_XIVE(dev
);
282 XiveSource
*xsrc
= &xive
->source
;
283 XiveENDSource
*end_xsrc
= &xive
->end_source
;
284 Error
*local_err
= NULL
;
286 if (!xive
->nr_irqs
) {
287 error_setg(errp
, "Number of interrupt needs to be greater 0");
291 if (!xive
->nr_ends
) {
292 error_setg(errp
, "Number of interrupt needs to be greater 0");
297 * Initialize the internal sources, for IPIs and virtual devices.
299 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
301 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
303 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
305 error_propagate(errp
, local_err
);
310 * Initialize the END ESB source
312 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
314 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
316 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
318 error_propagate(errp
, local_err
);
322 /* Set the mapping address of the END ESB pages after the source ESBs */
323 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
326 * Allocate the routing tables
328 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
329 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
331 xive
->nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
332 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
334 qemu_register_reset(spapr_xive_reset
, dev
);
336 /* Define all XIVE MMIO regions on SysBus */
337 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
338 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
339 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
342 void spapr_xive_init(SpaprXive
*xive
, Error
**errp
)
344 XiveSource
*xsrc
= &xive
->source
;
347 * The emulated XIVE device can only be initialized once. If the
348 * ESB memory region has been already mapped, it means we have been
351 if (memory_region_is_mapped(&xsrc
->esb_mmio
)) {
355 /* TIMA initialization */
356 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
357 "xive.tima", 4ull << TM_SHIFT
);
359 /* Map all regions */
360 spapr_xive_map_mmio(xive
);
363 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
364 uint32_t eas_idx
, XiveEAS
*eas
)
366 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
368 if (eas_idx
>= xive
->nr_irqs
) {
372 *eas
= xive
->eat
[eas_idx
];
376 static int spapr_xive_get_end(XiveRouter
*xrtr
,
377 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
379 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
381 if (end_idx
>= xive
->nr_ends
) {
385 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
389 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
390 uint32_t end_idx
, XiveEND
*end
,
393 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
395 if (end_idx
>= xive
->nr_ends
) {
399 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
403 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
404 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
406 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
407 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
410 /* TODO: should we assert() if we can find a NVT ? */
415 * sPAPR does not maintain a NVT table. Return that the NVT is
416 * valid if we have found a matching CPU
418 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
422 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
423 uint32_t nvt_idx
, XiveNVT
*nvt
,
427 * We don't need to write back to the NVTs because the sPAPR
428 * machine should never hit a non-scheduled NVT. It should never
431 g_assert_not_reached();
434 static XiveTCTX
*spapr_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
436 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
438 return spapr_cpu_state(cpu
)->tctx
;
441 static const VMStateDescription vmstate_spapr_xive_end
= {
442 .name
= TYPE_SPAPR_XIVE
"/end",
444 .minimum_version_id
= 1,
445 .fields
= (VMStateField
[]) {
446 VMSTATE_UINT32(w0
, XiveEND
),
447 VMSTATE_UINT32(w1
, XiveEND
),
448 VMSTATE_UINT32(w2
, XiveEND
),
449 VMSTATE_UINT32(w3
, XiveEND
),
450 VMSTATE_UINT32(w4
, XiveEND
),
451 VMSTATE_UINT32(w5
, XiveEND
),
452 VMSTATE_UINT32(w6
, XiveEND
),
453 VMSTATE_UINT32(w7
, XiveEND
),
454 VMSTATE_END_OF_LIST()
458 static const VMStateDescription vmstate_spapr_xive_eas
= {
459 .name
= TYPE_SPAPR_XIVE
"/eas",
461 .minimum_version_id
= 1,
462 .fields
= (VMStateField
[]) {
463 VMSTATE_UINT64(w
, XiveEAS
),
464 VMSTATE_END_OF_LIST()
468 static int vmstate_spapr_xive_pre_save(void *opaque
)
470 if (kvm_irqchip_in_kernel()) {
471 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque
));
478 * Called by the sPAPR IRQ backend 'post_load' method at the machine
481 int spapr_xive_post_load(SpaprXive
*xive
, int version_id
)
483 if (kvm_irqchip_in_kernel()) {
484 return kvmppc_xive_post_load(xive
, version_id
);
490 static const VMStateDescription vmstate_spapr_xive
= {
491 .name
= TYPE_SPAPR_XIVE
,
493 .minimum_version_id
= 1,
494 .pre_save
= vmstate_spapr_xive_pre_save
,
495 .post_load
= NULL
, /* handled at the machine level */
496 .fields
= (VMStateField
[]) {
497 VMSTATE_UINT32_EQUAL(nr_irqs
, SpaprXive
, NULL
),
498 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, SpaprXive
, nr_irqs
,
499 vmstate_spapr_xive_eas
, XiveEAS
),
500 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, SpaprXive
, nr_ends
,
501 vmstate_spapr_xive_end
, XiveEND
),
502 VMSTATE_END_OF_LIST()
506 static Property spapr_xive_properties
[] = {
507 DEFINE_PROP_UINT32("nr-irqs", SpaprXive
, nr_irqs
, 0),
508 DEFINE_PROP_UINT32("nr-ends", SpaprXive
, nr_ends
, 0),
509 DEFINE_PROP_UINT64("vc-base", SpaprXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
510 DEFINE_PROP_UINT64("tm-base", SpaprXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
511 DEFINE_PROP_END_OF_LIST(),
514 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
516 DeviceClass
*dc
= DEVICE_CLASS(klass
);
517 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
519 dc
->desc
= "sPAPR XIVE Interrupt Controller";
520 dc
->props
= spapr_xive_properties
;
521 dc
->realize
= spapr_xive_realize
;
522 dc
->vmsd
= &vmstate_spapr_xive
;
524 xrc
->get_eas
= spapr_xive_get_eas
;
525 xrc
->get_end
= spapr_xive_get_end
;
526 xrc
->write_end
= spapr_xive_write_end
;
527 xrc
->get_nvt
= spapr_xive_get_nvt
;
528 xrc
->write_nvt
= spapr_xive_write_nvt
;
529 xrc
->get_tctx
= spapr_xive_get_tctx
;
532 static const TypeInfo spapr_xive_info
= {
533 .name
= TYPE_SPAPR_XIVE
,
534 .parent
= TYPE_XIVE_ROUTER
,
535 .instance_init
= spapr_xive_instance_init
,
536 .instance_size
= sizeof(SpaprXive
),
537 .class_init
= spapr_xive_class_init
,
540 static void spapr_xive_register_types(void)
542 type_register_static(&spapr_xive_info
);
545 type_init(spapr_xive_register_types
)
547 bool spapr_xive_irq_claim(SpaprXive
*xive
, uint32_t lisn
, bool lsi
)
549 XiveSource
*xsrc
= &xive
->source
;
551 if (lisn
>= xive
->nr_irqs
) {
555 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
);
557 xive_source_irq_set_lsi(xsrc
, lisn
);
560 if (kvm_irqchip_in_kernel()) {
561 Error
*local_err
= NULL
;
563 kvmppc_xive_source_reset_one(xsrc
, lisn
, &local_err
);
565 error_report_err(local_err
);
573 bool spapr_xive_irq_free(SpaprXive
*xive
, uint32_t lisn
)
575 if (lisn
>= xive
->nr_irqs
) {
579 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
586 * The terminology used by the XIVE hcalls is the following :
589 * EQ Event Queue assigned by OS to receive event data
590 * ESB page for source interrupt management
591 * LISN Logical Interrupt Source Number identifying a source in the
593 * EISN Effective Interrupt Source Number used by guest OS to
594 * identify source in the guest
596 * The EAS, END, NVT structures are not exposed.
600 * Linux hosts under OPAL reserve priority 7 for their own escalation
601 * interrupts (DD2.X POWER9). So we only allow the guest to use
604 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
609 case 7: /* OPAL escalation queue */
616 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
617 * real address of the MMIO page through which the Event State Buffer
618 * entry associated with the value of the "lisn" parameter is managed.
624 * - R5: "lisn" is per "interrupts", "interrupt-map", or
625 * "ibm,xive-lisn-ranges" properties, or as returned by the
626 * ibm,query-interrupt-source-number RTAS call, or as returned
627 * by the H_ALLOCATE_VAS_WINDOW hcall
631 * Bits 0-59: Reserved
632 * Bit 60: H_INT_ESB must be used for Event State Buffer
634 * Bit 61: 1 == LSI 0 == MSI
635 * Bit 62: the full function page supports trigger
636 * Bit 63: Store EOI Supported
637 * - R5: Logical Real address of full function Event State Buffer
638 * management page, -1 if H_INT_ESB hcall flag is set to 1.
639 * - R6: Logical Real Address of trigger only Event State Buffer
640 * management page or -1.
641 * - R7: Power of 2 page size for the ESB management pages returned in
645 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
646 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
647 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
649 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
651 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
652 SpaprMachineState
*spapr
,
656 SpaprXive
*xive
= spapr
->xive
;
657 XiveSource
*xsrc
= &xive
->source
;
658 target_ulong flags
= args
[0];
659 target_ulong lisn
= args
[1];
661 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
669 if (lisn
>= xive
->nr_irqs
) {
670 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
675 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
676 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
682 * All sources are emulated under the main XIVE object and share
683 * the same characteristics.
686 if (!xive_source_esb_has_2page(xsrc
)) {
687 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
689 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
690 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
694 * Force the use of the H_INT_ESB hcall in case of an LSI
695 * interrupt. This is necessary under KVM to re-trigger the
696 * interrupt if the level is still asserted
698 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
699 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
702 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
703 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
708 if (xive_source_esb_has_2page(xsrc
) &&
709 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
710 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
715 if (xive_source_esb_has_2page(xsrc
)) {
716 args
[3] = xsrc
->esb_shift
- 1;
718 args
[3] = xsrc
->esb_shift
;
725 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
726 * Interrupt Source to a target. The Logical Interrupt Source is
727 * designated with the "lisn" parameter and the target is designated
728 * with the "target" and "priority" parameters. Upon return from the
729 * hcall(), no additional interrupts will be directed to the old EQ.
734 * Bits 0-61: Reserved
735 * Bit 62: set the "eisn" in the EAS
736 * Bit 63: masks the interrupt source in the hardware interrupt
737 * control structure. An interrupt masked by this mechanism will
738 * be dropped, but it's source state bits will still be
739 * set. There is no race-free way of unmasking and restoring the
740 * source. Thus this should only be used in interrupts that are
741 * also masked at the source, and only in cases where the
742 * interrupt is not meant to be used for a large amount of time
743 * because no valid target exists for it for example
744 * - R5: "lisn" is per "interrupts", "interrupt-map", or
745 * "ibm,xive-lisn-ranges" properties, or as returned by the
746 * ibm,query-interrupt-source-number RTAS call, or as returned by
747 * the H_ALLOCATE_VAS_WINDOW hcall
748 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
749 * "ibm,ppc-interrupt-gserver#s"
750 * - R7: "priority" is a valid priority not in
751 * "ibm,plat-res-int-priorities"
752 * - R8: "eisn" is the guest EISN associated with the "lisn"
758 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
759 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
761 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
762 SpaprMachineState
*spapr
,
766 SpaprXive
*xive
= spapr
->xive
;
767 XiveEAS eas
, new_eas
;
768 target_ulong flags
= args
[0];
769 target_ulong lisn
= args
[1];
770 target_ulong target
= args
[2];
771 target_ulong priority
= args
[3];
772 target_ulong eisn
= args
[4];
776 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
780 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
784 if (lisn
>= xive
->nr_irqs
) {
785 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
790 eas
= xive
->eat
[lisn
];
791 if (!xive_eas_is_valid(&eas
)) {
792 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
797 /* priority 0xff is used to reset the EAS */
798 if (priority
== 0xff) {
799 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
803 if (flags
& SPAPR_XIVE_SRC_MASK
) {
804 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
806 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
809 if (spapr_xive_priority_is_reserved(priority
)) {
810 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
811 " is reserved\n", priority
);
816 * Validate that "target" is part of the list of threads allocated
817 * to the partition. For that, find the END corresponding to the
820 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
824 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
825 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
827 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
828 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
831 if (kvm_irqchip_in_kernel()) {
832 Error
*local_err
= NULL
;
834 kvmppc_xive_set_source_config(xive
, lisn
, &new_eas
, &local_err
);
836 error_report_err(local_err
);
842 xive
->eat
[lisn
] = new_eas
;
847 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
848 * target/priority pair is assigned to the specified Logical Interrupt
855 * - R5: "lisn" is per "interrupts", "interrupt-map", or
856 * "ibm,xive-lisn-ranges" properties, or as returned by the
857 * ibm,query-interrupt-source-number RTAS call, or as
858 * returned by the H_ALLOCATE_VAS_WINDOW hcall
861 * - R4: Target to which the specified Logical Interrupt Source is
863 * - R5: Priority to which the specified Logical Interrupt Source is
865 * - R6: EISN for the specified Logical Interrupt Source (this will be
866 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
868 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
869 SpaprMachineState
*spapr
,
873 SpaprXive
*xive
= spapr
->xive
;
874 target_ulong flags
= args
[0];
875 target_ulong lisn
= args
[1];
879 uint32_t end_idx
, nvt_idx
;
881 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
889 if (lisn
>= xive
->nr_irqs
) {
890 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
895 eas
= xive
->eat
[lisn
];
896 if (!xive_eas_is_valid(&eas
)) {
897 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
902 /* EAS_END_BLOCK is unused on sPAPR */
903 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
905 assert(end_idx
< xive
->nr_ends
);
906 end
= &xive
->endt
[end_idx
];
908 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
909 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
910 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
912 if (xive_eas_is_masked(&eas
)) {
915 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
918 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
924 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
925 * address of the notification management page associated with the
926 * specified target and priority.
932 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
933 * "ibm,ppc-interrupt-gserver#s"
934 * - R6: "priority" is a valid priority not in
935 * "ibm,plat-res-int-priorities"
938 * - R4: Logical real address of notification page
939 * - R5: Power of 2 page size of the notification page
941 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
942 SpaprMachineState
*spapr
,
946 SpaprXive
*xive
= spapr
->xive
;
947 XiveENDSource
*end_xsrc
= &xive
->end_source
;
948 target_ulong flags
= args
[0];
949 target_ulong target
= args
[1];
950 target_ulong priority
= args
[2];
955 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
964 * H_STATE should be returned if a H_INT_RESET is in progress.
965 * This is not needed when running the emulation under QEMU
968 if (spapr_xive_priority_is_reserved(priority
)) {
969 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
970 " is reserved\n", priority
);
975 * Validate that "target" is part of the list of threads allocated
976 * to the partition. For that, find the END corresponding to the
979 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
983 assert(end_idx
< xive
->nr_ends
);
984 end
= &xive
->endt
[end_idx
];
986 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
987 if (xive_end_is_enqueue(end
)) {
988 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
997 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
998 * a given "target" and "priority". It is also used to set the
999 * notification config associated with the EQ. An EQ size of 0 is
1000 * used to reset the EQ config for a given target and priority. If
1001 * resetting the EQ config, the END associated with the given "target"
1002 * and "priority" will be changed to disable queueing.
1004 * Upon return from the hcall(), no additional interrupts will be
1005 * directed to the old EQ (if one was set). The old EQ (if one was
1006 * set) should be investigated for interrupts that occurred prior to
1007 * or during the hcall().
1012 * Bits 0-62: Reserved
1013 * Bit 63: Unconditional Notify (n) per the XIVE spec
1014 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1015 * "ibm,ppc-interrupt-gserver#s"
1016 * - R6: "priority" is a valid priority not in
1017 * "ibm,plat-res-int-priorities"
1018 * - R7: "eventQueue": The logical real address of the start of the EQ
1019 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1025 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1027 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
1028 SpaprMachineState
*spapr
,
1029 target_ulong opcode
,
1032 SpaprXive
*xive
= spapr
->xive
;
1033 target_ulong flags
= args
[0];
1034 target_ulong target
= args
[1];
1035 target_ulong priority
= args
[2];
1036 target_ulong qpage
= args
[3];
1037 target_ulong qsize
= args
[4];
1039 uint8_t end_blk
, nvt_blk
;
1040 uint32_t end_idx
, nvt_idx
;
1042 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1046 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1051 * H_STATE should be returned if a H_INT_RESET is in progress.
1052 * This is not needed when running the emulation under QEMU
1055 if (spapr_xive_priority_is_reserved(priority
)) {
1056 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1057 " is reserved\n", priority
);
1062 * Validate that "target" is part of the list of threads allocated
1063 * to the partition. For that, find the END corresponding to the
1067 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1071 assert(end_idx
< xive
->nr_ends
);
1072 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
1079 if (!QEMU_IS_ALIGNED(qpage
, 1ul << qsize
)) {
1080 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: EQ @0x%" HWADDR_PRIx
1081 " is not naturally aligned with %" HWADDR_PRIx
"\n",
1082 qpage
, (hwaddr
)1 << qsize
);
1085 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
1086 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
1087 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
1088 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1091 /* reset queue and disable queueing */
1092 spapr_xive_end_reset(&end
);
1096 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1102 hwaddr plen
= 1 << qsize
;
1106 * Validate the guest EQ. We should also check that the queue
1107 * has been zeroed by the OS.
1109 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1110 MEMTXATTRS_UNSPECIFIED
);
1111 if (plen
!= 1 << qsize
) {
1112 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1113 HWADDR_PRIx
"\n", qpage
);
1116 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1119 /* "target" should have been validated above */
1120 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1121 g_assert_not_reached();
1125 * Ensure the priority and target are correctly set (they will not
1126 * be right after allocation)
1128 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1129 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1130 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1132 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1133 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1135 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1139 * The generation bit for the END starts at 1 and The END page
1140 * offset counter starts at 0.
1142 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1143 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1144 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1147 * TODO: issue syncs required to ensure all in-flight interrupts
1148 * are complete on the old END
1152 if (kvm_irqchip_in_kernel()) {
1153 Error
*local_err
= NULL
;
1155 kvmppc_xive_set_queue_config(xive
, end_blk
, end_idx
, &end
, &local_err
);
1157 error_report_err(local_err
);
1163 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1168 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1169 * target and priority.
1174 * Bits 0-62: Reserved
1175 * Bit 63: Debug: Return debug data
1176 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1177 * "ibm,ppc-interrupt-gserver#s"
1178 * - R6: "priority" is a valid priority not in
1179 * "ibm,plat-res-int-priorities"
1183 * Bits 0-61: Reserved
1184 * Bit 62: The value of Event Queue Generation Number (g) per
1185 * the XIVE spec if "Debug" = 1
1186 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1187 * - R5: The logical real address of the start of the EQ
1188 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1189 * - R7: The value of Event Queue Offset Counter per XIVE spec
1190 * if "Debug" = 1, else 0
1194 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1196 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1197 SpaprMachineState
*spapr
,
1198 target_ulong opcode
,
1201 SpaprXive
*xive
= spapr
->xive
;
1202 target_ulong flags
= args
[0];
1203 target_ulong target
= args
[1];
1204 target_ulong priority
= args
[2];
1209 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1213 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1218 * H_STATE should be returned if a H_INT_RESET is in progress.
1219 * This is not needed when running the emulation under QEMU
1222 if (spapr_xive_priority_is_reserved(priority
)) {
1223 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1224 " is reserved\n", priority
);
1229 * Validate that "target" is part of the list of threads allocated
1230 * to the partition. For that, find the END corresponding to the
1233 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1237 assert(end_idx
< xive
->nr_ends
);
1238 end
= &xive
->endt
[end_idx
];
1241 if (xive_end_is_notify(end
)) {
1242 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1245 if (xive_end_is_enqueue(end
)) {
1246 args
[1] = xive_end_qaddr(end
);
1247 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1253 if (kvm_irqchip_in_kernel()) {
1254 Error
*local_err
= NULL
;
1256 kvmppc_xive_get_queue_config(xive
, end_blk
, end_idx
, end
, &local_err
);
1258 error_report_err(local_err
);
1263 /* TODO: do we need any locking on the END ? */
1264 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1265 /* Load the event queue generation number into the return flags */
1266 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1268 /* Load R7 with the event queue offset counter */
1269 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1278 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1279 * reporting cache line pair for the calling thread. The reporting
1280 * cache lines will contain the OS interrupt context when the OS
1281 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1282 * interrupt. The reporting cache lines can be reset by inputting -1
1283 * in "reportingLine". Issuing the CI store byte without reporting
1284 * cache lines registered will result in the data not being accessible
1290 * Bits 0-63: Reserved
1291 * - R5: "reportingLine": The logical real address of the reporting cache
1297 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1298 SpaprMachineState
*spapr
,
1299 target_ulong opcode
,
1302 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1307 * H_STATE should be returned if a H_INT_RESET is in progress.
1308 * This is not needed when running the emulation under QEMU
1311 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1316 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1317 * real address of the reporting cache line pair set for the input
1318 * "target". If no reporting cache line pair has been set, -1 is
1324 * Bits 0-63: Reserved
1325 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1326 * "ibm,ppc-interrupt-gserver#s"
1327 * - R6: "reportingLine": The logical real address of the reporting
1331 * - R4: The logical real address of the reporting line if set, else -1
1333 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1334 SpaprMachineState
*spapr
,
1335 target_ulong opcode
,
1338 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1343 * H_STATE should be returned if a H_INT_RESET is in progress.
1344 * This is not needed when running the emulation under QEMU
1347 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1352 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1353 * page for the input "lisn". This hcall is only supported for LISNs
1354 * that have the ESB hcall flag set to 1 when returned from hcall()
1355 * H_INT_GET_SOURCE_INFO.
1360 * Bits 0-62: Reserved
1361 * bit 63: Store: Store=1, store operation, else load operation
1362 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1363 * "ibm,xive-lisn-ranges" properties, or as returned by the
1364 * ibm,query-interrupt-source-number RTAS call, or as
1365 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1366 * - R6: "esbOffset" is the offset into the ESB page for the load or
1368 * - R7: "storeData" is the data to write for a store operation
1371 * - R4: The value of the load if load operation, else -1
1374 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1376 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1377 SpaprMachineState
*spapr
,
1378 target_ulong opcode
,
1381 SpaprXive
*xive
= spapr
->xive
;
1383 target_ulong flags
= args
[0];
1384 target_ulong lisn
= args
[1];
1385 target_ulong offset
= args
[2];
1386 target_ulong data
= args
[3];
1388 XiveSource
*xsrc
= &xive
->source
;
1390 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1394 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1398 if (lisn
>= xive
->nr_irqs
) {
1399 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1404 eas
= xive
->eat
[lisn
];
1405 if (!xive_eas_is_valid(&eas
)) {
1406 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1411 if (offset
> (1ull << xsrc
->esb_shift
)) {
1415 if (kvm_irqchip_in_kernel()) {
1416 args
[0] = kvmppc_xive_esb_rw(xsrc
, lisn
, offset
, data
,
1417 flags
& SPAPR_XIVE_ESB_STORE
);
1419 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1421 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1422 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1423 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1424 HWADDR_PRIx
"\n", mmio_addr
);
1427 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1433 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1434 * ensure any in flight events for the input lisn are in the event
1440 * Bits 0-63: Reserved
1441 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1442 * "ibm,xive-lisn-ranges" properties, or as returned by the
1443 * ibm,query-interrupt-source-number RTAS call, or as
1444 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1449 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1450 SpaprMachineState
*spapr
,
1451 target_ulong opcode
,
1454 SpaprXive
*xive
= spapr
->xive
;
1456 target_ulong flags
= args
[0];
1457 target_ulong lisn
= args
[1];
1459 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1467 if (lisn
>= xive
->nr_irqs
) {
1468 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1473 eas
= xive
->eat
[lisn
];
1474 if (!xive_eas_is_valid(&eas
)) {
1475 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1481 * H_STATE should be returned if a H_INT_RESET is in progress.
1482 * This is not needed when running the emulation under QEMU
1486 * This is not real hardware. Nothing to be done unless when
1490 if (kvm_irqchip_in_kernel()) {
1491 Error
*local_err
= NULL
;
1493 kvmppc_xive_sync_source(xive
, lisn
, &local_err
);
1495 error_report_err(local_err
);
1503 * The H_INT_RESET hcall() is used to reset all of the partition's
1504 * interrupt exploitation structures to their initial state. This
1505 * means losing all previously set interrupt state set via
1506 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1511 * Bits 0-63: Reserved
1516 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1517 SpaprMachineState
*spapr
,
1518 target_ulong opcode
,
1521 SpaprXive
*xive
= spapr
->xive
;
1522 target_ulong flags
= args
[0];
1524 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1532 device_reset(DEVICE(xive
));
1534 if (kvm_irqchip_in_kernel()) {
1535 Error
*local_err
= NULL
;
1537 kvmppc_xive_reset(xive
, &local_err
);
1539 error_report_err(local_err
);
1546 void spapr_xive_hcall_init(SpaprMachineState
*spapr
)
1548 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1549 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1550 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1551 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1552 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1553 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1554 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1555 h_int_set_os_reporting_line
);
1556 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1557 h_int_get_os_reporting_line
);
1558 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1559 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1560 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1563 void spapr_dt_xive(SpaprMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1566 SpaprXive
*xive
= spapr
->xive
;
1568 uint64_t timas
[2 * 2];
1569 /* Interrupt number ranges for the IPIs */
1570 uint32_t lisn_ranges
[] = {
1572 cpu_to_be32(nr_servers
),
1575 * EQ size - the sizes of pages supported by the system 4K, 64K,
1576 * 2M, 16M. We only advertise 64K for the moment.
1578 uint32_t eq_sizes
[] = {
1579 cpu_to_be32(16), /* 64K */
1582 * The following array is in sync with the reserved priorities
1583 * defined by the 'spapr_xive_priority_is_reserved' routine.
1585 uint32_t plat_res_int_priorities
[] = {
1586 cpu_to_be32(7), /* start */
1587 cpu_to_be32(0xf8), /* count */
1590 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1591 timas
[0] = cpu_to_be64(xive
->tm_base
+
1592 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1593 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1594 timas
[2] = cpu_to_be64(xive
->tm_base
+
1595 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1596 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1598 _FDT(node
= fdt_add_subnode(fdt
, 0, xive
->nodename
));
1600 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1601 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1603 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1604 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1606 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1607 sizeof(lisn_ranges
)));
1609 /* For Linux to link the LSIs to the interrupt controller. */
1610 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1611 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1614 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1615 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1618 * The "ibm,plat-res-int-priorities" property defines the priority
1619 * ranges reserved by the hypervisor
1621 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1622 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));