hw/misc/macio/cuda.c

   1 /*
   2  * QEMU PowerMac CUDA device support
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/ppc/mac.h"
  27 #include "hw/input/adb.h"
  28 #include "qemu/timer.h"
  29 #include "sysemu/sysemu.h"
  30
  31 /* XXX: implement all timer modes */
  32
  33 /* debug CUDA */
  34 //#define DEBUG_CUDA
  35
  36 /* debug CUDA packets */
  37 //#define DEBUG_CUDA_PACKET
  38
  39 #ifdef DEBUG_CUDA
  40 #define CUDA_DPRINTF(fmt, ...)                                  \
  41     do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0)
  42 #else
  43 #define CUDA_DPRINTF(fmt, ...)
  44 #endif
  45
  46 /* Bits in B data register: all active low */
  47 #define TREQ            0x08            /* Transfer request (input) */
  48 #define TACK            0x10            /* Transfer acknowledge (output) */
  49 #define TIP             0x20            /* Transfer in progress (output) */
  50
  51 /* Bits in ACR */
  52 #define SR_CTRL         0x1c            /* Shift register control bits */
  53 #define SR_EXT          0x0c            /* Shift on external clock */
  54 #define SR_OUT          0x10            /* Shift out if 1 */
  55
  56 /* Bits in IFR and IER */
  57 #define IER_SET         0x80            /* set bits in IER */
  58 #define IER_CLR         0               /* clear bits in IER */
  59 #define SR_INT          0x04            /* Shift register full/empty */
  60 #define SR_DATA_INT     0x08
  61 #define SR_CLOCK_INT    0x10
  62 #define T1_INT          0x40            /* Timer 1 interrupt */
  63 #define T2_INT          0x20            /* Timer 2 interrupt */
  64
  65 /* Bits in ACR */
  66 #define T1MODE          0xc0            /* Timer 1 mode */
  67 #define T1MODE_CONT     0x40            /*  continuous interrupts */
  68
  69 /* commands (1st byte) */
  70 #define ADB_PACKET      0
  71 #define CUDA_PACKET     1
  72 #define ERROR_PACKET    2
  73 #define TIMER_PACKET    3
  74 #define POWER_PACKET    4
  75 #define MACIIC_PACKET   5
  76 #define PMU_PACKET      6
  77
  78
  79 /* CUDA commands (2nd byte) */
  80 #define CUDA_WARM_START                 0x0
  81 #define CUDA_AUTOPOLL                   0x1
  82 #define CUDA_GET_6805_ADDR              0x2
  83 #define CUDA_GET_TIME                   0x3
  84 #define CUDA_GET_PRAM                   0x7
  85 #define CUDA_SET_6805_ADDR              0x8
  86 #define CUDA_SET_TIME                   0x9
  87 #define CUDA_POWERDOWN                  0xa
  88 #define CUDA_POWERUP_TIME               0xb
  89 #define CUDA_SET_PRAM                   0xc
  90 #define CUDA_MS_RESET                   0xd
  91 #define CUDA_SEND_DFAC                  0xe
  92 #define CUDA_BATTERY_SWAP_SENSE         0x10
  93 #define CUDA_RESET_SYSTEM               0x11
  94 #define CUDA_SET_IPL                    0x12
  95 #define CUDA_FILE_SERVER_FLAG           0x13
  96 #define CUDA_SET_AUTO_RATE              0x14
  97 #define CUDA_GET_AUTO_RATE              0x16
  98 #define CUDA_SET_DEVICE_LIST            0x19
  99 #define CUDA_GET_DEVICE_LIST            0x1a
 100 #define CUDA_SET_ONE_SECOND_MODE        0x1b
 101 #define CUDA_SET_POWER_MESSAGES         0x21
 102 #define CUDA_GET_SET_IIC                0x22
 103 #define CUDA_WAKEUP                     0x23
 104 #define CUDA_TIMER_TICKLE               0x24
 105 #define CUDA_COMBINED_FORMAT_IIC        0x25
 106
 107 #define CUDA_TIMER_FREQ (4700000 / 6)
 108 #define CUDA_ADB_POLL_FREQ 50
 109
 110 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
 111 #define RTC_OFFSET                      2082844800
 112
 113 /* CUDA registers */
 114 #define CUDA_REG_B       0x00
 115 #define CUDA_REG_A       0x01
 116 #define CUDA_REG_DIRB    0x02
 117 #define CUDA_REG_DIRA    0x03
 118 #define CUDA_REG_T1CL    0x04
 119 #define CUDA_REG_T1CH    0x05
 120 #define CUDA_REG_T1LL    0x06
 121 #define CUDA_REG_T1LH    0x07
 122 #define CUDA_REG_T2CL    0x08
 123 #define CUDA_REG_T2CH    0x09
 124 #define CUDA_REG_SR      0x0a
 125 #define CUDA_REG_ACR     0x0b
 126 #define CUDA_REG_PCR     0x0c
 127 #define CUDA_REG_IFR     0x0d
 128 #define CUDA_REG_IER     0x0e
 129 #define CUDA_REG_ANH     0x0f
 130
 131 static void cuda_update(CUDAState *s);
 132 static void cuda_receive_packet_from_host(CUDAState *s,
 133                                           const uint8_t *data, int len);
 134 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 135                               int64_t current_time);
 136
 137 static void cuda_update_irq(CUDAState *s)
 138 {
 139     if (s->ifr & s->ier & (SR_INT | T1_INT)) {
 140         qemu_irq_raise(s->irq);
 141     } else {
 142         qemu_irq_lower(s->irq);
 143     }
 144 }
 145
 146 static uint64_t get_tb(uint64_t time, uint64_t freq)
 147 {
 148     return muldiv64(time, freq, get_ticks_per_sec());
 149 }
 150
 151 static unsigned int get_counter(CUDATimer *ti)
 152 {
 153     int64_t d;
 154     unsigned int counter;
 155     uint64_t tb_diff;
 156     uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 157
 158     /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */
 159     tb_diff = get_tb(current_time, ti->frequency) - ti->load_time;
 160     d = (tb_diff * 0xBF401675E5DULL) / (ti->frequency << 24);
 161
 162     if (ti->index == 0) {
 163         /* the timer goes down from latch to -1 (period of latch + 2) */
 164         if (d <= (ti->counter_value + 1)) {
 165             counter = (ti->counter_value - d) & 0xffff;
 166         } else {
 167             counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
 168             counter = (ti->latch - counter) & 0xffff;
 169         }
 170     } else {
 171         counter = (ti->counter_value - d) & 0xffff;
 172     }
 173     return counter;
 174 }
 175
 176 static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
 177 {
 178     CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
 179     ti->load_time = get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 180                            s->frequency);
 181     ti->counter_value = val;
 182     cuda_timer_update(s, ti, ti->load_time);
 183 }
 184
 185 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
 186 {
 187     int64_t d, next_time;
 188     unsigned int counter;
 189
 190     /* current counter value */
 191     d = muldiv64(current_time - s->load_time,
 192                  CUDA_TIMER_FREQ, get_ticks_per_sec());
 193     /* the timer goes down from latch to -1 (period of latch + 2) */
 194     if (d <= (s->counter_value + 1)) {
 195         counter = (s->counter_value - d) & 0xffff;
 196     } else {
 197         counter = (d - (s->counter_value + 1)) % (s->latch + 2);
 198         counter = (s->latch - counter) & 0xffff;
 199     }
 200
 201     /* Note: we consider the irq is raised on 0 */
 202     if (counter == 0xffff) {
 203         next_time = d + s->latch + 1;
 204     } else if (counter == 0) {
 205         next_time = d + s->latch + 2;
 206     } else {
 207         next_time = d + counter;
 208     }
 209     CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
 210                  s->latch, d, next_time - d);
 211     next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) +
 212         s->load_time;
 213     if (next_time <= current_time)
 214         next_time = current_time + 1;
 215     return next_time;
 216 }
 217
 218 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 219                               int64_t current_time)
 220 {
 221     if (!ti->timer)
 222         return;
 223     if ((s->acr & T1MODE) != T1MODE_CONT) {
 224         timer_del(ti->timer);
 225     } else {
 226         ti->next_irq_time = get_next_irq_time(ti, current_time);
 227         timer_mod(ti->timer, ti->next_irq_time);
 228     }
 229 }
 230
 231 static void cuda_timer1(void *opaque)
 232 {
 233     CUDAState *s = opaque;
 234     CUDATimer *ti = &s->timers[0];
 235
 236     cuda_timer_update(s, ti, ti->next_irq_time);
 237     s->ifr |= T1_INT;
 238     cuda_update_irq(s);
 239 }
 240
 241 static uint32_t cuda_readb(void *opaque, hwaddr addr)
 242 {
 243     CUDAState *s = opaque;
 244     uint32_t val;
 245
 246     addr = (addr >> 9) & 0xf;
 247     switch(addr) {
 248     case CUDA_REG_B:
 249         val = s->b;
 250         break;
 251     case CUDA_REG_A:
 252         val = s->a;
 253         break;
 254     case CUDA_REG_DIRB:
 255         val = s->dirb;
 256         break;
 257     case CUDA_REG_DIRA:
 258         val = s->dira;
 259         break;
 260     case CUDA_REG_T1CL:
 261         val = get_counter(&s->timers[0]) & 0xff;
 262         s->ifr &= ~T1_INT;
 263         cuda_update_irq(s);
 264         break;
 265     case CUDA_REG_T1CH:
 266         val = get_counter(&s->timers[0]) >> 8;
 267         cuda_update_irq(s);
 268         break;
 269     case CUDA_REG_T1LL:
 270         val = s->timers[0].latch & 0xff;
 271         break;
 272     case CUDA_REG_T1LH:
 273         /* XXX: check this */
 274         val = (s->timers[0].latch >> 8) & 0xff;
 275         break;
 276     case CUDA_REG_T2CL:
 277         val = get_counter(&s->timers[1]) & 0xff;
 278         s->ifr &= ~T2_INT;
 279         break;
 280     case CUDA_REG_T2CH:
 281         val = get_counter(&s->timers[1]) >> 8;
 282         break;
 283     case CUDA_REG_SR:
 284         val = s->sr;
 285         s->ifr &= ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT);
 286         cuda_update_irq(s);
 287         break;
 288     case CUDA_REG_ACR:
 289         val = s->acr;
 290         break;
 291     case CUDA_REG_PCR:
 292         val = s->pcr;
 293         break;
 294     case CUDA_REG_IFR:
 295         val = s->ifr;
 296         if (s->ifr & s->ier) {
 297             val |= 0x80;
 298         }
 299         break;
 300     case CUDA_REG_IER:
 301         val = s->ier | 0x80;
 302         break;
 303     default:
 304     case CUDA_REG_ANH:
 305         val = s->anh;
 306         break;
 307     }
 308     if (addr != CUDA_REG_IFR || val != 0) {
 309         CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val);
 310     }
 311
 312     return val;
 313 }
 314
 315 static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
 316 {
 317     CUDAState *s = opaque;
 318
 319     addr = (addr >> 9) & 0xf;
 320     CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val);
 321
 322     switch(addr) {
 323     case CUDA_REG_B:
 324         s->b = val;
 325         cuda_update(s);
 326         break;
 327     case CUDA_REG_A:
 328         s->a = val;
 329         break;
 330     case CUDA_REG_DIRB:
 331         s->dirb = val;
 332         break;
 333     case CUDA_REG_DIRA:
 334         s->dira = val;
 335         break;
 336     case CUDA_REG_T1CL:
 337         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 338         cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 339         break;
 340     case CUDA_REG_T1CH:
 341         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 342         s->ifr &= ~T1_INT;
 343         set_counter(s, &s->timers[0], s->timers[0].latch);
 344         break;
 345     case CUDA_REG_T1LL:
 346         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 347         cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 348         break;
 349     case CUDA_REG_T1LH:
 350         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 351         s->ifr &= ~T1_INT;
 352         cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 353         break;
 354     case CUDA_REG_T2CL:
 355         s->timers[1].latch = val;
 356         set_counter(s, &s->timers[1], val);
 357         break;
 358     case CUDA_REG_T2CH:
 359         set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
 360         break;
 361     case CUDA_REG_SR:
 362         s->sr = val;
 363         break;
 364     case CUDA_REG_ACR:
 365         s->acr = val;
 366         cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 367         cuda_update(s);
 368         break;
 369     case CUDA_REG_PCR:
 370         s->pcr = val;
 371         break;
 372     case CUDA_REG_IFR:
 373         /* reset bits */
 374         s->ifr &= ~val;
 375         cuda_update_irq(s);
 376         break;
 377     case CUDA_REG_IER:
 378         if (val & IER_SET) {
 379             /* set bits */
 380             s->ier |= val & 0x7f;
 381         } else {
 382             /* reset bits */
 383             s->ier &= ~val;
 384         }
 385         cuda_update_irq(s);
 386         break;
 387     default:
 388     case CUDA_REG_ANH:
 389         s->anh = val;
 390         break;
 391     }
 392 }
 393
 394 /* NOTE: TIP and TREQ are negated */
 395 static void cuda_update(CUDAState *s)
 396 {
 397     int packet_received, len;
 398
 399     packet_received = 0;
 400     if (!(s->b & TIP)) {
 401         /* transfer requested from host */
 402
 403         if (s->acr & SR_OUT) {
 404             /* data output */
 405             if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 406                 if (s->data_out_index < sizeof(s->data_out)) {
 407                     CUDA_DPRINTF("send: %02x\n", s->sr);
 408                     s->data_out[s->data_out_index++] = s->sr;
 409                     s->ifr |= SR_INT;
 410                     cuda_update_irq(s);
 411                 }
 412             }
 413         } else {
 414             if (s->data_in_index < s->data_in_size) {
 415                 /* data input */
 416                 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 417                     s->sr = s->data_in[s->data_in_index++];
 418                     CUDA_DPRINTF("recv: %02x\n", s->sr);
 419                     /* indicate end of transfer */
 420                     if (s->data_in_index >= s->data_in_size) {
 421                         s->b = (s->b | TREQ);
 422                     }
 423                     s->ifr |= SR_INT;
 424                     cuda_update_irq(s);
 425                 }
 426             }
 427         }
 428     } else {
 429         /* no transfer requested: handle sync case */
 430         if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
 431             /* update TREQ state each time TACK change state */
 432             if (s->b & TACK)
 433                 s->b = (s->b | TREQ);
 434             else
 435                 s->b = (s->b & ~TREQ);
 436             s->ifr |= SR_INT;
 437             cuda_update_irq(s);
 438         } else {
 439             if (!(s->last_b & TIP)) {
 440                 /* handle end of host to cuda transfer */
 441                 packet_received = (s->data_out_index > 0);
 442                 /* always an IRQ at the end of transfer */
 443                 s->ifr |= SR_INT;
 444                 cuda_update_irq(s);
 445             }
 446             /* signal if there is data to read */
 447             if (s->data_in_index < s->data_in_size) {
 448                 s->b = (s->b & ~TREQ);
 449             }
 450         }
 451     }
 452
 453     s->last_acr = s->acr;
 454     s->last_b = s->b;
 455
 456     /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
 457        recursively */
 458     if (packet_received) {
 459         len = s->data_out_index;
 460         s->data_out_index = 0;
 461         cuda_receive_packet_from_host(s, s->data_out, len);
 462     }
 463 }
 464
 465 static void cuda_send_packet_to_host(CUDAState *s,
 466                                      const uint8_t *data, int len)
 467 {
 468 #ifdef DEBUG_CUDA_PACKET
 469     {
 470         int i;
 471         printf("cuda_send_packet_to_host:\n");
 472         for(i = 0; i < len; i++)
 473             printf(" %02x", data[i]);
 474         printf("\n");
 475     }
 476 #endif
 477     memcpy(s->data_in, data, len);
 478     s->data_in_size = len;
 479     s->data_in_index = 0;
 480     cuda_update(s);
 481     s->ifr |= SR_INT;
 482     cuda_update_irq(s);
 483 }
 484
 485 static void cuda_adb_poll(void *opaque)
 486 {
 487     CUDAState *s = opaque;
 488     uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 489     int olen;
 490
 491     olen = adb_poll(&s->adb_bus, obuf + 2);
 492     if (olen > 0) {
 493         obuf[0] = ADB_PACKET;
 494         obuf[1] = 0x40; /* polled data */
 495         cuda_send_packet_to_host(s, obuf, olen + 2);
 496     }
 497     timer_mod(s->adb_poll_timer,
 498                    qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 499                    (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
 500 }
 501
 502 static void cuda_receive_packet(CUDAState *s,
 503                                 const uint8_t *data, int len)
 504 {
 505     uint8_t obuf[16] = { CUDA_PACKET, 0, data[0] };
 506     int autopoll;
 507     uint32_t ti;
 508
 509     switch(data[0]) {
 510     case CUDA_AUTOPOLL:
 511         autopoll = (data[1] != 0);
 512         if (autopoll != s->autopoll) {
 513             s->autopoll = autopoll;
 514             if (autopoll) {
 515                 timer_mod(s->adb_poll_timer,
 516                                qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 517                                (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
 518             } else {
 519                 timer_del(s->adb_poll_timer);
 520             }
 521         }
 522         cuda_send_packet_to_host(s, obuf, 3);
 523         break;
 524     case CUDA_GET_6805_ADDR:
 525         cuda_send_packet_to_host(s, obuf, 3);
 526         break;
 527     case CUDA_SET_TIME:
 528         ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4];
 529         s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec());
 530         cuda_send_packet_to_host(s, obuf, 3);
 531         break;
 532     case CUDA_GET_TIME:
 533         ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec());
 534         obuf[3] = ti >> 24;
 535         obuf[4] = ti >> 16;
 536         obuf[5] = ti >> 8;
 537         obuf[6] = ti;
 538         cuda_send_packet_to_host(s, obuf, 7);
 539         break;
 540     case CUDA_FILE_SERVER_FLAG:
 541     case CUDA_SET_DEVICE_LIST:
 542     case CUDA_SET_AUTO_RATE:
 543     case CUDA_SET_POWER_MESSAGES:
 544         cuda_send_packet_to_host(s, obuf, 3);
 545         break;
 546     case CUDA_POWERDOWN:
 547         cuda_send_packet_to_host(s, obuf, 3);
 548         qemu_system_shutdown_request();
 549         break;
 550     case CUDA_RESET_SYSTEM:
 551         cuda_send_packet_to_host(s, obuf, 3);
 552         qemu_system_reset_request();
 553         break;
 554     case CUDA_COMBINED_FORMAT_IIC:
 555         obuf[0] = ERROR_PACKET;
 556         obuf[1] = 0x5;
 557         obuf[2] = CUDA_PACKET;
 558         obuf[3] = data[0];
 559         cuda_send_packet_to_host(s, obuf, 4);
 560         break;
 561     case CUDA_GET_SET_IIC:
 562         if (len == 4) {
 563             cuda_send_packet_to_host(s, obuf, 3);
 564         } else {
 565             obuf[0] = ERROR_PACKET;
 566             obuf[1] = 0x2;
 567             obuf[2] = CUDA_PACKET;
 568             obuf[3] = data[0];
 569             cuda_send_packet_to_host(s, obuf, 4);
 570         }
 571         break;
 572     default:
 573         break;
 574     }
 575 }
 576
 577 static void cuda_receive_packet_from_host(CUDAState *s,
 578                                           const uint8_t *data, int len)
 579 {
 580 #ifdef DEBUG_CUDA_PACKET
 581     {
 582         int i;
 583         printf("cuda_receive_packet_from_host:\n");
 584         for(i = 0; i < len; i++)
 585             printf(" %02x", data[i]);
 586         printf("\n");
 587     }
 588 #endif
 589     switch(data[0]) {
 590     case ADB_PACKET:
 591         {
 592             uint8_t obuf[ADB_MAX_OUT_LEN + 3];
 593             int olen;
 594             olen = adb_request(&s->adb_bus, obuf + 2, data + 1, len - 1);
 595             if (olen > 0) {
 596                 obuf[0] = ADB_PACKET;
 597                 obuf[1] = 0x00;
 598                 cuda_send_packet_to_host(s, obuf, olen + 2);
 599             } else {
 600                 /* error */
 601                 obuf[0] = ADB_PACKET;
 602                 obuf[1] = -olen;
 603                 obuf[2] = data[1];
 604                 olen = 0;
 605                 cuda_send_packet_to_host(s, obuf, olen + 3);
 606             }
 607         }
 608         break;
 609     case CUDA_PACKET:
 610         cuda_receive_packet(s, data + 1, len - 1);
 611         break;
 612     }
 613 }
 614
 615 static void cuda_writew (void *opaque, hwaddr addr, uint32_t value)
 616 {
 617 }
 618
 619 static void cuda_writel (void *opaque, hwaddr addr, uint32_t value)
 620 {
 621 }
 622
 623 static uint32_t cuda_readw (void *opaque, hwaddr addr)
 624 {
 625     return 0;
 626 }
 627
 628 static uint32_t cuda_readl (void *opaque, hwaddr addr)
 629 {
 630     return 0;
 631 }
 632
 633 static const MemoryRegionOps cuda_ops = {
 634     .old_mmio = {
 635         .write = {
 636             cuda_writeb,
 637             cuda_writew,
 638             cuda_writel,
 639         },
 640         .read = {
 641             cuda_readb,
 642             cuda_readw,
 643             cuda_readl,
 644         },
 645     },
 646     .endianness = DEVICE_NATIVE_ENDIAN,
 647 };
 648
 649 static bool cuda_timer_exist(void *opaque, int version_id)
 650 {
 651     CUDATimer *s = opaque;
 652
 653     return s->timer != NULL;
 654 }
 655
 656 static const VMStateDescription vmstate_cuda_timer = {
 657     .name = "cuda_timer",
 658     .version_id = 0,
 659     .minimum_version_id = 0,
 660     .fields = (VMStateField[]) {
 661         VMSTATE_UINT16(latch, CUDATimer),
 662         VMSTATE_UINT16(counter_value, CUDATimer),
 663         VMSTATE_INT64(load_time, CUDATimer),
 664         VMSTATE_INT64(next_irq_time, CUDATimer),
 665         VMSTATE_TIMER_PTR_TEST(timer, CUDATimer, cuda_timer_exist),
 666         VMSTATE_END_OF_LIST()
 667     }
 668 };
 669
 670 static const VMStateDescription vmstate_cuda = {
 671     .name = "cuda",
 672     .version_id = 2,
 673     .minimum_version_id = 2,
 674     .fields = (VMStateField[]) {
 675         VMSTATE_UINT8(a, CUDAState),
 676         VMSTATE_UINT8(b, CUDAState),
 677         VMSTATE_UINT8(dira, CUDAState),
 678         VMSTATE_UINT8(dirb, CUDAState),
 679         VMSTATE_UINT8(sr, CUDAState),
 680         VMSTATE_UINT8(acr, CUDAState),
 681         VMSTATE_UINT8(pcr, CUDAState),
 682         VMSTATE_UINT8(ifr, CUDAState),
 683         VMSTATE_UINT8(ier, CUDAState),
 684         VMSTATE_UINT8(anh, CUDAState),
 685         VMSTATE_INT32(data_in_size, CUDAState),
 686         VMSTATE_INT32(data_in_index, CUDAState),
 687         VMSTATE_INT32(data_out_index, CUDAState),
 688         VMSTATE_UINT8(autopoll, CUDAState),
 689         VMSTATE_BUFFER(data_in, CUDAState),
 690         VMSTATE_BUFFER(data_out, CUDAState),
 691         VMSTATE_UINT32(tick_offset, CUDAState),
 692         VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1,
 693                              vmstate_cuda_timer, CUDATimer),
 694         VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState),
 695         VMSTATE_END_OF_LIST()
 696     }
 697 };
 698
 699 static void cuda_reset(DeviceState *dev)
 700 {
 701     CUDAState *s = CUDA(dev);
 702
 703     s->b = 0;
 704     s->a = 0;
 705     s->dirb = 0;
 706     s->dira = 0;
 707     s->sr = 0;
 708     s->acr = 0;
 709     s->pcr = 0;
 710     s->ifr = 0;
 711     s->ier = 0;
 712     //    s->ier = T1_INT | SR_INT;
 713     s->anh = 0;
 714     s->data_in_size = 0;
 715     s->data_in_index = 0;
 716     s->data_out_index = 0;
 717     s->autopoll = 0;
 718
 719     s->timers[0].latch = 0xffff;
 720     set_counter(s, &s->timers[0], 0xffff);
 721
 722     s->timers[1].latch = 0;
 723     set_counter(s, &s->timers[1], 0xffff);
 724 }
 725
 726 static void cuda_realizefn(DeviceState *dev, Error **errp)
 727 {
 728     CUDAState *s = CUDA(dev);
 729     struct tm tm;
 730
 731     s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s);
 732     s->timers[0].frequency = s->frequency;
 733     s->timers[1].frequency = s->frequency;
 734
 735     qemu_get_timedate(&tm, 0);
 736     s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
 737
 738     s->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, s);
 739 }
 740
 741 static void cuda_initfn(Object *obj)
 742 {
 743     SysBusDevice *d = SYS_BUS_DEVICE(obj);
 744     CUDAState *s = CUDA(obj);
 745     int i;
 746
 747     memory_region_init_io(&s->mem, obj, &cuda_ops, s, "cuda", 0x2000);
 748     sysbus_init_mmio(d, &s->mem);
 749     sysbus_init_irq(d, &s->irq);
 750
 751     for (i = 0; i < ARRAY_SIZE(s->timers); i++) {
 752         s->timers[i].index = i;
 753     }
 754
 755     qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
 756                         DEVICE(obj), "adb.0");
 757 }
 758
 759 static Property cuda_properties[] = {
 760     DEFINE_PROP_UINT64("frequency", CUDAState, frequency, 0),
 761     DEFINE_PROP_END_OF_LIST()
 762 };
 763
 764 static void cuda_class_init(ObjectClass *oc, void *data)
 765 {
 766     DeviceClass *dc = DEVICE_CLASS(oc);
 767
 768     dc->realize = cuda_realizefn;
 769     dc->reset = cuda_reset;
 770     dc->vmsd = &vmstate_cuda;
 771     dc->props = cuda_properties;
 772     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 773 }
 774
 775 static const TypeInfo cuda_type_info = {
 776     .name = TYPE_CUDA,
 777     .parent = TYPE_SYS_BUS_DEVICE,
 778     .instance_size = sizeof(CUDAState),
 779     .instance_init = cuda_initfn,
 780     .class_init = cuda_class_init,
 781 };
 782
 783 static void cuda_register_types(void)
 784 {
 785     type_register_static(&cuda_type_info);
 786 }
 787
 788 type_init(cuda_register_types)