2 * QEMU PowerMac CUDA device support
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/ppc/mac.h"
28 #include "hw/input/adb.h"
29 #include "qemu/timer.h"
30 #include "sysemu/sysemu.h"
32 /* XXX: implement all timer modes */
37 /* debug CUDA packets */
38 //#define DEBUG_CUDA_PACKET
41 #define CUDA_DPRINTF(fmt, ...) \
42 do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0)
44 #define CUDA_DPRINTF(fmt, ...)
47 /* Bits in B data register: all active low */
48 #define TREQ 0x08 /* Transfer request (input) */
49 #define TACK 0x10 /* Transfer acknowledge (output) */
50 #define TIP 0x20 /* Transfer in progress (output) */
53 #define SR_CTRL 0x1c /* Shift register control bits */
54 #define SR_EXT 0x0c /* Shift on external clock */
55 #define SR_OUT 0x10 /* Shift out if 1 */
57 /* Bits in IFR and IER */
58 #define IER_SET 0x80 /* set bits in IER */
59 #define IER_CLR 0 /* clear bits in IER */
60 #define SR_INT 0x04 /* Shift register full/empty */
61 #define SR_DATA_INT 0x08
62 #define SR_CLOCK_INT 0x10
63 #define T1_INT 0x40 /* Timer 1 interrupt */
64 #define T2_INT 0x20 /* Timer 2 interrupt */
67 #define T1MODE 0xc0 /* Timer 1 mode */
68 #define T1MODE_CONT 0x40 /* continuous interrupts */
70 /* commands (1st byte) */
73 #define ERROR_PACKET 2
74 #define TIMER_PACKET 3
75 #define POWER_PACKET 4
76 #define MACIIC_PACKET 5
80 /* CUDA commands (2nd byte) */
81 #define CUDA_WARM_START 0x0
82 #define CUDA_AUTOPOLL 0x1
83 #define CUDA_GET_6805_ADDR 0x2
84 #define CUDA_GET_TIME 0x3
85 #define CUDA_GET_PRAM 0x7
86 #define CUDA_SET_6805_ADDR 0x8
87 #define CUDA_SET_TIME 0x9
88 #define CUDA_POWERDOWN 0xa
89 #define CUDA_POWERUP_TIME 0xb
90 #define CUDA_SET_PRAM 0xc
91 #define CUDA_MS_RESET 0xd
92 #define CUDA_SEND_DFAC 0xe
93 #define CUDA_BATTERY_SWAP_SENSE 0x10
94 #define CUDA_RESET_SYSTEM 0x11
95 #define CUDA_SET_IPL 0x12
96 #define CUDA_FILE_SERVER_FLAG 0x13
97 #define CUDA_SET_AUTO_RATE 0x14
98 #define CUDA_GET_AUTO_RATE 0x16
99 #define CUDA_SET_DEVICE_LIST 0x19
100 #define CUDA_GET_DEVICE_LIST 0x1a
101 #define CUDA_SET_ONE_SECOND_MODE 0x1b
102 #define CUDA_SET_POWER_MESSAGES 0x21
103 #define CUDA_GET_SET_IIC 0x22
104 #define CUDA_WAKEUP 0x23
105 #define CUDA_TIMER_TICKLE 0x24
106 #define CUDA_COMBINED_FORMAT_IIC 0x25
108 #define CUDA_TIMER_FREQ (4700000 / 6)
109 #define CUDA_ADB_POLL_FREQ 50
111 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
112 #define RTC_OFFSET 2082844800
115 #define CUDA_REG_B 0x00
116 #define CUDA_REG_A 0x01
117 #define CUDA_REG_DIRB 0x02
118 #define CUDA_REG_DIRA 0x03
119 #define CUDA_REG_T1CL 0x04
120 #define CUDA_REG_T1CH 0x05
121 #define CUDA_REG_T1LL 0x06
122 #define CUDA_REG_T1LH 0x07
123 #define CUDA_REG_T2CL 0x08
124 #define CUDA_REG_T2CH 0x09
125 #define CUDA_REG_SR 0x0a
126 #define CUDA_REG_ACR 0x0b
127 #define CUDA_REG_PCR 0x0c
128 #define CUDA_REG_IFR 0x0d
129 #define CUDA_REG_IER 0x0e
130 #define CUDA_REG_ANH 0x0f
132 static void cuda_update(CUDAState
*s
);
133 static void cuda_receive_packet_from_host(CUDAState
*s
,
134 const uint8_t *data
, int len
);
135 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
136 int64_t current_time
);
138 static void cuda_update_irq(CUDAState
*s
)
140 if (s
->ifr
& s
->ier
& (SR_INT
| T1_INT
| T2_INT
)) {
141 qemu_irq_raise(s
->irq
);
143 qemu_irq_lower(s
->irq
);
147 static uint64_t get_tb(uint64_t time
, uint64_t freq
)
149 return muldiv64(time
, freq
, get_ticks_per_sec());
152 static unsigned int get_counter(CUDATimer
*ti
)
155 unsigned int counter
;
157 uint64_t current_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
159 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */
160 tb_diff
= get_tb(current_time
, ti
->frequency
) - ti
->load_time
;
161 d
= (tb_diff
* 0xBF401675E5DULL
) / (ti
->frequency
<< 24);
163 if (ti
->index
== 0) {
164 /* the timer goes down from latch to -1 (period of latch + 2) */
165 if (d
<= (ti
->counter_value
+ 1)) {
166 counter
= (ti
->counter_value
- d
) & 0xffff;
168 counter
= (d
- (ti
->counter_value
+ 1)) % (ti
->latch
+ 2);
169 counter
= (ti
->latch
- counter
) & 0xffff;
172 counter
= (ti
->counter_value
- d
) & 0xffff;
177 static void set_counter(CUDAState
*s
, CUDATimer
*ti
, unsigned int val
)
179 CUDA_DPRINTF("T%d.counter=%d\n", 1 + ti
->index
, val
);
180 ti
->load_time
= get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
182 ti
->counter_value
= val
;
183 cuda_timer_update(s
, ti
, ti
->load_time
);
186 static int64_t get_next_irq_time(CUDATimer
*s
, int64_t current_time
)
188 int64_t d
, next_time
;
189 unsigned int counter
;
191 /* current counter value */
192 d
= muldiv64(current_time
- s
->load_time
,
193 CUDA_TIMER_FREQ
, get_ticks_per_sec());
194 /* the timer goes down from latch to -1 (period of latch + 2) */
195 if (d
<= (s
->counter_value
+ 1)) {
196 counter
= (s
->counter_value
- d
) & 0xffff;
198 counter
= (d
- (s
->counter_value
+ 1)) % (s
->latch
+ 2);
199 counter
= (s
->latch
- counter
) & 0xffff;
202 /* Note: we consider the irq is raised on 0 */
203 if (counter
== 0xffff) {
204 next_time
= d
+ s
->latch
+ 1;
205 } else if (counter
== 0) {
206 next_time
= d
+ s
->latch
+ 2;
208 next_time
= d
+ counter
;
210 CUDA_DPRINTF("latch=%d counter=%" PRId64
" delta_next=%" PRId64
"\n",
211 s
->latch
, d
, next_time
- d
);
212 next_time
= muldiv64(next_time
, get_ticks_per_sec(), CUDA_TIMER_FREQ
) +
214 if (next_time
<= current_time
)
215 next_time
= current_time
+ 1;
219 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
220 int64_t current_time
)
224 if (ti
->index
== 0 && (s
->acr
& T1MODE
) != T1MODE_CONT
) {
225 timer_del(ti
->timer
);
227 ti
->next_irq_time
= get_next_irq_time(ti
, current_time
);
228 timer_mod(ti
->timer
, ti
->next_irq_time
);
232 static void cuda_timer1(void *opaque
)
234 CUDAState
*s
= opaque
;
235 CUDATimer
*ti
= &s
->timers
[0];
237 cuda_timer_update(s
, ti
, ti
->next_irq_time
);
242 static void cuda_timer2(void *opaque
)
244 CUDAState
*s
= opaque
;
245 CUDATimer
*ti
= &s
->timers
[1];
247 cuda_timer_update(s
, ti
, ti
->next_irq_time
);
252 static void cuda_set_sr_int(void *opaque
)
254 CUDAState
*s
= opaque
;
256 CUDA_DPRINTF("CUDA: %s:%d\n", __func__
, __LINE__
);
261 static void cuda_delay_set_sr_int(CUDAState
*s
)
265 if (s
->dirb
== 0xff) {
266 /* Not in Mac OS, fire the IRQ directly */
271 CUDA_DPRINTF("CUDA: %s:%d\n", __func__
, __LINE__
);
273 expire
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 300 * SCALE_US
;
274 timer_mod(s
->sr_delay_timer
, expire
);
277 static uint32_t cuda_readb(void *opaque
, hwaddr addr
)
279 CUDAState
*s
= opaque
;
282 addr
= (addr
>> 9) & 0xf;
297 val
= get_counter(&s
->timers
[0]) & 0xff;
302 val
= get_counter(&s
->timers
[0]) >> 8;
306 val
= s
->timers
[0].latch
& 0xff;
309 /* XXX: check this */
310 val
= (s
->timers
[0].latch
>> 8) & 0xff;
313 val
= get_counter(&s
->timers
[1]) & 0xff;
318 val
= get_counter(&s
->timers
[1]) >> 8;
322 s
->ifr
&= ~(SR_INT
| SR_CLOCK_INT
| SR_DATA_INT
);
333 if (s
->ifr
& s
->ier
) {
345 if (addr
!= CUDA_REG_IFR
|| val
!= 0) {
346 CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr
, val
);
352 static void cuda_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
354 CUDAState
*s
= opaque
;
356 addr
= (addr
>> 9) & 0xf;
357 CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr
, val
);
374 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
375 cuda_timer_update(s
, &s
->timers
[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
378 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
380 set_counter(s
, &s
->timers
[0], s
->timers
[0].latch
);
383 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
384 cuda_timer_update(s
, &s
->timers
[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
387 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
389 cuda_timer_update(s
, &s
->timers
[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
392 s
->timers
[1].latch
= (s
->timers
[1].latch
& 0xff00) | val
;
395 /* To ensure T2 generates an interrupt on zero crossing with the
396 common timer code, write the value directly from the latch to
398 s
->timers
[1].latch
= (s
->timers
[1].latch
& 0xff) | (val
<< 8);
400 set_counter(s
, &s
->timers
[1], s
->timers
[1].latch
);
407 cuda_timer_update(s
, &s
->timers
[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
421 s
->ier
|= val
& 0x7f;
435 /* NOTE: TIP and TREQ are negated */
436 static void cuda_update(CUDAState
*s
)
438 int packet_received
, len
;
442 /* transfer requested from host */
444 if (s
->acr
& SR_OUT
) {
446 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
447 if (s
->data_out_index
< sizeof(s
->data_out
)) {
448 CUDA_DPRINTF("send: %02x\n", s
->sr
);
449 s
->data_out
[s
->data_out_index
++] = s
->sr
;
450 cuda_delay_set_sr_int(s
);
454 if (s
->data_in_index
< s
->data_in_size
) {
456 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
457 s
->sr
= s
->data_in
[s
->data_in_index
++];
458 CUDA_DPRINTF("recv: %02x\n", s
->sr
);
459 /* indicate end of transfer */
460 if (s
->data_in_index
>= s
->data_in_size
) {
461 s
->b
= (s
->b
| TREQ
);
463 cuda_delay_set_sr_int(s
);
468 /* no transfer requested: handle sync case */
469 if ((s
->last_b
& TIP
) && (s
->b
& TACK
) != (s
->last_b
& TACK
)) {
470 /* update TREQ state each time TACK change state */
472 s
->b
= (s
->b
| TREQ
);
474 s
->b
= (s
->b
& ~TREQ
);
475 cuda_delay_set_sr_int(s
);
477 if (!(s
->last_b
& TIP
)) {
478 /* handle end of host to cuda transfer */
479 packet_received
= (s
->data_out_index
> 0);
480 /* always an IRQ at the end of transfer */
481 cuda_delay_set_sr_int(s
);
483 /* signal if there is data to read */
484 if (s
->data_in_index
< s
->data_in_size
) {
485 s
->b
= (s
->b
& ~TREQ
);
490 s
->last_acr
= s
->acr
;
493 /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
495 if (packet_received
) {
496 len
= s
->data_out_index
;
497 s
->data_out_index
= 0;
498 cuda_receive_packet_from_host(s
, s
->data_out
, len
);
502 static void cuda_send_packet_to_host(CUDAState
*s
,
503 const uint8_t *data
, int len
)
505 #ifdef DEBUG_CUDA_PACKET
508 printf("cuda_send_packet_to_host:\n");
509 for(i
= 0; i
< len
; i
++)
510 printf(" %02x", data
[i
]);
514 memcpy(s
->data_in
, data
, len
);
515 s
->data_in_size
= len
;
516 s
->data_in_index
= 0;
518 cuda_delay_set_sr_int(s
);
521 static void cuda_adb_poll(void *opaque
)
523 CUDAState
*s
= opaque
;
524 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 2];
527 olen
= adb_poll(&s
->adb_bus
, obuf
+ 2);
529 obuf
[0] = ADB_PACKET
;
530 obuf
[1] = 0x40; /* polled data */
531 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
533 timer_mod(s
->adb_poll_timer
,
534 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
535 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ
));
538 /* description of commands */
539 typedef struct CudaCommand
{
542 bool (*handler
)(CUDAState
*s
,
543 const uint8_t *in_args
, int in_len
,
544 uint8_t *out_args
, int *out_len
);
547 static const CudaCommand handlers
[] = {
550 static void cuda_receive_packet(CUDAState
*s
,
551 const uint8_t *data
, int len
)
553 uint8_t obuf
[16] = { CUDA_PACKET
, 0, data
[0] };
558 for (i
= 0; i
< ARRAY_SIZE(handlers
); i
++) {
559 const CudaCommand
*desc
= &handlers
[i
];
560 if (desc
->command
== data
[0]) {
561 CUDA_DPRINTF("handling command %s\n", desc
->name
);
563 if (desc
->handler(s
, data
+ 1, len
- 1, obuf
+ 3, &out_len
)) {
564 cuda_send_packet_to_host(s
, obuf
, 3 + out_len
);
566 qemu_log_mask(LOG_GUEST_ERROR
,
567 "CUDA: %s: wrong parameters %d\n",
569 obuf
[0] = ERROR_PACKET
;
570 obuf
[1] = 0x5; /* bad parameters */
571 obuf
[2] = CUDA_PACKET
;
573 cuda_send_packet_to_host(s
, obuf
, 4);
581 autopoll
= (data
[1] != 0);
582 if (autopoll
!= s
->autopoll
) {
583 s
->autopoll
= autopoll
;
585 timer_mod(s
->adb_poll_timer
,
586 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
587 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ
));
589 timer_del(s
->adb_poll_timer
);
592 cuda_send_packet_to_host(s
, obuf
, 3);
594 case CUDA_GET_6805_ADDR
:
595 cuda_send_packet_to_host(s
, obuf
, 3);
598 ti
= (((uint32_t)data
[1]) << 24) + (((uint32_t)data
[2]) << 16) + (((uint32_t)data
[3]) << 8) + data
[4];
599 s
->tick_offset
= ti
- (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / get_ticks_per_sec());
600 cuda_send_packet_to_host(s
, obuf
, 3);
603 ti
= s
->tick_offset
+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / get_ticks_per_sec());
608 cuda_send_packet_to_host(s
, obuf
, 7);
610 case CUDA_FILE_SERVER_FLAG
:
611 case CUDA_SET_DEVICE_LIST
:
612 case CUDA_SET_AUTO_RATE
:
613 case CUDA_SET_POWER_MESSAGES
:
614 cuda_send_packet_to_host(s
, obuf
, 3);
617 cuda_send_packet_to_host(s
, obuf
, 3);
618 qemu_system_shutdown_request();
620 case CUDA_RESET_SYSTEM
:
621 cuda_send_packet_to_host(s
, obuf
, 3);
622 qemu_system_reset_request();
624 case CUDA_COMBINED_FORMAT_IIC
:
625 obuf
[0] = ERROR_PACKET
;
627 obuf
[2] = CUDA_PACKET
;
629 cuda_send_packet_to_host(s
, obuf
, 4);
631 case CUDA_GET_SET_IIC
:
633 cuda_send_packet_to_host(s
, obuf
, 3);
635 obuf
[0] = ERROR_PACKET
;
637 obuf
[2] = CUDA_PACKET
;
639 cuda_send_packet_to_host(s
, obuf
, 4);
646 qemu_log_mask(LOG_GUEST_ERROR
, "CUDA: unknown command 0x%02x\n", data
[0]);
647 obuf
[0] = ERROR_PACKET
;
648 obuf
[1] = 0x2; /* unknown command */
649 obuf
[2] = CUDA_PACKET
;
651 cuda_send_packet_to_host(s
, obuf
, 4);
654 static void cuda_receive_packet_from_host(CUDAState
*s
,
655 const uint8_t *data
, int len
)
657 #ifdef DEBUG_CUDA_PACKET
660 printf("cuda_receive_packet_from_host:\n");
661 for(i
= 0; i
< len
; i
++)
662 printf(" %02x", data
[i
]);
669 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 3];
671 olen
= adb_request(&s
->adb_bus
, obuf
+ 2, data
+ 1, len
- 1);
673 obuf
[0] = ADB_PACKET
;
675 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
678 obuf
[0] = ADB_PACKET
;
682 cuda_send_packet_to_host(s
, obuf
, olen
+ 3);
687 cuda_receive_packet(s
, data
+ 1, len
- 1);
692 static void cuda_writew (void *opaque
, hwaddr addr
, uint32_t value
)
696 static void cuda_writel (void *opaque
, hwaddr addr
, uint32_t value
)
700 static uint32_t cuda_readw (void *opaque
, hwaddr addr
)
705 static uint32_t cuda_readl (void *opaque
, hwaddr addr
)
710 static const MemoryRegionOps cuda_ops
= {
723 .endianness
= DEVICE_NATIVE_ENDIAN
,
726 static bool cuda_timer_exist(void *opaque
, int version_id
)
728 CUDATimer
*s
= opaque
;
730 return s
->timer
!= NULL
;
733 static const VMStateDescription vmstate_cuda_timer
= {
734 .name
= "cuda_timer",
736 .minimum_version_id
= 0,
737 .fields
= (VMStateField
[]) {
738 VMSTATE_UINT16(latch
, CUDATimer
),
739 VMSTATE_UINT16(counter_value
, CUDATimer
),
740 VMSTATE_INT64(load_time
, CUDATimer
),
741 VMSTATE_INT64(next_irq_time
, CUDATimer
),
742 VMSTATE_TIMER_PTR_TEST(timer
, CUDATimer
, cuda_timer_exist
),
743 VMSTATE_END_OF_LIST()
747 static const VMStateDescription vmstate_cuda
= {
750 .minimum_version_id
= 3,
751 .fields
= (VMStateField
[]) {
752 VMSTATE_UINT8(a
, CUDAState
),
753 VMSTATE_UINT8(b
, CUDAState
),
754 VMSTATE_UINT8(last_b
, CUDAState
),
755 VMSTATE_UINT8(dira
, CUDAState
),
756 VMSTATE_UINT8(dirb
, CUDAState
),
757 VMSTATE_UINT8(sr
, CUDAState
),
758 VMSTATE_UINT8(acr
, CUDAState
),
759 VMSTATE_UINT8(last_acr
, CUDAState
),
760 VMSTATE_UINT8(pcr
, CUDAState
),
761 VMSTATE_UINT8(ifr
, CUDAState
),
762 VMSTATE_UINT8(ier
, CUDAState
),
763 VMSTATE_UINT8(anh
, CUDAState
),
764 VMSTATE_INT32(data_in_size
, CUDAState
),
765 VMSTATE_INT32(data_in_index
, CUDAState
),
766 VMSTATE_INT32(data_out_index
, CUDAState
),
767 VMSTATE_UINT8(autopoll
, CUDAState
),
768 VMSTATE_BUFFER(data_in
, CUDAState
),
769 VMSTATE_BUFFER(data_out
, CUDAState
),
770 VMSTATE_UINT32(tick_offset
, CUDAState
),
771 VMSTATE_STRUCT_ARRAY(timers
, CUDAState
, 2, 1,
772 vmstate_cuda_timer
, CUDATimer
),
773 VMSTATE_TIMER_PTR(adb_poll_timer
, CUDAState
),
774 VMSTATE_TIMER_PTR(sr_delay_timer
, CUDAState
),
775 VMSTATE_END_OF_LIST()
779 static void cuda_reset(DeviceState
*dev
)
781 CUDAState
*s
= CUDA(dev
);
792 // s->ier = T1_INT | SR_INT;
795 s
->data_in_index
= 0;
796 s
->data_out_index
= 0;
799 s
->timers
[0].latch
= 0xffff;
800 set_counter(s
, &s
->timers
[0], 0xffff);
802 s
->timers
[1].latch
= 0xffff;
804 s
->sr_delay_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cuda_set_sr_int
, s
);
807 static void cuda_realizefn(DeviceState
*dev
, Error
**errp
)
809 CUDAState
*s
= CUDA(dev
);
812 s
->timers
[0].timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cuda_timer1
, s
);
813 s
->timers
[0].frequency
= s
->frequency
;
814 s
->timers
[1].timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cuda_timer2
, s
);
815 s
->timers
[1].frequency
= (SCALE_US
* 6000) / 4700;
817 qemu_get_timedate(&tm
, 0);
818 s
->tick_offset
= (uint32_t)mktimegm(&tm
) + RTC_OFFSET
;
820 s
->adb_poll_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cuda_adb_poll
, s
);
823 static void cuda_initfn(Object
*obj
)
825 SysBusDevice
*d
= SYS_BUS_DEVICE(obj
);
826 CUDAState
*s
= CUDA(obj
);
829 memory_region_init_io(&s
->mem
, obj
, &cuda_ops
, s
, "cuda", 0x2000);
830 sysbus_init_mmio(d
, &s
->mem
);
831 sysbus_init_irq(d
, &s
->irq
);
833 for (i
= 0; i
< ARRAY_SIZE(s
->timers
); i
++) {
834 s
->timers
[i
].index
= i
;
837 qbus_create_inplace(&s
->adb_bus
, sizeof(s
->adb_bus
), TYPE_ADB_BUS
,
838 DEVICE(obj
), "adb.0");
841 static Property cuda_properties
[] = {
842 DEFINE_PROP_UINT64("frequency", CUDAState
, frequency
, 0),
843 DEFINE_PROP_END_OF_LIST()
846 static void cuda_class_init(ObjectClass
*oc
, void *data
)
848 DeviceClass
*dc
= DEVICE_CLASS(oc
);
850 dc
->realize
= cuda_realizefn
;
851 dc
->reset
= cuda_reset
;
852 dc
->vmsd
= &vmstate_cuda
;
853 dc
->props
= cuda_properties
;
854 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
857 static const TypeInfo cuda_type_info
= {
859 .parent
= TYPE_SYS_BUS_DEVICE
,
860 .instance_size
= sizeof(CUDAState
),
861 .instance_init
= cuda_initfn
,
862 .class_init
= cuda_class_init
,
865 static void cuda_register_types(void)
867 type_register_static(&cuda_type_info
);
870 type_init(cuda_register_types
)