]> git.ipfire.org Git - thirdparty/qemu.git/blob - hw/pci-host/piix.c
hw/pci-host/piix: Fix code style issues
[thirdparty/qemu.git] / hw / pci-host / piix.c
1 /*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/i386/pc.h"
27 #include "hw/irq.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/pci-host/i440fx.h"
31 #include "hw/southbridge/piix.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/isa/isa.h"
34 #include "hw/sysbus.h"
35 #include "qapi/error.h"
36 #include "qemu/range.h"
37 #include "hw/xen/xen.h"
38 #include "migration/vmstate.h"
39 #include "hw/pci-host/pam.h"
40 #include "sysemu/reset.h"
41 #include "sysemu/runstate.h"
42 #include "hw/i386/ioapic.h"
43 #include "qapi/visitor.h"
44 #include "qemu/error-report.h"
45
46 /*
47 * I440FX chipset data sheet.
48 * https://wiki.qemu.org/File:29054901.pdf
49 */
50
51 #define I440FX_PCI_HOST_BRIDGE(obj) \
52 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
53
54 typedef struct I440FXState {
55 PCIHostState parent_obj;
56 Range pci_hole;
57 uint64_t pci_hole64_size;
58 bool pci_hole64_fix;
59 uint32_t short_root_bus;
60 } I440FXState;
61
62 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
63 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
64 #define XEN_PIIX_NUM_PIRQS 128ULL
65
66 typedef struct PIIX3State {
67 PCIDevice dev;
68
69 /*
70 * bitmap to track pic levels.
71 * The pic level is the logical OR of all the PCI irqs mapped to it
72 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
73 *
74 * PIRQ is mapped to PIC pins, we track it by
75 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
76 * pic_irq * PIIX_NUM_PIRQS + pirq
77 */
78 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
79 #error "unable to encode pic state in 64bit in pic_levels."
80 #endif
81 uint64_t pic_levels;
82
83 qemu_irq *pic;
84
85 /* This member isn't used. Just for save/load compatibility */
86 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
87
88 /* Reset Control Register contents */
89 uint8_t rcr;
90
91 /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
92 MemoryRegion rcr_mem;
93 } PIIX3State;
94
95 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
96 #define PIIX3_PCI_DEVICE(obj) \
97 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
98
99 #define I440FX_PCI_DEVICE(obj) \
100 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
101
102 #define TYPE_PIIX3_DEVICE "PIIX3"
103 #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
104
105 struct PCII440FXState {
106 /*< private >*/
107 PCIDevice parent_obj;
108 /*< public >*/
109
110 MemoryRegion *system_memory;
111 MemoryRegion *pci_address_space;
112 MemoryRegion *ram_memory;
113 PAMMemoryRegion pam_regions[13];
114 MemoryRegion smram_region;
115 MemoryRegion smram, low_smram;
116 };
117
118
119 #define I440FX_PAM 0x59
120 #define I440FX_PAM_SIZE 7
121 #define I440FX_SMRAM 0x72
122
123 /* Keep it 2G to comply with older win32 guests */
124 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
125
126 /* Older coreboot versions (4.0 and older) read a config register that doesn't
127 * exist in real hardware, to get the RAM size from QEMU.
128 */
129 #define I440FX_COREBOOT_RAM_SIZE 0x57
130
131 static void piix3_set_irq(void *opaque, int pirq, int level);
132 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
133 static void piix3_write_config_xen(PCIDevice *dev,
134 uint32_t address, uint32_t val, int len);
135
136 /*
137 * Return the global irq number corresponding to a given device irq
138 * pin. We could also use the bus number to have a more precise mapping.
139 */
140 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
141 {
142 int slot_addend;
143 slot_addend = (pci_dev->devfn >> 3) - 1;
144 return (pci_intx + slot_addend) & 3;
145 }
146
147 static void i440fx_update_memory_mappings(PCII440FXState *d)
148 {
149 int i;
150 PCIDevice *pd = PCI_DEVICE(d);
151
152 memory_region_transaction_begin();
153 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
154 pam_update(&d->pam_regions[i], i,
155 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
156 }
157 memory_region_set_enabled(&d->smram_region,
158 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
159 memory_region_set_enabled(&d->smram,
160 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
161 memory_region_transaction_commit();
162 }
163
164
165 static void i440fx_write_config(PCIDevice *dev,
166 uint32_t address, uint32_t val, int len)
167 {
168 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
169
170 /* XXX: implement SMRAM.D_LOCK */
171 pci_default_write_config(dev, address, val, len);
172 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
173 range_covers_byte(address, len, I440FX_SMRAM)) {
174 i440fx_update_memory_mappings(d);
175 }
176 }
177
178 static int i440fx_post_load(void *opaque, int version_id)
179 {
180 PCII440FXState *d = opaque;
181
182 i440fx_update_memory_mappings(d);
183 return 0;
184 }
185
186 static const VMStateDescription vmstate_i440fx = {
187 .name = "I440FX",
188 .version_id = 3,
189 .minimum_version_id = 3,
190 .post_load = i440fx_post_load,
191 .fields = (VMStateField[]) {
192 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
193 /* Used to be smm_enabled, which was basically always zero because
194 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
195 */
196 VMSTATE_UNUSED(1),
197 VMSTATE_END_OF_LIST()
198 }
199 };
200
201 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
202 const char *name, void *opaque,
203 Error **errp)
204 {
205 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
206 uint64_t val64;
207 uint32_t value;
208
209 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
210 value = val64;
211 assert(value == val64);
212 visit_type_uint32(v, name, &value, errp);
213 }
214
215 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
216 const char *name, void *opaque,
217 Error **errp)
218 {
219 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
220 uint64_t val64;
221 uint32_t value;
222
223 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
224 value = val64;
225 assert(value == val64);
226 visit_type_uint32(v, name, &value, errp);
227 }
228
229 /*
230 * The 64bit PCI hole start is set by the Guest firmware
231 * as the address of the first 64bit PCI MEM resource.
232 * If no PCI device has resources on the 64bit area,
233 * the 64bit PCI hole will start after "over 4G RAM" and the
234 * reserved space for memory hotplug if any.
235 */
236 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
237 {
238 PCIHostState *h = PCI_HOST_BRIDGE(obj);
239 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
240 Range w64;
241 uint64_t value;
242
243 pci_bus_get_w64_range(h->bus, &w64);
244 value = range_is_empty(&w64) ? 0 : range_lob(&w64);
245 if (!value && s->pci_hole64_fix) {
246 value = pc_pci_hole64_start();
247 }
248 return value;
249 }
250
251 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
252 const char *name,
253 void *opaque, Error **errp)
254 {
255 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
256
257 visit_type_uint64(v, name, &hole64_start, errp);
258 }
259
260 /*
261 * The 64bit PCI hole end is set by the Guest firmware
262 * as the address of the last 64bit PCI MEM resource.
263 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
264 * that can be configured by the user.
265 */
266 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
267 const char *name, void *opaque,
268 Error **errp)
269 {
270 PCIHostState *h = PCI_HOST_BRIDGE(obj);
271 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
272 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
273 Range w64;
274 uint64_t value, hole64_end;
275
276 pci_bus_get_w64_range(h->bus, &w64);
277 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
278 hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
279 if (s->pci_hole64_fix && value < hole64_end) {
280 value = hole64_end;
281 }
282 visit_type_uint64(v, name, &value, errp);
283 }
284
285 static void i440fx_pcihost_initfn(Object *obj)
286 {
287 PCIHostState *s = PCI_HOST_BRIDGE(obj);
288
289 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
290 "pci-conf-idx", 4);
291 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
292 "pci-conf-data", 4);
293
294 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
295 i440fx_pcihost_get_pci_hole_start,
296 NULL, NULL, NULL, NULL);
297
298 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
299 i440fx_pcihost_get_pci_hole_end,
300 NULL, NULL, NULL, NULL);
301
302 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
303 i440fx_pcihost_get_pci_hole64_start,
304 NULL, NULL, NULL, NULL);
305
306 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
307 i440fx_pcihost_get_pci_hole64_end,
308 NULL, NULL, NULL, NULL);
309 }
310
311 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
312 {
313 PCIHostState *s = PCI_HOST_BRIDGE(dev);
314 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
315
316 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
317 sysbus_init_ioports(sbd, 0xcf8, 4);
318
319 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
320 sysbus_init_ioports(sbd, 0xcfc, 4);
321
322 /* register i440fx 0xcf8 port as coalesced pio */
323 memory_region_set_flush_coalesced(&s->data_mem);
324 memory_region_add_coalescing(&s->conf_mem, 0, 4);
325 }
326
327 static void i440fx_realize(PCIDevice *dev, Error **errp)
328 {
329 dev->config[I440FX_SMRAM] = 0x02;
330
331 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
332 warn_report("i440fx doesn't support emulated iommu");
333 }
334 }
335
336 static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
337 {
338 PIIX3State *piix3;
339 PCIDevice *pci_dev;
340
341 /*
342 * Xen supports additional interrupt routes from the PCI devices to
343 * the IOAPIC: the four pins of each PCI device on the bus are also
344 * connected to the IOAPIC directly.
345 * These additional routes can be discovered through ACPI.
346 */
347 if (xen_enabled()) {
348 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
349 TYPE_PIIX3_XEN_DEVICE);
350 piix3 = PIIX3_PCI_DEVICE(pci_dev);
351 pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
352 piix3, XEN_PIIX_NUM_PIRQS);
353 } else {
354 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
355 TYPE_PIIX3_DEVICE);
356 piix3 = PIIX3_PCI_DEVICE(pci_dev);
357 pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
358 piix3, PIIX_NUM_PIRQS);
359 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
360 }
361 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
362
363 return piix3;
364 }
365
366 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
367 PCII440FXState **pi440fx_state,
368 int *piix3_devfn,
369 ISABus **isa_bus, qemu_irq *pic,
370 MemoryRegion *address_space_mem,
371 MemoryRegion *address_space_io,
372 ram_addr_t ram_size,
373 ram_addr_t below_4g_mem_size,
374 ram_addr_t above_4g_mem_size,
375 MemoryRegion *pci_address_space,
376 MemoryRegion *ram_memory)
377 {
378 DeviceState *dev;
379 PCIBus *b;
380 PCIDevice *d;
381 PCIHostState *s;
382 PIIX3State *piix3;
383 PCII440FXState *f;
384 unsigned i;
385 I440FXState *i440fx;
386
387 dev = qdev_create(NULL, host_type);
388 s = PCI_HOST_BRIDGE(dev);
389 b = pci_root_bus_new(dev, NULL, pci_address_space,
390 address_space_io, 0, TYPE_PCI_BUS);
391 s->bus = b;
392 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
393 qdev_init_nofail(dev);
394
395 d = pci_create_simple(b, 0, pci_type);
396 *pi440fx_state = I440FX_PCI_DEVICE(d);
397 f = *pi440fx_state;
398 f->system_memory = address_space_mem;
399 f->pci_address_space = pci_address_space;
400 f->ram_memory = ram_memory;
401
402 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
403 range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
404 IO_APIC_DEFAULT_ADDRESS - 1);
405
406 /* setup pci memory mapping */
407 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
408 f->pci_address_space);
409
410 /* if *disabled* show SMRAM to all CPUs */
411 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
412 f->pci_address_space, 0xa0000, 0x20000);
413 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
414 &f->smram_region, 1);
415 memory_region_set_enabled(&f->smram_region, true);
416
417 /* smram, as seen by SMM CPUs */
418 memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
419 memory_region_set_enabled(&f->smram, true);
420 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
421 f->ram_memory, 0xa0000, 0x20000);
422 memory_region_set_enabled(&f->low_smram, true);
423 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
424 object_property_add_const_link(qdev_get_machine(), "smram",
425 OBJECT(&f->smram), &error_abort);
426
427 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
428 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
429 for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
430 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
431 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
432 PAM_EXPAN_SIZE);
433 }
434
435 piix3 = piix3_create(b, isa_bus);
436 piix3->pic = pic;
437 *piix3_devfn = piix3->dev.devfn;
438
439 ram_size = ram_size / 8 / 1024 / 1024;
440 if (ram_size > 255) {
441 ram_size = 255;
442 }
443 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
444
445 i440fx_update_memory_mappings(f);
446
447 return b;
448 }
449
450 PCIBus *find_i440fx(void)
451 {
452 PCIHostState *s = OBJECT_CHECK(PCIHostState,
453 object_resolve_path("/machine/i440fx", NULL),
454 TYPE_PCI_HOST_BRIDGE);
455 return s ? s->bus : NULL;
456 }
457
458 /* PIIX3 PCI to ISA bridge */
459 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
460 {
461 qemu_set_irq(piix3->pic[pic_irq],
462 !!(piix3->pic_levels &
463 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
464 (pic_irq * PIIX_NUM_PIRQS))));
465 }
466
467 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
468 {
469 int pic_irq;
470 uint64_t mask;
471
472 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
473 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
474 return;
475 }
476
477 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
478 piix3->pic_levels &= ~mask;
479 piix3->pic_levels |= mask * !!level;
480 }
481
482 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
483 {
484 int pic_irq;
485
486 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
487 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
488 return;
489 }
490
491 piix3_set_irq_level_internal(piix3, pirq, level);
492
493 piix3_set_irq_pic(piix3, pic_irq);
494 }
495
496 static void piix3_set_irq(void *opaque, int pirq, int level)
497 {
498 PIIX3State *piix3 = opaque;
499 piix3_set_irq_level(piix3, pirq, level);
500 }
501
502 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
503 {
504 PIIX3State *piix3 = opaque;
505 int irq = piix3->dev.config[PIIX_PIRQCA + pin];
506 PCIINTxRoute route;
507
508 if (irq < PIIX_NUM_PIC_IRQS) {
509 route.mode = PCI_INTX_ENABLED;
510 route.irq = irq;
511 } else {
512 route.mode = PCI_INTX_DISABLED;
513 route.irq = -1;
514 }
515 return route;
516 }
517
518 /* irq routing is changed. so rebuild bitmap */
519 static void piix3_update_irq_levels(PIIX3State *piix3)
520 {
521 PCIBus *bus = pci_get_bus(&piix3->dev);
522 int pirq;
523
524 piix3->pic_levels = 0;
525 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
526 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
527 }
528 }
529
530 static void piix3_write_config(PCIDevice *dev,
531 uint32_t address, uint32_t val, int len)
532 {
533 pci_default_write_config(dev, address, val, len);
534 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
535 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
536 int pic_irq;
537
538 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
539 piix3_update_irq_levels(piix3);
540 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
541 piix3_set_irq_pic(piix3, pic_irq);
542 }
543 }
544 }
545
546 static void piix3_write_config_xen(PCIDevice *dev,
547 uint32_t address, uint32_t val, int len)
548 {
549 xen_piix_pci_write_config_client(address, val, len);
550 piix3_write_config(dev, address, val, len);
551 }
552
553 static void piix3_reset(void *opaque)
554 {
555 PIIX3State *d = opaque;
556 uint8_t *pci_conf = d->dev.config;
557
558 pci_conf[0x04] = 0x07; /* master, memory and I/O */
559 pci_conf[0x05] = 0x00;
560 pci_conf[0x06] = 0x00;
561 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
562 pci_conf[0x4c] = 0x4d;
563 pci_conf[0x4e] = 0x03;
564 pci_conf[0x4f] = 0x00;
565 pci_conf[0x60] = 0x80;
566 pci_conf[0x61] = 0x80;
567 pci_conf[0x62] = 0x80;
568 pci_conf[0x63] = 0x80;
569 pci_conf[0x69] = 0x02;
570 pci_conf[0x70] = 0x80;
571 pci_conf[0x76] = 0x0c;
572 pci_conf[0x77] = 0x0c;
573 pci_conf[0x78] = 0x02;
574 pci_conf[0x79] = 0x00;
575 pci_conf[0x80] = 0x00;
576 pci_conf[0x82] = 0x00;
577 pci_conf[0xa0] = 0x08;
578 pci_conf[0xa2] = 0x00;
579 pci_conf[0xa3] = 0x00;
580 pci_conf[0xa4] = 0x00;
581 pci_conf[0xa5] = 0x00;
582 pci_conf[0xa6] = 0x00;
583 pci_conf[0xa7] = 0x00;
584 pci_conf[0xa8] = 0x0f;
585 pci_conf[0xaa] = 0x00;
586 pci_conf[0xab] = 0x00;
587 pci_conf[0xac] = 0x00;
588 pci_conf[0xae] = 0x00;
589
590 d->pic_levels = 0;
591 d->rcr = 0;
592 }
593
594 static int piix3_post_load(void *opaque, int version_id)
595 {
596 PIIX3State *piix3 = opaque;
597 int pirq;
598
599 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
600 * might bring the system to a different state than the saved one;
601 * for example, the interrupt could be masked but the i8259 would
602 * not know that yet and would trigger an interrupt in the CPU.
603 *
604 * Here, we update irq levels without raising the interrupt.
605 * Interrupt state will be deserialized separately through the i8259.
606 */
607 piix3->pic_levels = 0;
608 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
609 piix3_set_irq_level_internal(piix3, pirq,
610 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
611 }
612 return 0;
613 }
614
615 static int piix3_pre_save(void *opaque)
616 {
617 int i;
618 PIIX3State *piix3 = opaque;
619
620 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
621 piix3->pci_irq_levels_vmstate[i] =
622 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
623 }
624
625 return 0;
626 }
627
628 static bool piix3_rcr_needed(void *opaque)
629 {
630 PIIX3State *piix3 = opaque;
631
632 return (piix3->rcr != 0);
633 }
634
635 static const VMStateDescription vmstate_piix3_rcr = {
636 .name = "PIIX3/rcr",
637 .version_id = 1,
638 .minimum_version_id = 1,
639 .needed = piix3_rcr_needed,
640 .fields = (VMStateField[]) {
641 VMSTATE_UINT8(rcr, PIIX3State),
642 VMSTATE_END_OF_LIST()
643 }
644 };
645
646 static const VMStateDescription vmstate_piix3 = {
647 .name = "PIIX3",
648 .version_id = 3,
649 .minimum_version_id = 2,
650 .post_load = piix3_post_load,
651 .pre_save = piix3_pre_save,
652 .fields = (VMStateField[]) {
653 VMSTATE_PCI_DEVICE(dev, PIIX3State),
654 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
655 PIIX_NUM_PIRQS, 3),
656 VMSTATE_END_OF_LIST()
657 },
658 .subsections = (const VMStateDescription*[]) {
659 &vmstate_piix3_rcr,
660 NULL
661 }
662 };
663
664
665 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
666 {
667 PIIX3State *d = opaque;
668
669 if (val & 4) {
670 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
671 return;
672 }
673 d->rcr = val & 2; /* keep System Reset type only */
674 }
675
676 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
677 {
678 PIIX3State *d = opaque;
679
680 return d->rcr;
681 }
682
683 static const MemoryRegionOps rcr_ops = {
684 .read = rcr_read,
685 .write = rcr_write,
686 .endianness = DEVICE_LITTLE_ENDIAN
687 };
688
689 static void piix3_realize(PCIDevice *dev, Error **errp)
690 {
691 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
692
693 if (!isa_bus_new(DEVICE(d), get_system_memory(),
694 pci_address_space_io(dev), errp)) {
695 return;
696 }
697
698 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
699 "piix3-reset-control", 1);
700 memory_region_add_subregion_overlap(pci_address_space_io(dev),
701 PIIX_RCR_IOPORT, &d->rcr_mem, 1);
702
703 qemu_register_reset(piix3_reset, d);
704 }
705
706 static void pci_piix3_class_init(ObjectClass *klass, void *data)
707 {
708 DeviceClass *dc = DEVICE_CLASS(klass);
709 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
710
711 dc->desc = "ISA bridge";
712 dc->vmsd = &vmstate_piix3;
713 dc->hotpluggable = false;
714 k->realize = piix3_realize;
715 k->vendor_id = PCI_VENDOR_ID_INTEL;
716 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
717 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
718 k->class_id = PCI_CLASS_BRIDGE_ISA;
719 /*
720 * Reason: part of PIIX3 southbridge, needs to be wired up by
721 * pc_piix.c's pc_init1()
722 */
723 dc->user_creatable = false;
724 }
725
726 static const TypeInfo piix3_pci_type_info = {
727 .name = TYPE_PIIX3_PCI_DEVICE,
728 .parent = TYPE_PCI_DEVICE,
729 .instance_size = sizeof(PIIX3State),
730 .abstract = true,
731 .class_init = pci_piix3_class_init,
732 .interfaces = (InterfaceInfo[]) {
733 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
734 { },
735 },
736 };
737
738 static void piix3_class_init(ObjectClass *klass, void *data)
739 {
740 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
741
742 k->config_write = piix3_write_config;
743 }
744
745 static const TypeInfo piix3_info = {
746 .name = TYPE_PIIX3_DEVICE,
747 .parent = TYPE_PIIX3_PCI_DEVICE,
748 .class_init = piix3_class_init,
749 };
750
751 static void piix3_xen_class_init(ObjectClass *klass, void *data)
752 {
753 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
754
755 k->config_write = piix3_write_config_xen;
756 };
757
758 static const TypeInfo piix3_xen_info = {
759 .name = TYPE_PIIX3_XEN_DEVICE,
760 .parent = TYPE_PIIX3_PCI_DEVICE,
761 .class_init = piix3_xen_class_init,
762 };
763
764 static void i440fx_class_init(ObjectClass *klass, void *data)
765 {
766 DeviceClass *dc = DEVICE_CLASS(klass);
767 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
768
769 k->realize = i440fx_realize;
770 k->config_write = i440fx_write_config;
771 k->vendor_id = PCI_VENDOR_ID_INTEL;
772 k->device_id = PCI_DEVICE_ID_INTEL_82441;
773 k->revision = 0x02;
774 k->class_id = PCI_CLASS_BRIDGE_HOST;
775 dc->desc = "Host bridge";
776 dc->vmsd = &vmstate_i440fx;
777 /*
778 * PCI-facing part of the host bridge, not usable without the
779 * host-facing part, which can't be device_add'ed, yet.
780 */
781 dc->user_creatable = false;
782 dc->hotpluggable = false;
783 }
784
785 static const TypeInfo i440fx_info = {
786 .name = TYPE_I440FX_PCI_DEVICE,
787 .parent = TYPE_PCI_DEVICE,
788 .instance_size = sizeof(PCII440FXState),
789 .class_init = i440fx_class_init,
790 .interfaces = (InterfaceInfo[]) {
791 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
792 { },
793 },
794 };
795
796 /* IGD Passthrough Host Bridge. */
797 typedef struct {
798 uint8_t offset;
799 uint8_t len;
800 } IGDHostInfo;
801
802 /* Here we just expose minimal host bridge offset subset. */
803 static const IGDHostInfo igd_host_bridge_infos[] = {
804 {0x08, 2}, /* revision id */
805 {0x2c, 2}, /* sybsystem vendor id */
806 {0x2e, 2}, /* sybsystem id */
807 {0x50, 2}, /* SNB: processor graphics control register */
808 {0x52, 2}, /* processor graphics control register */
809 {0xa4, 4}, /* SNB: graphics base of stolen memory */
810 {0xa8, 4}, /* SNB: base of GTT stolen memory */
811 };
812
813 static void host_pci_config_read(int pos, int len, uint32_t *val, Error **errp)
814 {
815 int rc, config_fd;
816 /* Access real host bridge. */
817 char *path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
818 0, 0, 0, 0, "config");
819
820 config_fd = open(path, O_RDWR);
821 if (config_fd < 0) {
822 error_setg_errno(errp, errno, "Failed to open: %s", path);
823 goto out;
824 }
825
826 if (lseek(config_fd, pos, SEEK_SET) != pos) {
827 error_setg_errno(errp, errno, "Failed to seek: %s", path);
828 goto out_close_fd;
829 }
830
831 do {
832 rc = read(config_fd, (uint8_t *)val, len);
833 } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
834 if (rc != len) {
835 error_setg_errno(errp, errno, "Failed to read: %s", path);
836 }
837
838 out_close_fd:
839 close(config_fd);
840 out:
841 g_free(path);
842 }
843
844 static void igd_pt_i440fx_realize(PCIDevice *pci_dev, Error **errp)
845 {
846 uint32_t val = 0;
847 int i, num;
848 int pos, len;
849 Error *local_err = NULL;
850
851 num = ARRAY_SIZE(igd_host_bridge_infos);
852 for (i = 0; i < num; i++) {
853 pos = igd_host_bridge_infos[i].offset;
854 len = igd_host_bridge_infos[i].len;
855 host_pci_config_read(pos, len, &val, &local_err);
856 if (local_err) {
857 error_propagate(errp, local_err);
858 return;
859 }
860 pci_default_write_config(pci_dev, pos, val, len);
861 }
862 }
863
864 static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
865 {
866 DeviceClass *dc = DEVICE_CLASS(klass);
867 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
868
869 k->realize = igd_pt_i440fx_realize;
870 dc->desc = "IGD Passthrough Host bridge";
871 }
872
873 static const TypeInfo igd_passthrough_i440fx_info = {
874 .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
875 .parent = TYPE_I440FX_PCI_DEVICE,
876 .instance_size = sizeof(PCII440FXState),
877 .class_init = igd_passthrough_i440fx_class_init,
878 };
879
880 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
881 PCIBus *rootbus)
882 {
883 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
884
885 /* For backwards compat with old device paths */
886 if (s->short_root_bus) {
887 return "0000";
888 }
889 return "0000:00";
890 }
891
892 static Property i440fx_props[] = {
893 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
894 pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
895 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
896 DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
897 DEFINE_PROP_END_OF_LIST(),
898 };
899
900 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
901 {
902 DeviceClass *dc = DEVICE_CLASS(klass);
903 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
904
905 hc->root_bus_path = i440fx_pcihost_root_bus_path;
906 dc->realize = i440fx_pcihost_realize;
907 dc->fw_name = "pci";
908 dc->props = i440fx_props;
909 /* Reason: needs to be wired up by pc_init1 */
910 dc->user_creatable = false;
911 }
912
913 static const TypeInfo i440fx_pcihost_info = {
914 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
915 .parent = TYPE_PCI_HOST_BRIDGE,
916 .instance_size = sizeof(I440FXState),
917 .instance_init = i440fx_pcihost_initfn,
918 .class_init = i440fx_pcihost_class_init,
919 };
920
921 static void i440fx_register_types(void)
922 {
923 type_register_static(&i440fx_info);
924 type_register_static(&igd_passthrough_i440fx_info);
925 type_register_static(&piix3_pci_type_info);
926 type_register_static(&piix3_info);
927 type_register_static(&piix3_xen_info);
928 type_register_static(&i440fx_pcihost_info);
929 }
930
931 type_init(i440fx_register_types)