hw/pci-host/piix.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/pci-host/i440fx.h"
  30 #include "hw/southbridge/piix.h"
  31 #include "hw/qdev-properties.h"
  32 #include "hw/sysbus.h"
  33 #include "qapi/error.h"
  34 #include "migration/vmstate.h"
  35 #include "hw/pci-host/pam.h"
  36 #include "qapi/visitor.h"
  37 #include "qemu/error-report.h"
  38
  39 /*
  40  * I440FX chipset data sheet.
  41  * https://wiki.qemu.org/File:29054901.pdf
  42  */
  43
  44 #define I440FX_PCI_HOST_BRIDGE(obj) \
  45     OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
  46
  47 typedef struct I440FXState {
  48     PCIHostState parent_obj;
  49     Range pci_hole;
  50     uint64_t pci_hole64_size;
  51     bool pci_hole64_fix;
  52     uint32_t short_root_bus;
  53 } I440FXState;
  54
  55 #define I440FX_PCI_DEVICE(obj) \
  56     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
  57
  58 struct PCII440FXState {
  59     /*< private >*/
  60     PCIDevice parent_obj;
  61     /*< public >*/
  62
  63     MemoryRegion *system_memory;
  64     MemoryRegion *pci_address_space;
  65     MemoryRegion *ram_memory;
  66     PAMMemoryRegion pam_regions[13];
  67     MemoryRegion smram_region;
  68     MemoryRegion smram, low_smram;
  69 };
  70
  71
  72 #define I440FX_PAM      0x59
  73 #define I440FX_PAM_SIZE 7
  74 #define I440FX_SMRAM    0x72
  75
  76 /* Keep it 2G to comply with older win32 guests */
  77 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
  78
  79 /* Older coreboot versions (4.0 and older) read a config register that doesn't
  80  * exist in real hardware, to get the RAM size from QEMU.
  81  */
  82 #define I440FX_COREBOOT_RAM_SIZE 0x57
  83
  84 static void i440fx_update_memory_mappings(PCII440FXState *d)
  85 {
  86     int i;
  87     PCIDevice *pd = PCI_DEVICE(d);
  88
  89     memory_region_transaction_begin();
  90     for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
  91         pam_update(&d->pam_regions[i], i,
  92                    pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
  93     }
  94     memory_region_set_enabled(&d->smram_region,
  95                               !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
  96     memory_region_set_enabled(&d->smram,
  97                               pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
  98     memory_region_transaction_commit();
  99 }
 100
 101
 102 static void i440fx_write_config(PCIDevice *dev,
 103                                 uint32_t address, uint32_t val, int len)
 104 {
 105     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 106
 107     /* XXX: implement SMRAM.D_LOCK */
 108     pci_default_write_config(dev, address, val, len);
 109     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 110         range_covers_byte(address, len, I440FX_SMRAM)) {
 111         i440fx_update_memory_mappings(d);
 112     }
 113 }
 114
 115 static int i440fx_post_load(void *opaque, int version_id)
 116 {
 117     PCII440FXState *d = opaque;
 118
 119     i440fx_update_memory_mappings(d);
 120     return 0;
 121 }
 122
 123 static const VMStateDescription vmstate_i440fx = {
 124     .name = "I440FX",
 125     .version_id = 3,
 126     .minimum_version_id = 3,
 127     .post_load = i440fx_post_load,
 128     .fields = (VMStateField[]) {
 129         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 130         /* Used to be smm_enabled, which was basically always zero because
 131          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 132          */
 133         VMSTATE_UNUSED(1),
 134         VMSTATE_END_OF_LIST()
 135     }
 136 };
 137
 138 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 139                                               const char *name, void *opaque,
 140                                               Error **errp)
 141 {
 142     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 143     uint64_t val64;
 144     uint32_t value;
 145
 146     val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
 147     value = val64;
 148     assert(value == val64);
 149     visit_type_uint32(v, name, &value, errp);
 150 }
 151
 152 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 153                                             const char *name, void *opaque,
 154                                             Error **errp)
 155 {
 156     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 157     uint64_t val64;
 158     uint32_t value;
 159
 160     val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
 161     value = val64;
 162     assert(value == val64);
 163     visit_type_uint32(v, name, &value, errp);
 164 }
 165
 166 /*
 167  * The 64bit PCI hole start is set by the Guest firmware
 168  * as the address of the first 64bit PCI MEM resource.
 169  * If no PCI device has resources on the 64bit area,
 170  * the 64bit PCI hole will start after "over 4G RAM" and the
 171  * reserved space for memory hotplug if any.
 172  */
 173 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
 174 {
 175     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 176     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 177     Range w64;
 178     uint64_t value;
 179
 180     pci_bus_get_w64_range(h->bus, &w64);
 181     value = range_is_empty(&w64) ? 0 : range_lob(&w64);
 182     if (!value && s->pci_hole64_fix) {
 183         value = pc_pci_hole64_start();
 184     }
 185     return value;
 186 }
 187
 188 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 189                                                 const char *name,
 190                                                 void *opaque, Error **errp)
 191 {
 192     uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 193
 194     visit_type_uint64(v, name, &hole64_start, errp);
 195 }
 196
 197 /*
 198  * The 64bit PCI hole end is set by the Guest firmware
 199  * as the address of the last 64bit PCI MEM resource.
 200  * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
 201  * that can be configured by the user.
 202  */
 203 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 204                                               const char *name, void *opaque,
 205                                               Error **errp)
 206 {
 207     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 208     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 209     uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 210     Range w64;
 211     uint64_t value, hole64_end;
 212
 213     pci_bus_get_w64_range(h->bus, &w64);
 214     value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
 215     hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
 216     if (s->pci_hole64_fix && value < hole64_end) {
 217         value = hole64_end;
 218     }
 219     visit_type_uint64(v, name, &value, errp);
 220 }
 221
 222 static void i440fx_pcihost_initfn(Object *obj)
 223 {
 224     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 225
 226     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 227                           "pci-conf-idx", 4);
 228     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 229                           "pci-conf-data", 4);
 230
 231     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
 232                         i440fx_pcihost_get_pci_hole_start,
 233                         NULL, NULL, NULL, NULL);
 234
 235     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
 236                         i440fx_pcihost_get_pci_hole_end,
 237                         NULL, NULL, NULL, NULL);
 238
 239     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
 240                         i440fx_pcihost_get_pci_hole64_start,
 241                         NULL, NULL, NULL, NULL);
 242
 243     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
 244                         i440fx_pcihost_get_pci_hole64_end,
 245                         NULL, NULL, NULL, NULL);
 246 }
 247
 248 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 249 {
 250     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 251     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 252
 253     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 254     sysbus_init_ioports(sbd, 0xcf8, 4);
 255
 256     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 257     sysbus_init_ioports(sbd, 0xcfc, 4);
 258
 259     /* register i440fx 0xcf8 port as coalesced pio */
 260     memory_region_set_flush_coalesced(&s->data_mem);
 261     memory_region_add_coalescing(&s->conf_mem, 0, 4);
 262 }
 263
 264 static void i440fx_realize(PCIDevice *dev, Error **errp)
 265 {
 266     dev->config[I440FX_SMRAM] = 0x02;
 267
 268     if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
 269         warn_report("i440fx doesn't support emulated iommu");
 270     }
 271 }
 272
 273 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 274                     PCII440FXState **pi440fx_state,
 275                     int *piix3_devfn,
 276                     ISABus **isa_bus, qemu_irq *pic,
 277                     MemoryRegion *address_space_mem,
 278                     MemoryRegion *address_space_io,
 279                     ram_addr_t ram_size,
 280                     ram_addr_t below_4g_mem_size,
 281                     ram_addr_t above_4g_mem_size,
 282                     MemoryRegion *pci_address_space,
 283                     MemoryRegion *ram_memory)
 284 {
 285     DeviceState *dev;
 286     PCIBus *b;
 287     PCIDevice *d;
 288     PCIHostState *s;
 289     PIIX3State *piix3;
 290     PCII440FXState *f;
 291     unsigned i;
 292     I440FXState *i440fx;
 293
 294     dev = qdev_create(NULL, host_type);
 295     s = PCI_HOST_BRIDGE(dev);
 296     b = pci_root_bus_new(dev, NULL, pci_address_space,
 297                          address_space_io, 0, TYPE_PCI_BUS);
 298     s->bus = b;
 299     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 300     qdev_init_nofail(dev);
 301
 302     d = pci_create_simple(b, 0, pci_type);
 303     *pi440fx_state = I440FX_PCI_DEVICE(d);
 304     f = *pi440fx_state;
 305     f->system_memory = address_space_mem;
 306     f->pci_address_space = pci_address_space;
 307     f->ram_memory = ram_memory;
 308
 309     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 310     range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
 311                      IO_APIC_DEFAULT_ADDRESS - 1);
 312
 313     /* setup pci memory mapping */
 314     pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
 315                            f->pci_address_space);
 316
 317     /* if *disabled* show SMRAM to all CPUs */
 318     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 319                              f->pci_address_space, 0xa0000, 0x20000);
 320     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 321                                         &f->smram_region, 1);
 322     memory_region_set_enabled(&f->smram_region, true);
 323
 324     /* smram, as seen by SMM CPUs */
 325     memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
 326     memory_region_set_enabled(&f->smram, true);
 327     memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
 328                              f->ram_memory, 0xa0000, 0x20000);
 329     memory_region_set_enabled(&f->low_smram, true);
 330     memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
 331     object_property_add_const_link(qdev_get_machine(), "smram",
 332                                    OBJECT(&f->smram), &error_abort);
 333
 334     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 335              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 336     for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
 337         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 338                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 339                  PAM_EXPAN_SIZE);
 340     }
 341
 342     piix3 = piix3_create(b, isa_bus);
 343     piix3->pic = pic;
 344     *piix3_devfn = piix3->dev.devfn;
 345
 346     ram_size = ram_size / 8 / 1024 / 1024;
 347     if (ram_size > 255) {
 348         ram_size = 255;
 349     }
 350     d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
 351
 352     i440fx_update_memory_mappings(f);
 353
 354     return b;
 355 }
 356
 357 PCIBus *find_i440fx(void)
 358 {
 359     PCIHostState *s = OBJECT_CHECK(PCIHostState,
 360                                    object_resolve_path("/machine/i440fx", NULL),
 361                                    TYPE_PCI_HOST_BRIDGE);
 362     return s ? s->bus : NULL;
 363 }
 364
 365 static void i440fx_class_init(ObjectClass *klass, void *data)
 366 {
 367     DeviceClass *dc = DEVICE_CLASS(klass);
 368     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 369
 370     k->realize = i440fx_realize;
 371     k->config_write = i440fx_write_config;
 372     k->vendor_id = PCI_VENDOR_ID_INTEL;
 373     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 374     k->revision = 0x02;
 375     k->class_id = PCI_CLASS_BRIDGE_HOST;
 376     dc->desc = "Host bridge";
 377     dc->vmsd = &vmstate_i440fx;
 378     /*
 379      * PCI-facing part of the host bridge, not usable without the
 380      * host-facing part, which can't be device_add'ed, yet.
 381      */
 382     dc->user_creatable = false;
 383     dc->hotpluggable   = false;
 384 }
 385
 386 static const TypeInfo i440fx_info = {
 387     .name          = TYPE_I440FX_PCI_DEVICE,
 388     .parent        = TYPE_PCI_DEVICE,
 389     .instance_size = sizeof(PCII440FXState),
 390     .class_init    = i440fx_class_init,
 391     .interfaces = (InterfaceInfo[]) {
 392         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 393         { },
 394     },
 395 };
 396
 397 /* IGD Passthrough Host Bridge. */
 398 typedef struct {
 399     uint8_t offset;
 400     uint8_t len;
 401 } IGDHostInfo;
 402
 403 /* Here we just expose minimal host bridge offset subset. */
 404 static const IGDHostInfo igd_host_bridge_infos[] = {
 405     {0x08, 2},  /* revision id */
 406     {0x2c, 2},  /* sybsystem vendor id */
 407     {0x2e, 2},  /* sybsystem id */
 408     {0x50, 2},  /* SNB: processor graphics control register */
 409     {0x52, 2},  /* processor graphics control register */
 410     {0xa4, 4},  /* SNB: graphics base of stolen memory */
 411     {0xa8, 4},  /* SNB: base of GTT stolen memory */
 412 };
 413
 414 static void host_pci_config_read(int pos, int len, uint32_t *val, Error **errp)
 415 {
 416     int rc, config_fd;
 417     /* Access real host bridge. */
 418     char *path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
 419                                  0, 0, 0, 0, "config");
 420
 421     config_fd = open(path, O_RDWR);
 422     if (config_fd < 0) {
 423         error_setg_errno(errp, errno, "Failed to open: %s", path);
 424         goto out;
 425     }
 426
 427     if (lseek(config_fd, pos, SEEK_SET) != pos) {
 428         error_setg_errno(errp, errno, "Failed to seek: %s", path);
 429         goto out_close_fd;
 430     }
 431
 432     do {
 433         rc = read(config_fd, (uint8_t *)val, len);
 434     } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
 435     if (rc != len) {
 436         error_setg_errno(errp, errno, "Failed to read: %s", path);
 437     }
 438
 439 out_close_fd:
 440     close(config_fd);
 441 out:
 442     g_free(path);
 443 }
 444
 445 static void igd_pt_i440fx_realize(PCIDevice *pci_dev, Error **errp)
 446 {
 447     uint32_t val = 0;
 448     int i, num;
 449     int pos, len;
 450     Error *local_err = NULL;
 451
 452     num = ARRAY_SIZE(igd_host_bridge_infos);
 453     for (i = 0; i < num; i++) {
 454         pos = igd_host_bridge_infos[i].offset;
 455         len = igd_host_bridge_infos[i].len;
 456         host_pci_config_read(pos, len, &val, &local_err);
 457         if (local_err) {
 458             error_propagate(errp, local_err);
 459             return;
 460         }
 461         pci_default_write_config(pci_dev, pos, val, len);
 462     }
 463 }
 464
 465 static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
 466 {
 467     DeviceClass *dc = DEVICE_CLASS(klass);
 468     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 469
 470     k->realize = igd_pt_i440fx_realize;
 471     dc->desc = "IGD Passthrough Host bridge";
 472 }
 473
 474 static const TypeInfo igd_passthrough_i440fx_info = {
 475     .name          = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
 476     .parent        = TYPE_I440FX_PCI_DEVICE,
 477     .instance_size = sizeof(PCII440FXState),
 478     .class_init    = igd_passthrough_i440fx_class_init,
 479 };
 480
 481 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 482                                                 PCIBus *rootbus)
 483 {
 484     I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 485
 486     /* For backwards compat with old device paths */
 487     if (s->short_root_bus) {
 488         return "0000";
 489     }
 490     return "0000:00";
 491 }
 492
 493 static Property i440fx_props[] = {
 494     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 495                      pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
 496     DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 497     DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
 498     DEFINE_PROP_END_OF_LIST(),
 499 };
 500
 501 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 502 {
 503     DeviceClass *dc = DEVICE_CLASS(klass);
 504     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 505
 506     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 507     dc->realize = i440fx_pcihost_realize;
 508     dc->fw_name = "pci";
 509     dc->props = i440fx_props;
 510     /* Reason: needs to be wired up by pc_init1 */
 511     dc->user_creatable = false;
 512 }
 513
 514 static const TypeInfo i440fx_pcihost_info = {
 515     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 516     .parent        = TYPE_PCI_HOST_BRIDGE,
 517     .instance_size = sizeof(I440FXState),
 518     .instance_init = i440fx_pcihost_initfn,
 519     .class_init    = i440fx_pcihost_class_init,
 520 };
 521
 522 static void i440fx_register_types(void)
 523 {
 524     type_register_static(&i440fx_info);
 525     type_register_static(&igd_passthrough_i440fx_info);
 526     type_register_static(&i440fx_pcihost_info);
 527 }
 528
 529 type_init(i440fx_register_types)