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1 /*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/i386/pc.h"
27 #include "hw/irq.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/pci-host/i440fx.h"
31 #include "hw/southbridge/piix.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/isa/isa.h"
34 #include "hw/sysbus.h"
35 #include "qapi/error.h"
36 #include "qemu/range.h"
37 #include "hw/xen/xen.h"
38 #include "migration/vmstate.h"
39 #include "hw/pci-host/pam.h"
40 #include "sysemu/reset.h"
41 #include "sysemu/runstate.h"
42 #include "hw/i386/ioapic.h"
43 #include "qapi/visitor.h"
44 #include "qemu/error-report.h"
45
46 /*
47 * I440FX chipset data sheet.
48 * https://wiki.qemu.org/File:29054901.pdf
49 */
50
51 #define I440FX_PCI_HOST_BRIDGE(obj) \
52 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
53
54 typedef struct I440FXState {
55 PCIHostState parent_obj;
56 Range pci_hole;
57 uint64_t pci_hole64_size;
58 bool pci_hole64_fix;
59 uint32_t short_root_bus;
60 } I440FXState;
61
62 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
63 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
64 #define XEN_PIIX_NUM_PIRQS 128ULL
65
66 typedef struct PIIX3State {
67 PCIDevice dev;
68
69 /*
70 * bitmap to track pic levels.
71 * The pic level is the logical OR of all the PCI irqs mapped to it
72 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
73 *
74 * PIRQ is mapped to PIC pins, we track it by
75 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
76 * pic_irq * PIIX_NUM_PIRQS + pirq
77 */
78 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
79 #error "unable to encode pic state in 64bit in pic_levels."
80 #endif
81 uint64_t pic_levels;
82
83 qemu_irq *pic;
84
85 /* This member isn't used. Just for save/load compatibility */
86 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
87
88 /* Reset Control Register contents */
89 uint8_t rcr;
90
91 /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
92 MemoryRegion rcr_mem;
93 } PIIX3State;
94
95 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
96 #define PIIX3_PCI_DEVICE(obj) \
97 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
98
99 #define I440FX_PCI_DEVICE(obj) \
100 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
101
102 #define TYPE_PIIX3_DEVICE "PIIX3"
103 #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
104
105 struct PCII440FXState {
106 /*< private >*/
107 PCIDevice parent_obj;
108 /*< public >*/
109
110 MemoryRegion *system_memory;
111 MemoryRegion *pci_address_space;
112 MemoryRegion *ram_memory;
113 PAMMemoryRegion pam_regions[13];
114 MemoryRegion smram_region;
115 MemoryRegion smram, low_smram;
116 };
117
118
119 #define I440FX_PAM 0x59
120 #define I440FX_PAM_SIZE 7
121 #define I440FX_SMRAM 0x72
122
123 /* Keep it 2G to comply with older win32 guests */
124 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
125
126 /* Older coreboot versions (4.0 and older) read a config register that doesn't
127 * exist in real hardware, to get the RAM size from QEMU.
128 */
129 #define I440FX_COREBOOT_RAM_SIZE 0x57
130
131 static void piix3_set_irq(void *opaque, int pirq, int level);
132 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
133 static void piix3_write_config_xen(PCIDevice *dev,
134 uint32_t address, uint32_t val, int len);
135
136 /* return the global irq number corresponding to a given device irq
137 pin. We could also use the bus number to have a more precise
138 mapping. */
139 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
140 {
141 int slot_addend;
142 slot_addend = (pci_dev->devfn >> 3) - 1;
143 return (pci_intx + slot_addend) & 3;
144 }
145
146 static void i440fx_update_memory_mappings(PCII440FXState *d)
147 {
148 int i;
149 PCIDevice *pd = PCI_DEVICE(d);
150
151 memory_region_transaction_begin();
152 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
153 pam_update(&d->pam_regions[i], i,
154 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
155 }
156 memory_region_set_enabled(&d->smram_region,
157 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
158 memory_region_set_enabled(&d->smram,
159 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
160 memory_region_transaction_commit();
161 }
162
163
164 static void i440fx_write_config(PCIDevice *dev,
165 uint32_t address, uint32_t val, int len)
166 {
167 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
168
169 /* XXX: implement SMRAM.D_LOCK */
170 pci_default_write_config(dev, address, val, len);
171 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
172 range_covers_byte(address, len, I440FX_SMRAM)) {
173 i440fx_update_memory_mappings(d);
174 }
175 }
176
177 static int i440fx_post_load(void *opaque, int version_id)
178 {
179 PCII440FXState *d = opaque;
180
181 i440fx_update_memory_mappings(d);
182 return 0;
183 }
184
185 static const VMStateDescription vmstate_i440fx = {
186 .name = "I440FX",
187 .version_id = 3,
188 .minimum_version_id = 3,
189 .post_load = i440fx_post_load,
190 .fields = (VMStateField[]) {
191 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
192 /* Used to be smm_enabled, which was basically always zero because
193 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
194 */
195 VMSTATE_UNUSED(1),
196 VMSTATE_END_OF_LIST()
197 }
198 };
199
200 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
201 const char *name, void *opaque,
202 Error **errp)
203 {
204 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
205 uint64_t val64;
206 uint32_t value;
207
208 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
209 value = val64;
210 assert(value == val64);
211 visit_type_uint32(v, name, &value, errp);
212 }
213
214 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
215 const char *name, void *opaque,
216 Error **errp)
217 {
218 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
219 uint64_t val64;
220 uint32_t value;
221
222 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
223 value = val64;
224 assert(value == val64);
225 visit_type_uint32(v, name, &value, errp);
226 }
227
228 /*
229 * The 64bit PCI hole start is set by the Guest firmware
230 * as the address of the first 64bit PCI MEM resource.
231 * If no PCI device has resources on the 64bit area,
232 * the 64bit PCI hole will start after "over 4G RAM" and the
233 * reserved space for memory hotplug if any.
234 */
235 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
236 {
237 PCIHostState *h = PCI_HOST_BRIDGE(obj);
238 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
239 Range w64;
240 uint64_t value;
241
242 pci_bus_get_w64_range(h->bus, &w64);
243 value = range_is_empty(&w64) ? 0 : range_lob(&w64);
244 if (!value && s->pci_hole64_fix) {
245 value = pc_pci_hole64_start();
246 }
247 return value;
248 }
249
250 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
251 const char *name,
252 void *opaque, Error **errp)
253 {
254 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
255
256 visit_type_uint64(v, name, &hole64_start, errp);
257 }
258
259 /*
260 * The 64bit PCI hole end is set by the Guest firmware
261 * as the address of the last 64bit PCI MEM resource.
262 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
263 * that can be configured by the user.
264 */
265 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
266 const char *name, void *opaque,
267 Error **errp)
268 {
269 PCIHostState *h = PCI_HOST_BRIDGE(obj);
270 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
271 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
272 Range w64;
273 uint64_t value, hole64_end;
274
275 pci_bus_get_w64_range(h->bus, &w64);
276 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
277 hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
278 if (s->pci_hole64_fix && value < hole64_end) {
279 value = hole64_end;
280 }
281 visit_type_uint64(v, name, &value, errp);
282 }
283
284 static void i440fx_pcihost_initfn(Object *obj)
285 {
286 PCIHostState *s = PCI_HOST_BRIDGE(obj);
287
288 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
289 "pci-conf-idx", 4);
290 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
291 "pci-conf-data", 4);
292
293 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
294 i440fx_pcihost_get_pci_hole_start,
295 NULL, NULL, NULL, NULL);
296
297 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
298 i440fx_pcihost_get_pci_hole_end,
299 NULL, NULL, NULL, NULL);
300
301 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
302 i440fx_pcihost_get_pci_hole64_start,
303 NULL, NULL, NULL, NULL);
304
305 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
306 i440fx_pcihost_get_pci_hole64_end,
307 NULL, NULL, NULL, NULL);
308 }
309
310 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
311 {
312 PCIHostState *s = PCI_HOST_BRIDGE(dev);
313 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
314
315 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
316 sysbus_init_ioports(sbd, 0xcf8, 4);
317
318 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
319 sysbus_init_ioports(sbd, 0xcfc, 4);
320
321 /* register i440fx 0xcf8 port as coalesced pio */
322 memory_region_set_flush_coalesced(&s->data_mem);
323 memory_region_add_coalescing(&s->conf_mem, 0, 4);
324 }
325
326 static void i440fx_realize(PCIDevice *dev, Error **errp)
327 {
328 dev->config[I440FX_SMRAM] = 0x02;
329
330 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
331 warn_report("i440fx doesn't support emulated iommu");
332 }
333 }
334
335 static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
336 {
337 PIIX3State *piix3;
338 PCIDevice *pci_dev;
339
340 /*
341 * Xen supports additional interrupt routes from the PCI devices to
342 * the IOAPIC: the four pins of each PCI device on the bus are also
343 * connected to the IOAPIC directly.
344 * These additional routes can be discovered through ACPI.
345 */
346 if (xen_enabled()) {
347 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
348 TYPE_PIIX3_XEN_DEVICE);
349 piix3 = PIIX3_PCI_DEVICE(pci_dev);
350 pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
351 piix3, XEN_PIIX_NUM_PIRQS);
352 } else {
353 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
354 TYPE_PIIX3_DEVICE);
355 piix3 = PIIX3_PCI_DEVICE(pci_dev);
356 pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
357 piix3, PIIX_NUM_PIRQS);
358 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
359 }
360 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
361
362 return piix3;
363 }
364
365 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
366 PCII440FXState **pi440fx_state,
367 int *piix3_devfn,
368 ISABus **isa_bus, qemu_irq *pic,
369 MemoryRegion *address_space_mem,
370 MemoryRegion *address_space_io,
371 ram_addr_t ram_size,
372 ram_addr_t below_4g_mem_size,
373 ram_addr_t above_4g_mem_size,
374 MemoryRegion *pci_address_space,
375 MemoryRegion *ram_memory)
376 {
377 DeviceState *dev;
378 PCIBus *b;
379 PCIDevice *d;
380 PCIHostState *s;
381 PIIX3State *piix3;
382 PCII440FXState *f;
383 unsigned i;
384 I440FXState *i440fx;
385
386 dev = qdev_create(NULL, host_type);
387 s = PCI_HOST_BRIDGE(dev);
388 b = pci_root_bus_new(dev, NULL, pci_address_space,
389 address_space_io, 0, TYPE_PCI_BUS);
390 s->bus = b;
391 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
392 qdev_init_nofail(dev);
393
394 d = pci_create_simple(b, 0, pci_type);
395 *pi440fx_state = I440FX_PCI_DEVICE(d);
396 f = *pi440fx_state;
397 f->system_memory = address_space_mem;
398 f->pci_address_space = pci_address_space;
399 f->ram_memory = ram_memory;
400
401 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
402 range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
403 IO_APIC_DEFAULT_ADDRESS - 1);
404
405 /* setup pci memory mapping */
406 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
407 f->pci_address_space);
408
409 /* if *disabled* show SMRAM to all CPUs */
410 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
411 f->pci_address_space, 0xa0000, 0x20000);
412 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
413 &f->smram_region, 1);
414 memory_region_set_enabled(&f->smram_region, true);
415
416 /* smram, as seen by SMM CPUs */
417 memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
418 memory_region_set_enabled(&f->smram, true);
419 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
420 f->ram_memory, 0xa0000, 0x20000);
421 memory_region_set_enabled(&f->low_smram, true);
422 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
423 object_property_add_const_link(qdev_get_machine(), "smram",
424 OBJECT(&f->smram), &error_abort);
425
426 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
427 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
428 for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
429 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
430 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
431 PAM_EXPAN_SIZE);
432 }
433
434 piix3 = piix3_create(b, isa_bus);
435 piix3->pic = pic;
436 *piix3_devfn = piix3->dev.devfn;
437
438 ram_size = ram_size / 8 / 1024 / 1024;
439 if (ram_size > 255) {
440 ram_size = 255;
441 }
442 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
443
444 i440fx_update_memory_mappings(f);
445
446 return b;
447 }
448
449 PCIBus *find_i440fx(void)
450 {
451 PCIHostState *s = OBJECT_CHECK(PCIHostState,
452 object_resolve_path("/machine/i440fx", NULL),
453 TYPE_PCI_HOST_BRIDGE);
454 return s ? s->bus : NULL;
455 }
456
457 /* PIIX3 PCI to ISA bridge */
458 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
459 {
460 qemu_set_irq(piix3->pic[pic_irq],
461 !!(piix3->pic_levels &
462 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
463 (pic_irq * PIIX_NUM_PIRQS))));
464 }
465
466 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
467 {
468 int pic_irq;
469 uint64_t mask;
470
471 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
472 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
473 return;
474 }
475
476 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
477 piix3->pic_levels &= ~mask;
478 piix3->pic_levels |= mask * !!level;
479 }
480
481 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
482 {
483 int pic_irq;
484
485 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
486 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
487 return;
488 }
489
490 piix3_set_irq_level_internal(piix3, pirq, level);
491
492 piix3_set_irq_pic(piix3, pic_irq);
493 }
494
495 static void piix3_set_irq(void *opaque, int pirq, int level)
496 {
497 PIIX3State *piix3 = opaque;
498 piix3_set_irq_level(piix3, pirq, level);
499 }
500
501 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
502 {
503 PIIX3State *piix3 = opaque;
504 int irq = piix3->dev.config[PIIX_PIRQCA + pin];
505 PCIINTxRoute route;
506
507 if (irq < PIIX_NUM_PIC_IRQS) {
508 route.mode = PCI_INTX_ENABLED;
509 route.irq = irq;
510 } else {
511 route.mode = PCI_INTX_DISABLED;
512 route.irq = -1;
513 }
514 return route;
515 }
516
517 /* irq routing is changed. so rebuild bitmap */
518 static void piix3_update_irq_levels(PIIX3State *piix3)
519 {
520 PCIBus *bus = pci_get_bus(&piix3->dev);
521 int pirq;
522
523 piix3->pic_levels = 0;
524 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
525 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
526 }
527 }
528
529 static void piix3_write_config(PCIDevice *dev,
530 uint32_t address, uint32_t val, int len)
531 {
532 pci_default_write_config(dev, address, val, len);
533 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
534 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
535 int pic_irq;
536
537 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
538 piix3_update_irq_levels(piix3);
539 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
540 piix3_set_irq_pic(piix3, pic_irq);
541 }
542 }
543 }
544
545 static void piix3_write_config_xen(PCIDevice *dev,
546 uint32_t address, uint32_t val, int len)
547 {
548 xen_piix_pci_write_config_client(address, val, len);
549 piix3_write_config(dev, address, val, len);
550 }
551
552 static void piix3_reset(void *opaque)
553 {
554 PIIX3State *d = opaque;
555 uint8_t *pci_conf = d->dev.config;
556
557 pci_conf[0x04] = 0x07; /* master, memory and I/O */
558 pci_conf[0x05] = 0x00;
559 pci_conf[0x06] = 0x00;
560 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
561 pci_conf[0x4c] = 0x4d;
562 pci_conf[0x4e] = 0x03;
563 pci_conf[0x4f] = 0x00;
564 pci_conf[0x60] = 0x80;
565 pci_conf[0x61] = 0x80;
566 pci_conf[0x62] = 0x80;
567 pci_conf[0x63] = 0x80;
568 pci_conf[0x69] = 0x02;
569 pci_conf[0x70] = 0x80;
570 pci_conf[0x76] = 0x0c;
571 pci_conf[0x77] = 0x0c;
572 pci_conf[0x78] = 0x02;
573 pci_conf[0x79] = 0x00;
574 pci_conf[0x80] = 0x00;
575 pci_conf[0x82] = 0x00;
576 pci_conf[0xa0] = 0x08;
577 pci_conf[0xa2] = 0x00;
578 pci_conf[0xa3] = 0x00;
579 pci_conf[0xa4] = 0x00;
580 pci_conf[0xa5] = 0x00;
581 pci_conf[0xa6] = 0x00;
582 pci_conf[0xa7] = 0x00;
583 pci_conf[0xa8] = 0x0f;
584 pci_conf[0xaa] = 0x00;
585 pci_conf[0xab] = 0x00;
586 pci_conf[0xac] = 0x00;
587 pci_conf[0xae] = 0x00;
588
589 d->pic_levels = 0;
590 d->rcr = 0;
591 }
592
593 static int piix3_post_load(void *opaque, int version_id)
594 {
595 PIIX3State *piix3 = opaque;
596 int pirq;
597
598 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
599 * might bring the system to a different state than the saved one;
600 * for example, the interrupt could be masked but the i8259 would
601 * not know that yet and would trigger an interrupt in the CPU.
602 *
603 * Here, we update irq levels without raising the interrupt.
604 * Interrupt state will be deserialized separately through the i8259.
605 */
606 piix3->pic_levels = 0;
607 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
608 piix3_set_irq_level_internal(piix3, pirq,
609 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
610 }
611 return 0;
612 }
613
614 static int piix3_pre_save(void *opaque)
615 {
616 int i;
617 PIIX3State *piix3 = opaque;
618
619 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
620 piix3->pci_irq_levels_vmstate[i] =
621 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
622 }
623
624 return 0;
625 }
626
627 static bool piix3_rcr_needed(void *opaque)
628 {
629 PIIX3State *piix3 = opaque;
630
631 return (piix3->rcr != 0);
632 }
633
634 static const VMStateDescription vmstate_piix3_rcr = {
635 .name = "PIIX3/rcr",
636 .version_id = 1,
637 .minimum_version_id = 1,
638 .needed = piix3_rcr_needed,
639 .fields = (VMStateField[]) {
640 VMSTATE_UINT8(rcr, PIIX3State),
641 VMSTATE_END_OF_LIST()
642 }
643 };
644
645 static const VMStateDescription vmstate_piix3 = {
646 .name = "PIIX3",
647 .version_id = 3,
648 .minimum_version_id = 2,
649 .post_load = piix3_post_load,
650 .pre_save = piix3_pre_save,
651 .fields = (VMStateField[]) {
652 VMSTATE_PCI_DEVICE(dev, PIIX3State),
653 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
654 PIIX_NUM_PIRQS, 3),
655 VMSTATE_END_OF_LIST()
656 },
657 .subsections = (const VMStateDescription*[]) {
658 &vmstate_piix3_rcr,
659 NULL
660 }
661 };
662
663
664 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
665 {
666 PIIX3State *d = opaque;
667
668 if (val & 4) {
669 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
670 return;
671 }
672 d->rcr = val & 2; /* keep System Reset type only */
673 }
674
675 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
676 {
677 PIIX3State *d = opaque;
678
679 return d->rcr;
680 }
681
682 static const MemoryRegionOps rcr_ops = {
683 .read = rcr_read,
684 .write = rcr_write,
685 .endianness = DEVICE_LITTLE_ENDIAN
686 };
687
688 static void piix3_realize(PCIDevice *dev, Error **errp)
689 {
690 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
691
692 if (!isa_bus_new(DEVICE(d), get_system_memory(),
693 pci_address_space_io(dev), errp)) {
694 return;
695 }
696
697 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
698 "piix3-reset-control", 1);
699 memory_region_add_subregion_overlap(pci_address_space_io(dev),
700 PIIX_RCR_IOPORT, &d->rcr_mem, 1);
701
702 qemu_register_reset(piix3_reset, d);
703 }
704
705 static void pci_piix3_class_init(ObjectClass *klass, void *data)
706 {
707 DeviceClass *dc = DEVICE_CLASS(klass);
708 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
709
710 dc->desc = "ISA bridge";
711 dc->vmsd = &vmstate_piix3;
712 dc->hotpluggable = false;
713 k->realize = piix3_realize;
714 k->vendor_id = PCI_VENDOR_ID_INTEL;
715 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
716 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
717 k->class_id = PCI_CLASS_BRIDGE_ISA;
718 /*
719 * Reason: part of PIIX3 southbridge, needs to be wired up by
720 * pc_piix.c's pc_init1()
721 */
722 dc->user_creatable = false;
723 }
724
725 static const TypeInfo piix3_pci_type_info = {
726 .name = TYPE_PIIX3_PCI_DEVICE,
727 .parent = TYPE_PCI_DEVICE,
728 .instance_size = sizeof(PIIX3State),
729 .abstract = true,
730 .class_init = pci_piix3_class_init,
731 .interfaces = (InterfaceInfo[]) {
732 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
733 { },
734 },
735 };
736
737 static void piix3_class_init(ObjectClass *klass, void *data)
738 {
739 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
740
741 k->config_write = piix3_write_config;
742 }
743
744 static const TypeInfo piix3_info = {
745 .name = TYPE_PIIX3_DEVICE,
746 .parent = TYPE_PIIX3_PCI_DEVICE,
747 .class_init = piix3_class_init,
748 };
749
750 static void piix3_xen_class_init(ObjectClass *klass, void *data)
751 {
752 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
753
754 k->config_write = piix3_write_config_xen;
755 };
756
757 static const TypeInfo piix3_xen_info = {
758 .name = TYPE_PIIX3_XEN_DEVICE,
759 .parent = TYPE_PIIX3_PCI_DEVICE,
760 .class_init = piix3_xen_class_init,
761 };
762
763 static void i440fx_class_init(ObjectClass *klass, void *data)
764 {
765 DeviceClass *dc = DEVICE_CLASS(klass);
766 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
767
768 k->realize = i440fx_realize;
769 k->config_write = i440fx_write_config;
770 k->vendor_id = PCI_VENDOR_ID_INTEL;
771 k->device_id = PCI_DEVICE_ID_INTEL_82441;
772 k->revision = 0x02;
773 k->class_id = PCI_CLASS_BRIDGE_HOST;
774 dc->desc = "Host bridge";
775 dc->vmsd = &vmstate_i440fx;
776 /*
777 * PCI-facing part of the host bridge, not usable without the
778 * host-facing part, which can't be device_add'ed, yet.
779 */
780 dc->user_creatable = false;
781 dc->hotpluggable = false;
782 }
783
784 static const TypeInfo i440fx_info = {
785 .name = TYPE_I440FX_PCI_DEVICE,
786 .parent = TYPE_PCI_DEVICE,
787 .instance_size = sizeof(PCII440FXState),
788 .class_init = i440fx_class_init,
789 .interfaces = (InterfaceInfo[]) {
790 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
791 { },
792 },
793 };
794
795 /* IGD Passthrough Host Bridge. */
796 typedef struct {
797 uint8_t offset;
798 uint8_t len;
799 } IGDHostInfo;
800
801 /* Here we just expose minimal host bridge offset subset. */
802 static const IGDHostInfo igd_host_bridge_infos[] = {
803 {0x08, 2}, /* revision id */
804 {0x2c, 2}, /* sybsystem vendor id */
805 {0x2e, 2}, /* sybsystem id */
806 {0x50, 2}, /* SNB: processor graphics control register */
807 {0x52, 2}, /* processor graphics control register */
808 {0xa4, 4}, /* SNB: graphics base of stolen memory */
809 {0xa8, 4}, /* SNB: base of GTT stolen memory */
810 };
811
812 static void host_pci_config_read(int pos, int len, uint32_t *val, Error **errp)
813 {
814 int rc, config_fd;
815 /* Access real host bridge. */
816 char *path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
817 0, 0, 0, 0, "config");
818
819 config_fd = open(path, O_RDWR);
820 if (config_fd < 0) {
821 error_setg_errno(errp, errno, "Failed to open: %s", path);
822 goto out;
823 }
824
825 if (lseek(config_fd, pos, SEEK_SET) != pos) {
826 error_setg_errno(errp, errno, "Failed to seek: %s", path);
827 goto out_close_fd;
828 }
829
830 do {
831 rc = read(config_fd, (uint8_t *)val, len);
832 } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
833 if (rc != len) {
834 error_setg_errno(errp, errno, "Failed to read: %s", path);
835 }
836
837 out_close_fd:
838 close(config_fd);
839 out:
840 g_free(path);
841 }
842
843 static void igd_pt_i440fx_realize(PCIDevice *pci_dev, Error **errp)
844 {
845 uint32_t val = 0;
846 int i, num;
847 int pos, len;
848 Error *local_err = NULL;
849
850 num = ARRAY_SIZE(igd_host_bridge_infos);
851 for (i = 0; i < num; i++) {
852 pos = igd_host_bridge_infos[i].offset;
853 len = igd_host_bridge_infos[i].len;
854 host_pci_config_read(pos, len, &val, &local_err);
855 if (local_err) {
856 error_propagate(errp, local_err);
857 return;
858 }
859 pci_default_write_config(pci_dev, pos, val, len);
860 }
861 }
862
863 static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
864 {
865 DeviceClass *dc = DEVICE_CLASS(klass);
866 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
867
868 k->realize = igd_pt_i440fx_realize;
869 dc->desc = "IGD Passthrough Host bridge";
870 }
871
872 static const TypeInfo igd_passthrough_i440fx_info = {
873 .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
874 .parent = TYPE_I440FX_PCI_DEVICE,
875 .instance_size = sizeof(PCII440FXState),
876 .class_init = igd_passthrough_i440fx_class_init,
877 };
878
879 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
880 PCIBus *rootbus)
881 {
882 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
883
884 /* For backwards compat with old device paths */
885 if (s->short_root_bus) {
886 return "0000";
887 }
888 return "0000:00";
889 }
890
891 static Property i440fx_props[] = {
892 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
893 pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
894 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
895 DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
896 DEFINE_PROP_END_OF_LIST(),
897 };
898
899 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
900 {
901 DeviceClass *dc = DEVICE_CLASS(klass);
902 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
903
904 hc->root_bus_path = i440fx_pcihost_root_bus_path;
905 dc->realize = i440fx_pcihost_realize;
906 dc->fw_name = "pci";
907 dc->props = i440fx_props;
908 /* Reason: needs to be wired up by pc_init1 */
909 dc->user_creatable = false;
910 }
911
912 static const TypeInfo i440fx_pcihost_info = {
913 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
914 .parent = TYPE_PCI_HOST_BRIDGE,
915 .instance_size = sizeof(I440FXState),
916 .instance_init = i440fx_pcihost_initfn,
917 .class_init = i440fx_pcihost_class_init,
918 };
919
920 static void i440fx_register_types(void)
921 {
922 type_register_static(&i440fx_info);
923 type_register_static(&igd_passthrough_i440fx_info);
924 type_register_static(&piix3_pci_type_info);
925 type_register_static(&piix3_info);
926 type_register_static(&piix3_xen_info);
927 type_register_static(&i440fx_pcihost_info);
928 }
929
930 type_init(i440fx_register_types)