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1 /*
2 * QEMU PowerPC e500-based platforms
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include "qemu/osdep.h"
18 #include "qapi/error.h"
19 #include "e500.h"
20 #include "e500-ccsr.h"
21 #include "net/net.h"
22 #include "qemu/config-file.h"
23 #include "hw/hw.h"
24 #include "hw/char/serial.h"
25 #include "hw/pci/pci.h"
26 #include "hw/boards.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/kvm.h"
29 #include "kvm_ppc.h"
30 #include "sysemu/device_tree.h"
31 #include "hw/ppc/openpic.h"
32 #include "hw/ppc/ppc.h"
33 #include "hw/loader.h"
34 #include "elf.h"
35 #include "hw/sysbus.h"
36 #include "exec/address-spaces.h"
37 #include "qemu/host-utils.h"
38 #include "qemu/option.h"
39 #include "hw/pci-host/ppce500.h"
40 #include "qemu/error-report.h"
41 #include "hw/platform-bus.h"
42 #include "hw/net/fsl_etsec/etsec.h"
43
44 #define EPAPR_MAGIC (0x45504150)
45 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
46 #define DTC_LOAD_PAD 0x1800000
47 #define DTC_PAD_MASK 0xFFFFF
48 #define DTB_MAX_SIZE (8 * 1024 * 1024)
49 #define INITRD_LOAD_PAD 0x2000000
50 #define INITRD_PAD_MASK 0xFFFFFF
51
52 #define RAM_SIZES_ALIGN (64UL << 20)
53
54 /* TODO: parameterize */
55 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
56 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
57 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
58 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
59 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
60 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
61 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
62 #define MPC8544_UTIL_OFFSET 0xe0000ULL
63 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
64 #define MPC8XXX_GPIO_IRQ 47
65
66 struct boot_info
67 {
68 uint32_t dt_base;
69 uint32_t dt_size;
70 uint32_t entry;
71 };
72
73 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
74 int nr_slots, int *len)
75 {
76 int i = 0;
77 int slot;
78 int pci_irq;
79 int host_irq;
80 int last_slot = first_slot + nr_slots;
81 uint32_t *pci_map;
82
83 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
84 pci_map = g_malloc(*len);
85
86 for (slot = first_slot; slot < last_slot; slot++) {
87 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
88 pci_map[i++] = cpu_to_be32(slot << 11);
89 pci_map[i++] = cpu_to_be32(0x0);
90 pci_map[i++] = cpu_to_be32(0x0);
91 pci_map[i++] = cpu_to_be32(pci_irq + 1);
92 pci_map[i++] = cpu_to_be32(mpic);
93 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
94 pci_map[i++] = cpu_to_be32(host_irq + 1);
95 pci_map[i++] = cpu_to_be32(0x1);
96 }
97 }
98
99 assert((i * sizeof(uint32_t)) == *len);
100
101 return pci_map;
102 }
103
104 static void dt_serial_create(void *fdt, unsigned long long offset,
105 const char *soc, const char *mpic,
106 const char *alias, int idx, bool defcon)
107 {
108 char ser[128];
109
110 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
111 qemu_fdt_add_subnode(fdt, ser);
112 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
113 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
114 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
115 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
116 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
117 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
118 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
119 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
120
121 if (defcon) {
122 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
123 }
124 }
125
126 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
127 {
128 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
129 int irq0 = MPC8XXX_GPIO_IRQ;
130 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
131 gchar *poweroff = g_strdup_printf("%s/power-off", soc);
132 int gpio_ph;
133
134 qemu_fdt_add_subnode(fdt, node);
135 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
136 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
137 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
138 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
139 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
140 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
141 gpio_ph = qemu_fdt_alloc_phandle(fdt);
142 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
143 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
144
145 /* Power Off Pin */
146 qemu_fdt_add_subnode(fdt, poweroff);
147 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
148 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
149
150 g_free(node);
151 g_free(poweroff);
152 }
153
154 typedef struct PlatformDevtreeData {
155 void *fdt;
156 const char *mpic;
157 int irq_start;
158 const char *node;
159 PlatformBusDevice *pbus;
160 } PlatformDevtreeData;
161
162 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
163 {
164 eTSEC *etsec = ETSEC_COMMON(sbdev);
165 PlatformBusDevice *pbus = data->pbus;
166 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
167 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
168 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
169 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
170 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0);
171 gchar *group = g_strdup_printf("%s/queue-group", node);
172 void *fdt = data->fdt;
173
174 assert((int64_t)mmio0 >= 0);
175 assert(irq0 >= 0);
176 assert(irq1 >= 0);
177 assert(irq2 >= 0);
178
179 qemu_fdt_add_subnode(fdt, node);
180 qemu_fdt_setprop_string(fdt, node, "device_type", "network");
181 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
182 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
183 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
184 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
185
186 qemu_fdt_add_subnode(fdt, group);
187 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
188 qemu_fdt_setprop_cells(fdt, group, "interrupts",
189 data->irq_start + irq0, 0x2,
190 data->irq_start + irq1, 0x2,
191 data->irq_start + irq2, 0x2);
192
193 g_free(node);
194 g_free(group);
195
196 return 0;
197 }
198
199 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
200 {
201 PlatformDevtreeData *data = opaque;
202 bool matched = false;
203
204 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
205 create_devtree_etsec(sbdev, data);
206 matched = true;
207 }
208
209 if (!matched) {
210 error_report("Device %s is not supported by this machine yet.",
211 qdev_fw_name(DEVICE(sbdev)));
212 exit(1);
213 }
214 }
215
216 static void platform_bus_create_devtree(PPCE500Params *params, void *fdt,
217 const char *mpic)
218 {
219 gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base);
220 const char platcomp[] = "qemu,platform\0simple-bus";
221 uint64_t addr = params->platform_bus_base;
222 uint64_t size = params->platform_bus_size;
223 int irq_start = params->platform_bus_first_irq;
224 PlatformBusDevice *pbus;
225 DeviceState *dev;
226
227 /* Create a /platform node that we can put all devices into */
228
229 qemu_fdt_add_subnode(fdt, node);
230 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
231
232 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
233 address and size */
234 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
235 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
236 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
237
238 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
239
240 dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE);
241 pbus = PLATFORM_BUS_DEVICE(dev);
242
243 /* We can only create dt nodes for dynamic devices when they're ready */
244 if (pbus->done_gathering) {
245 PlatformDevtreeData data = {
246 .fdt = fdt,
247 .mpic = mpic,
248 .irq_start = irq_start,
249 .node = node,
250 .pbus = pbus,
251 };
252
253 /* Loop through all dynamic sysbus devices and create nodes for them */
254 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
255 }
256
257 g_free(node);
258 }
259
260 static int ppce500_load_device_tree(MachineState *machine,
261 PPCE500Params *params,
262 hwaddr addr,
263 hwaddr initrd_base,
264 hwaddr initrd_size,
265 hwaddr kernel_base,
266 hwaddr kernel_size,
267 bool dry_run)
268 {
269 CPUPPCState *env = first_cpu->env_ptr;
270 int ret = -1;
271 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
272 int fdt_size;
273 void *fdt;
274 uint8_t hypercall[16];
275 uint32_t clock_freq = 400000000;
276 uint32_t tb_freq = 400000000;
277 int i;
278 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
279 char soc[128];
280 char mpic[128];
281 uint32_t mpic_ph;
282 uint32_t msi_ph;
283 char gutil[128];
284 char pci[128];
285 char msi[128];
286 uint32_t *pci_map = NULL;
287 int len;
288 uint32_t pci_ranges[14] =
289 {
290 0x2000000, 0x0, params->pci_mmio_bus_base,
291 params->pci_mmio_base >> 32, params->pci_mmio_base,
292 0x0, 0x20000000,
293
294 0x1000000, 0x0, 0x0,
295 params->pci_pio_base >> 32, params->pci_pio_base,
296 0x0, 0x10000,
297 };
298 QemuOpts *machine_opts = qemu_get_machine_opts();
299 const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
300 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
301
302 if (dtb_file) {
303 char *filename;
304 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
305 if (!filename) {
306 goto out;
307 }
308
309 fdt = load_device_tree(filename, &fdt_size);
310 g_free(filename);
311 if (!fdt) {
312 goto out;
313 }
314 goto done;
315 }
316
317 fdt = create_device_tree(&fdt_size);
318 if (fdt == NULL) {
319 goto out;
320 }
321
322 /* Manipulate device tree in memory. */
323 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
324 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
325
326 qemu_fdt_add_subnode(fdt, "/memory");
327 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
328 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
329 sizeof(mem_reg_property));
330
331 qemu_fdt_add_subnode(fdt, "/chosen");
332 if (initrd_size) {
333 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
334 initrd_base);
335 if (ret < 0) {
336 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
337 }
338
339 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
340 (initrd_base + initrd_size));
341 if (ret < 0) {
342 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
343 }
344
345 }
346
347 if (kernel_base != -1ULL) {
348 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
349 kernel_base >> 32, kernel_base,
350 kernel_size >> 32, kernel_size);
351 }
352
353 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
354 machine->kernel_cmdline);
355 if (ret < 0)
356 fprintf(stderr, "couldn't set /chosen/bootargs\n");
357
358 if (kvm_enabled()) {
359 /* Read out host's frequencies */
360 clock_freq = kvmppc_get_clockfreq();
361 tb_freq = kvmppc_get_tbfreq();
362
363 /* indicate KVM hypercall interface */
364 qemu_fdt_add_subnode(fdt, "/hypervisor");
365 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
366 "linux,kvm");
367 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
368 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
369 hypercall, sizeof(hypercall));
370 /* if KVM supports the idle hcall, set property indicating this */
371 if (kvmppc_get_hasidle(env)) {
372 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
373 }
374 }
375
376 /* Create CPU nodes */
377 qemu_fdt_add_subnode(fdt, "/cpus");
378 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
379 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
380
381 /* We need to generate the cpu nodes in reverse order, so Linux can pick
382 the first node as boot node and be happy */
383 for (i = smp_cpus - 1; i >= 0; i--) {
384 CPUState *cpu;
385 char cpu_name[128];
386 uint64_t cpu_release_addr = params->spin_base + (i * 0x20);
387
388 cpu = qemu_get_cpu(i);
389 if (cpu == NULL) {
390 continue;
391 }
392 env = cpu->env_ptr;
393
394 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", i);
395 qemu_fdt_add_subnode(fdt, cpu_name);
396 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
397 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
398 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
399 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
400 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
401 env->dcache_line_size);
402 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
403 env->icache_line_size);
404 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
405 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
406 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
407 if (cpu->cpu_index) {
408 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
409 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
410 "spin-table");
411 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
412 cpu_release_addr);
413 } else {
414 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
415 }
416 }
417
418 qemu_fdt_add_subnode(fdt, "/aliases");
419 /* XXX These should go into their respective devices' code */
420 snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base);
421 qemu_fdt_add_subnode(fdt, soc);
422 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
423 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
424 sizeof(compatible_sb));
425 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
426 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
427 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
428 params->ccsrbar_base >> 32, params->ccsrbar_base,
429 MPC8544_CCSRBAR_SIZE);
430 /* XXX should contain a reasonable value */
431 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
432
433 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
434 qemu_fdt_add_subnode(fdt, mpic);
435 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
436 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
437 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
438 0x40000);
439 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
440 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
441 mpic_ph = qemu_fdt_alloc_phandle(fdt);
442 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
443 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
444 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
445
446 /*
447 * We have to generate ser1 first, because Linux takes the first
448 * device it finds in the dt as serial output device. And we generate
449 * devices in reverse order to the dt.
450 */
451 if (serial_hds[1]) {
452 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
453 soc, mpic, "serial1", 1, false);
454 }
455
456 if (serial_hds[0]) {
457 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
458 soc, mpic, "serial0", 0, true);
459 }
460
461 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
462 MPC8544_UTIL_OFFSET);
463 qemu_fdt_add_subnode(fdt, gutil);
464 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
465 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
466 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
467
468 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
469 qemu_fdt_add_subnode(fdt, msi);
470 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
471 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
472 msi_ph = qemu_fdt_alloc_phandle(fdt);
473 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
474 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
475 qemu_fdt_setprop_cells(fdt, msi, "interrupts",
476 0xe0, 0x0,
477 0xe1, 0x0,
478 0xe2, 0x0,
479 0xe3, 0x0,
480 0xe4, 0x0,
481 0xe5, 0x0,
482 0xe6, 0x0,
483 0xe7, 0x0);
484 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
485 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
486
487 snprintf(pci, sizeof(pci), "/pci@%llx",
488 params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
489 qemu_fdt_add_subnode(fdt, pci);
490 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
491 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
492 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
493 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
494 0x0, 0x7);
495 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
496 params->pci_first_slot, params->pci_nr_slots,
497 &len);
498 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
499 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
500 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
501 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
502 for (i = 0; i < 14; i++) {
503 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
504 }
505 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
506 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
507 qemu_fdt_setprop_cells(fdt, pci, "reg",
508 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
509 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
510 0, 0x1000);
511 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
512 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
513 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
514 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
515 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
516
517 if (params->has_mpc8xxx_gpio) {
518 create_dt_mpc8xxx_gpio(fdt, soc, mpic);
519 }
520
521 if (params->has_platform_bus) {
522 platform_bus_create_devtree(params, fdt, mpic);
523 }
524
525 params->fixup_devtree(params, fdt);
526
527 if (toplevel_compat) {
528 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
529 strlen(toplevel_compat) + 1);
530 }
531
532 done:
533 if (!dry_run) {
534 qemu_fdt_dumpdtb(fdt, fdt_size);
535 cpu_physical_memory_write(addr, fdt, fdt_size);
536 }
537 ret = fdt_size;
538
539 out:
540 g_free(pci_map);
541
542 return ret;
543 }
544
545 typedef struct DeviceTreeParams {
546 MachineState *machine;
547 PPCE500Params params;
548 hwaddr addr;
549 hwaddr initrd_base;
550 hwaddr initrd_size;
551 hwaddr kernel_base;
552 hwaddr kernel_size;
553 Notifier notifier;
554 } DeviceTreeParams;
555
556 static void ppce500_reset_device_tree(void *opaque)
557 {
558 DeviceTreeParams *p = opaque;
559 ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base,
560 p->initrd_size, p->kernel_base, p->kernel_size,
561 false);
562 }
563
564 static void ppce500_init_notify(Notifier *notifier, void *data)
565 {
566 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
567 ppce500_reset_device_tree(p);
568 }
569
570 static int ppce500_prep_device_tree(MachineState *machine,
571 PPCE500Params *params,
572 hwaddr addr,
573 hwaddr initrd_base,
574 hwaddr initrd_size,
575 hwaddr kernel_base,
576 hwaddr kernel_size)
577 {
578 DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
579 p->machine = machine;
580 p->params = *params;
581 p->addr = addr;
582 p->initrd_base = initrd_base;
583 p->initrd_size = initrd_size;
584 p->kernel_base = kernel_base;
585 p->kernel_size = kernel_size;
586
587 qemu_register_reset(ppce500_reset_device_tree, p);
588 p->notifier.notify = ppce500_init_notify;
589 qemu_add_machine_init_done_notifier(&p->notifier);
590
591 /* Issue the device tree loader once, so that we get the size of the blob */
592 return ppce500_load_device_tree(machine, params, addr, initrd_base,
593 initrd_size, kernel_base, kernel_size,
594 true);
595 }
596
597 /* Create -kernel TLB entries for BookE. */
598 hwaddr booke206_page_size_to_tlb(uint64_t size)
599 {
600 return 63 - clz64(size >> 10);
601 }
602
603 static int booke206_initial_map_tsize(CPUPPCState *env)
604 {
605 struct boot_info *bi = env->load_info;
606 hwaddr dt_end;
607 int ps;
608
609 /* Our initial TLB entry needs to cover everything from 0 to
610 the device tree top */
611 dt_end = bi->dt_base + bi->dt_size;
612 ps = booke206_page_size_to_tlb(dt_end) + 1;
613 if (ps & 1) {
614 /* e500v2 can only do even TLB size bits */
615 ps++;
616 }
617 return ps;
618 }
619
620 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
621 {
622 int tsize;
623
624 tsize = booke206_initial_map_tsize(env);
625 return (1ULL << 10 << tsize);
626 }
627
628 static void mmubooke_create_initial_mapping(CPUPPCState *env)
629 {
630 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
631 hwaddr size;
632 int ps;
633
634 ps = booke206_initial_map_tsize(env);
635 size = (ps << MAS1_TSIZE_SHIFT);
636 tlb->mas1 = MAS1_VALID | size;
637 tlb->mas2 = 0;
638 tlb->mas7_3 = 0;
639 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
640
641 env->tlb_dirty = true;
642 }
643
644 static void ppce500_cpu_reset_sec(void *opaque)
645 {
646 PowerPCCPU *cpu = opaque;
647 CPUState *cs = CPU(cpu);
648
649 cpu_reset(cs);
650
651 /* Secondary CPU starts in halted state for now. Needs to change when
652 implementing non-kernel boot. */
653 cs->halted = 1;
654 cs->exception_index = EXCP_HLT;
655 }
656
657 static void ppce500_cpu_reset(void *opaque)
658 {
659 PowerPCCPU *cpu = opaque;
660 CPUState *cs = CPU(cpu);
661 CPUPPCState *env = &cpu->env;
662 struct boot_info *bi = env->load_info;
663
664 cpu_reset(cs);
665
666 /* Set initial guest state. */
667 cs->halted = 0;
668 env->gpr[1] = (16<<20) - 8;
669 env->gpr[3] = bi->dt_base;
670 env->gpr[4] = 0;
671 env->gpr[5] = 0;
672 env->gpr[6] = EPAPR_MAGIC;
673 env->gpr[7] = mmubooke_initial_mapsize(env);
674 env->gpr[8] = 0;
675 env->gpr[9] = 0;
676 env->nip = bi->entry;
677 mmubooke_create_initial_mapping(env);
678 }
679
680 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
681 qemu_irq **irqs)
682 {
683 DeviceState *dev;
684 SysBusDevice *s;
685 int i, j, k;
686
687 dev = qdev_create(NULL, TYPE_OPENPIC);
688 object_property_add_child(qdev_get_machine(), "pic", OBJECT(dev),
689 &error_fatal);
690 qdev_prop_set_uint32(dev, "model", params->mpic_version);
691 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
692
693 qdev_init_nofail(dev);
694 s = SYS_BUS_DEVICE(dev);
695
696 k = 0;
697 for (i = 0; i < smp_cpus; i++) {
698 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
699 sysbus_connect_irq(s, k++, irqs[i][j]);
700 }
701 }
702
703 return dev;
704 }
705
706 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
707 qemu_irq **irqs, Error **errp)
708 {
709 Error *err = NULL;
710 DeviceState *dev;
711 CPUState *cs;
712
713 dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
714 qdev_prop_set_uint32(dev, "model", params->mpic_version);
715
716 object_property_set_bool(OBJECT(dev), true, "realized", &err);
717 if (err) {
718 error_propagate(errp, err);
719 object_unparent(OBJECT(dev));
720 return NULL;
721 }
722
723 CPU_FOREACH(cs) {
724 if (kvm_openpic_connect_vcpu(dev, cs)) {
725 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
726 __func__);
727 abort();
728 }
729 }
730
731 return dev;
732 }
733
734 static DeviceState *ppce500_init_mpic(MachineState *machine,
735 PPCE500Params *params,
736 MemoryRegion *ccsr,
737 qemu_irq **irqs)
738 {
739 DeviceState *dev = NULL;
740 SysBusDevice *s;
741
742 if (kvm_enabled()) {
743 Error *err = NULL;
744
745 if (machine_kernel_irqchip_allowed(machine)) {
746 dev = ppce500_init_mpic_kvm(params, irqs, &err);
747 }
748 if (machine_kernel_irqchip_required(machine) && !dev) {
749 error_reportf_err(err,
750 "kernel_irqchip requested but unavailable: ");
751 exit(1);
752 }
753 }
754
755 if (!dev) {
756 dev = ppce500_init_mpic_qemu(params, irqs);
757 }
758
759 s = SYS_BUS_DEVICE(dev);
760 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
761 s->mmio[0].memory);
762
763 return dev;
764 }
765
766 static void ppce500_power_off(void *opaque, int line, int on)
767 {
768 if (on) {
769 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
770 }
771 }
772
773 void ppce500_init(MachineState *machine, PPCE500Params *params)
774 {
775 MemoryRegion *address_space_mem = get_system_memory();
776 MemoryRegion *ram = g_new(MemoryRegion, 1);
777 PCIBus *pci_bus;
778 CPUPPCState *env = NULL;
779 uint64_t loadaddr;
780 hwaddr kernel_base = -1LL;
781 int kernel_size = 0;
782 hwaddr dt_base = 0;
783 hwaddr initrd_base = 0;
784 int initrd_size = 0;
785 hwaddr cur_base = 0;
786 char *filename;
787 hwaddr bios_entry = 0;
788 target_long bios_size;
789 struct boot_info *boot_info;
790 int dt_size;
791 int i;
792 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
793 * 4 respectively */
794 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
795 qemu_irq **irqs;
796 DeviceState *dev, *mpicdev;
797 CPUPPCState *firstenv = NULL;
798 MemoryRegion *ccsr_addr_space;
799 SysBusDevice *s;
800 PPCE500CCSRState *ccsr;
801
802 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
803 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
804 for (i = 0; i < smp_cpus; i++) {
805 PowerPCCPU *cpu;
806 CPUState *cs;
807 qemu_irq *input;
808
809 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
810 env = &cpu->env;
811 cs = CPU(cpu);
812
813 if (env->mmu_model != POWERPC_MMU_BOOKE206) {
814 error_report("MMU model %i not supported by this machine",
815 env->mmu_model);
816 exit(1);
817 }
818
819 if (!firstenv) {
820 firstenv = env;
821 }
822
823 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
824 input = (qemu_irq *)env->irq_inputs;
825 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
826 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
827 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
828 env->mpic_iack = params->ccsrbar_base +
829 MPC8544_MPIC_REGS_OFFSET + 0xa0;
830
831 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
832
833 /* Register reset handler */
834 if (!i) {
835 /* Primary CPU */
836 struct boot_info *boot_info;
837 boot_info = g_malloc0(sizeof(struct boot_info));
838 qemu_register_reset(ppce500_cpu_reset, cpu);
839 env->load_info = boot_info;
840 } else {
841 /* Secondary CPUs */
842 qemu_register_reset(ppce500_cpu_reset_sec, cpu);
843 }
844 }
845
846 env = firstenv;
847
848 /* Fixup Memory size on a alignment boundary */
849 ram_size &= ~(RAM_SIZES_ALIGN - 1);
850 machine->ram_size = ram_size;
851
852 /* Register Memory */
853 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size);
854 memory_region_add_subregion(address_space_mem, 0, ram);
855
856 dev = qdev_create(NULL, "e500-ccsr");
857 object_property_add_child(qdev_get_machine(), "e500-ccsr",
858 OBJECT(dev), NULL);
859 qdev_init_nofail(dev);
860 ccsr = CCSR(dev);
861 ccsr_addr_space = &ccsr->ccsr_space;
862 memory_region_add_subregion(address_space_mem, params->ccsrbar_base,
863 ccsr_addr_space);
864
865 mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
866
867 /* Serial */
868 if (serial_hds[0]) {
869 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
870 0, qdev_get_gpio_in(mpicdev, 42), 399193,
871 serial_hds[0], DEVICE_BIG_ENDIAN);
872 }
873
874 if (serial_hds[1]) {
875 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
876 0, qdev_get_gpio_in(mpicdev, 42), 399193,
877 serial_hds[1], DEVICE_BIG_ENDIAN);
878 }
879
880 /* General Utility device */
881 dev = qdev_create(NULL, "mpc8544-guts");
882 qdev_init_nofail(dev);
883 s = SYS_BUS_DEVICE(dev);
884 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
885 sysbus_mmio_get_region(s, 0));
886
887 /* PCI */
888 dev = qdev_create(NULL, "e500-pcihost");
889 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev),
890 &error_abort);
891 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
892 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
893 qdev_init_nofail(dev);
894 s = SYS_BUS_DEVICE(dev);
895 for (i = 0; i < PCI_NUM_PINS; i++) {
896 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
897 }
898
899 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
900 sysbus_mmio_get_region(s, 0));
901
902 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
903 if (!pci_bus)
904 printf("couldn't create PCI controller!\n");
905
906 if (pci_bus) {
907 /* Register network interfaces. */
908 for (i = 0; i < nb_nics; i++) {
909 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL);
910 }
911 }
912
913 /* Register spinning region */
914 sysbus_create_simple("e500-spin", params->spin_base, NULL);
915
916 if (cur_base < (32 * 1024 * 1024)) {
917 /* u-boot occupies memory up to 32MB, so load blobs above */
918 cur_base = (32 * 1024 * 1024);
919 }
920
921 if (params->has_mpc8xxx_gpio) {
922 qemu_irq poweroff_irq;
923
924 dev = qdev_create(NULL, "mpc8xxx_gpio");
925 s = SYS_BUS_DEVICE(dev);
926 qdev_init_nofail(dev);
927 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
928 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
929 sysbus_mmio_get_region(s, 0));
930
931 /* Power Off GPIO at Pin 0 */
932 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
933 qdev_connect_gpio_out(dev, 0, poweroff_irq);
934 }
935
936 /* Platform Bus Device */
937 if (params->has_platform_bus) {
938 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
939 dev->id = TYPE_PLATFORM_BUS_DEVICE;
940 qdev_prop_set_uint32(dev, "num_irqs", params->platform_bus_num_irqs);
941 qdev_prop_set_uint32(dev, "mmio_size", params->platform_bus_size);
942 qdev_init_nofail(dev);
943 s = SYS_BUS_DEVICE(dev);
944
945 for (i = 0; i < params->platform_bus_num_irqs; i++) {
946 int irqn = params->platform_bus_first_irq + i;
947 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
948 }
949
950 memory_region_add_subregion(address_space_mem,
951 params->platform_bus_base,
952 sysbus_mmio_get_region(s, 0));
953 }
954
955 /* Load kernel. */
956 if (machine->kernel_filename) {
957 kernel_base = cur_base;
958 kernel_size = load_image_targphys(machine->kernel_filename,
959 cur_base,
960 ram_size - cur_base);
961 if (kernel_size < 0) {
962 error_report("could not load kernel '%s'",
963 machine->kernel_filename);
964 exit(1);
965 }
966
967 cur_base += kernel_size;
968 }
969
970 /* Load initrd. */
971 if (machine->initrd_filename) {
972 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
973 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
974 ram_size - initrd_base);
975
976 if (initrd_size < 0) {
977 error_report("could not load initial ram disk '%s'",
978 machine->initrd_filename);
979 exit(1);
980 }
981
982 cur_base = initrd_base + initrd_size;
983 }
984
985 /*
986 * Smart firmware defaults ahead!
987 *
988 * We follow the following table to select which payload we execute.
989 *
990 * -kernel | -bios | payload
991 * ---------+-------+---------
992 * N | Y | u-boot
993 * N | N | u-boot
994 * Y | Y | u-boot
995 * Y | N | kernel
996 *
997 * This ensures backwards compatibility with how we used to expose
998 * -kernel to users but allows them to run through u-boot as well.
999 */
1000 if (bios_name == NULL) {
1001 if (machine->kernel_filename) {
1002 bios_name = machine->kernel_filename;
1003 } else {
1004 bios_name = "u-boot.e500";
1005 }
1006 }
1007 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1008
1009 bios_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL,
1010 1, PPC_ELF_MACHINE, 0, 0);
1011 if (bios_size < 0) {
1012 /*
1013 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1014 * ePAPR compliant kernel
1015 */
1016 kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1017 NULL, NULL);
1018 if (kernel_size < 0) {
1019 error_report("could not load firmware '%s'", filename);
1020 exit(1);
1021 }
1022 }
1023 g_free(filename);
1024
1025 /* Reserve space for dtb */
1026 dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1027
1028 dt_size = ppce500_prep_device_tree(machine, params, dt_base,
1029 initrd_base, initrd_size,
1030 kernel_base, kernel_size);
1031 if (dt_size < 0) {
1032 error_report("couldn't load device tree");
1033 exit(1);
1034 }
1035 assert(dt_size < DTB_MAX_SIZE);
1036
1037 boot_info = env->load_info;
1038 boot_info->entry = bios_entry;
1039 boot_info->dt_base = dt_base;
1040 boot_info->dt_size = dt_size;
1041 }
1042
1043 static void e500_ccsr_initfn(Object *obj)
1044 {
1045 PPCE500CCSRState *ccsr = CCSR(obj);
1046 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
1047 MPC8544_CCSRBAR_SIZE);
1048 }
1049
1050 static const TypeInfo e500_ccsr_info = {
1051 .name = TYPE_CCSR,
1052 .parent = TYPE_SYS_BUS_DEVICE,
1053 .instance_size = sizeof(PPCE500CCSRState),
1054 .instance_init = e500_ccsr_initfn,
1055 };
1056
1057 static void e500_register_types(void)
1058 {
1059 type_register_static(&e500_ccsr_info);
1060 }
1061
1062 type_init(e500_register_types)