]> git.ipfire.org Git - thirdparty/qemu.git/blob - hw/ppc/spapr_events.c
projects / thirdparty / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request...
[thirdparty/qemu.git] / hw / ppc / spapr_events.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * RTAS events handling
5 *
6 * Copyright (c) 2012 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "cpu.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/runstate.h"
33
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/ppc/spapr_vio.h"
37 #include "hw/pci/pci.h"
38 #include "hw/irq.h"
39 #include "hw/pci-host/spapr.h"
40 #include "hw/ppc/spapr_drc.h"
41 #include "qemu/help_option.h"
42 #include "qemu/bcd.h"
43 #include "qemu/main-loop.h"
44 #include "hw/ppc/spapr_ovec.h"
45 #include <libfdt.h>
46 #include "migration/blocker.h"
47
48 #define RTAS_LOG_VERSION_MASK 0xff000000
49 #define RTAS_LOG_VERSION_6 0x06000000
50 #define RTAS_LOG_SEVERITY_MASK 0x00e00000
51 #define RTAS_LOG_SEVERITY_ALREADY_REPORTED 0x00c00000
52 #define RTAS_LOG_SEVERITY_FATAL 0x00a00000
53 #define RTAS_LOG_SEVERITY_ERROR 0x00800000
54 #define RTAS_LOG_SEVERITY_ERROR_SYNC 0x00600000
55 #define RTAS_LOG_SEVERITY_WARNING 0x00400000
56 #define RTAS_LOG_SEVERITY_EVENT 0x00200000
57 #define RTAS_LOG_SEVERITY_NO_ERROR 0x00000000
58 #define RTAS_LOG_DISPOSITION_MASK 0x00180000
59 #define RTAS_LOG_DISPOSITION_FULLY_RECOVERED 0x00000000
60 #define RTAS_LOG_DISPOSITION_LIMITED_RECOVERY 0x00080000
61 #define RTAS_LOG_DISPOSITION_NOT_RECOVERED 0x00100000
62 #define RTAS_LOG_OPTIONAL_PART_PRESENT 0x00040000
63 #define RTAS_LOG_INITIATOR_MASK 0x0000f000
64 #define RTAS_LOG_INITIATOR_UNKNOWN 0x00000000
65 #define RTAS_LOG_INITIATOR_CPU 0x00001000
66 #define RTAS_LOG_INITIATOR_PCI 0x00002000
67 #define RTAS_LOG_INITIATOR_MEMORY 0x00004000
68 #define RTAS_LOG_INITIATOR_HOTPLUG 0x00006000
69 #define RTAS_LOG_TARGET_MASK 0x00000f00
70 #define RTAS_LOG_TARGET_UNKNOWN 0x00000000
71 #define RTAS_LOG_TARGET_CPU 0x00000100
72 #define RTAS_LOG_TARGET_PCI 0x00000200
73 #define RTAS_LOG_TARGET_MEMORY 0x00000400
74 #define RTAS_LOG_TARGET_HOTPLUG 0x00000600
75 #define RTAS_LOG_TYPE_MASK 0x000000ff
76 #define RTAS_LOG_TYPE_OTHER 0x00000000
77 #define RTAS_LOG_TYPE_RETRY 0x00000001
78 #define RTAS_LOG_TYPE_TCE_ERR 0x00000002
79 #define RTAS_LOG_TYPE_INTERN_DEV_FAIL 0x00000003
80 #define RTAS_LOG_TYPE_TIMEOUT 0x00000004
81 #define RTAS_LOG_TYPE_DATA_PARITY 0x00000005
82 #define RTAS_LOG_TYPE_ADDR_PARITY 0x00000006
83 #define RTAS_LOG_TYPE_CACHE_PARITY 0x00000007
84 #define RTAS_LOG_TYPE_ADDR_INVALID 0x00000008
85 #define RTAS_LOG_TYPE_ECC_UNCORR 0x00000009
86 #define RTAS_LOG_TYPE_ECC_CORR 0x0000000a
87 #define RTAS_LOG_TYPE_EPOW 0x00000040
88 #define RTAS_LOG_TYPE_HOTPLUG 0x000000e5
89
90 struct rtas_error_log {
91 uint32_t summary;
92 uint32_t extended_length;
93 } QEMU_PACKED;
94
95 struct rtas_event_log_v6 {
96 uint8_t b0;
97 #define RTAS_LOG_V6_B0_VALID 0x80
98 #define RTAS_LOG_V6_B0_UNRECOVERABLE_ERROR 0x40
99 #define RTAS_LOG_V6_B0_RECOVERABLE_ERROR 0x20
100 #define RTAS_LOG_V6_B0_DEGRADED_OPERATION 0x10
101 #define RTAS_LOG_V6_B0_PREDICTIVE_ERROR 0x08
102 #define RTAS_LOG_V6_B0_NEW_LOG 0x04
103 #define RTAS_LOG_V6_B0_BIGENDIAN 0x02
104 uint8_t _resv1;
105 uint8_t b2;
106 #define RTAS_LOG_V6_B2_POWERPC_FORMAT 0x80
107 #define RTAS_LOG_V6_B2_LOG_FORMAT_MASK 0x0f
108 #define RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT 0x0e
109 uint8_t _resv2[9];
110 uint32_t company;
111 #define RTAS_LOG_V6_COMPANY_IBM 0x49424d00 /* IBM<null> */
112 } QEMU_PACKED;
113
114 struct rtas_event_log_v6_section_header {
115 uint16_t section_id;
116 uint16_t section_length;
117 uint8_t section_version;
118 uint8_t section_subtype;
119 uint16_t creator_component_id;
120 } QEMU_PACKED;
121
122 struct rtas_event_log_v6_maina {
123 #define RTAS_LOG_V6_SECTION_ID_MAINA 0x5048 /* PH */
124 struct rtas_event_log_v6_section_header hdr;
125 uint32_t creation_date; /* BCD: YYYYMMDD */
126 uint32_t creation_time; /* BCD: HHMMSS00 */
127 uint8_t _platform1[8];
128 char creator_id;
129 uint8_t _resv1[2];
130 uint8_t section_count;
131 uint8_t _resv2[4];
132 uint8_t _platform2[8];
133 uint32_t plid;
134 uint8_t _platform3[4];
135 } QEMU_PACKED;
136
137 struct rtas_event_log_v6_mainb {
138 #define RTAS_LOG_V6_SECTION_ID_MAINB 0x5548 /* UH */
139 struct rtas_event_log_v6_section_header hdr;
140 uint8_t subsystem_id;
141 uint8_t _platform1;
142 uint8_t event_severity;
143 uint8_t event_subtype;
144 uint8_t _platform2[4];
145 uint8_t _resv1[2];
146 uint16_t action_flags;
147 uint8_t _resv2[4];
148 } QEMU_PACKED;
149
150 struct rtas_event_log_v6_epow {
151 #define RTAS_LOG_V6_SECTION_ID_EPOW 0x4550 /* EP */
152 struct rtas_event_log_v6_section_header hdr;
153 uint8_t sensor_value;
154 #define RTAS_LOG_V6_EPOW_ACTION_RESET 0
155 #define RTAS_LOG_V6_EPOW_ACTION_WARN_COOLING 1
156 #define RTAS_LOG_V6_EPOW_ACTION_WARN_POWER 2
157 #define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN 3
158 #define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_HALT 4
159 #define RTAS_LOG_V6_EPOW_ACTION_MAIN_ENCLOSURE 5
160 #define RTAS_LOG_V6_EPOW_ACTION_POWER_OFF 7
161 uint8_t event_modifier;
162 #define RTAS_LOG_V6_EPOW_MODIFIER_NORMAL 1
163 #define RTAS_LOG_V6_EPOW_MODIFIER_ON_UPS 2
164 #define RTAS_LOG_V6_EPOW_MODIFIER_CRITICAL 3
165 #define RTAS_LOG_V6_EPOW_MODIFIER_TEMPERATURE 4
166 uint8_t extended_modifier;
167 #define RTAS_LOG_V6_EPOW_XMODIFIER_SYSTEM_WIDE 0
168 #define RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC 1
169 uint8_t _resv;
170 uint64_t reason_code;
171 } QEMU_PACKED;
172
173 struct epow_extended_log {
174 struct rtas_event_log_v6 v6hdr;
175 struct rtas_event_log_v6_maina maina;
176 struct rtas_event_log_v6_mainb mainb;
177 struct rtas_event_log_v6_epow epow;
178 } QEMU_PACKED;
179
180 union drc_identifier {
181 uint32_t index;
182 uint32_t count;
183 struct {
184 uint32_t count;
185 uint32_t index;
186 } count_indexed;
187 char name[1];
188 } QEMU_PACKED;
189
190 struct rtas_event_log_v6_hp {
191 #define RTAS_LOG_V6_SECTION_ID_HOTPLUG 0x4850 /* HP */
192 struct rtas_event_log_v6_section_header hdr;
193 uint8_t hotplug_type;
194 #define RTAS_LOG_V6_HP_TYPE_CPU 1
195 #define RTAS_LOG_V6_HP_TYPE_MEMORY 2
196 #define RTAS_LOG_V6_HP_TYPE_SLOT 3
197 #define RTAS_LOG_V6_HP_TYPE_PHB 4
198 #define RTAS_LOG_V6_HP_TYPE_PCI 5
199 #define RTAS_LOG_V6_HP_TYPE_PMEM 6
200 uint8_t hotplug_action;
201 #define RTAS_LOG_V6_HP_ACTION_ADD 1
202 #define RTAS_LOG_V6_HP_ACTION_REMOVE 2
203 uint8_t hotplug_identifier;
204 #define RTAS_LOG_V6_HP_ID_DRC_NAME 1
205 #define RTAS_LOG_V6_HP_ID_DRC_INDEX 2
206 #define RTAS_LOG_V6_HP_ID_DRC_COUNT 3
207 #define RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED 4
208 uint8_t reserved;
209 union drc_identifier drc_id;
210 } QEMU_PACKED;
211
212 struct hp_extended_log {
213 struct rtas_event_log_v6 v6hdr;
214 struct rtas_event_log_v6_maina maina;
215 struct rtas_event_log_v6_mainb mainb;
216 struct rtas_event_log_v6_hp hp;
217 } QEMU_PACKED;
218
219 struct rtas_event_log_v6_mc {
220 #define RTAS_LOG_V6_SECTION_ID_MC 0x4D43 /* MC */
221 struct rtas_event_log_v6_section_header hdr;
222 uint32_t fru_id;
223 uint32_t proc_id;
224 uint8_t error_type;
225 #define RTAS_LOG_V6_MC_TYPE_UE 0
226 #define RTAS_LOG_V6_MC_TYPE_SLB 1
227 #define RTAS_LOG_V6_MC_TYPE_ERAT 2
228 #define RTAS_LOG_V6_MC_TYPE_TLB 4
229 #define RTAS_LOG_V6_MC_TYPE_D_CACHE 5
230 #define RTAS_LOG_V6_MC_TYPE_I_CACHE 7
231 uint8_t sub_err_type;
232 #define RTAS_LOG_V6_MC_UE_INDETERMINATE 0
233 #define RTAS_LOG_V6_MC_UE_IFETCH 1
234 #define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH 2
235 #define RTAS_LOG_V6_MC_UE_LOAD_STORE 3
236 #define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE 4
237 #define RTAS_LOG_V6_MC_SLB_PARITY 0
238 #define RTAS_LOG_V6_MC_SLB_MULTIHIT 1
239 #define RTAS_LOG_V6_MC_SLB_INDETERMINATE 2
240 #define RTAS_LOG_V6_MC_ERAT_PARITY 1
241 #define RTAS_LOG_V6_MC_ERAT_MULTIHIT 2
242 #define RTAS_LOG_V6_MC_ERAT_INDETERMINATE 3
243 #define RTAS_LOG_V6_MC_TLB_PARITY 1
244 #define RTAS_LOG_V6_MC_TLB_MULTIHIT 2
245 #define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3
246 uint8_t reserved_1[6];
247 uint64_t effective_address;
248 uint64_t logical_address;
249 } QEMU_PACKED;
250
251 struct mc_extended_log {
252 struct rtas_event_log_v6 v6hdr;
253 struct rtas_event_log_v6_mc mc;
254 } QEMU_PACKED;
255
256 struct MC_ierror_table {
257 unsigned long srr1_mask;
258 unsigned long srr1_value;
259 bool nip_valid; /* nip is a valid indicator of faulting address */
260 uint8_t error_type;
261 uint8_t error_subtype;
262 unsigned int initiator;
263 unsigned int severity;
264 };
265
266 static const struct MC_ierror_table mc_ierror_table[] = {
267 { 0x00000000081c0000, 0x0000000000040000, true,
268 RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_IFETCH,
269 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
270 { 0x00000000081c0000, 0x0000000000080000, true,
271 RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY,
272 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
273 { 0x00000000081c0000, 0x00000000000c0000, true,
274 RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT,
275 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
276 { 0x00000000081c0000, 0x0000000000100000, true,
277 RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT,
278 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
279 { 0x00000000081c0000, 0x0000000000140000, true,
280 RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT,
281 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
282 { 0x00000000081c0000, 0x0000000000180000, true,
283 RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH,
284 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } };
285
286 struct MC_derror_table {
287 unsigned long dsisr_value;
288 bool dar_valid; /* dar is a valid indicator of faulting address */
289 uint8_t error_type;
290 uint8_t error_subtype;
291 unsigned int initiator;
292 unsigned int severity;
293 };
294
295 static const struct MC_derror_table mc_derror_table[] = {
296 { 0x00008000, false,
297 RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_LOAD_STORE,
298 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
299 { 0x00004000, true,
300 RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE,
301 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
302 { 0x00000800, true,
303 RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT,
304 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
305 { 0x00000400, true,
306 RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT,
307 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
308 { 0x00000080, true,
309 RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, /* Before PARITY */
310 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, },
311 { 0x00000100, true,
312 RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY,
313 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } };
314
315 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
316
317 typedef enum EventClass {
318 EVENT_CLASS_INTERNAL_ERRORS = 0,
319 EVENT_CLASS_EPOW = 1,
320 EVENT_CLASS_RESERVED = 2,
321 EVENT_CLASS_HOT_PLUG = 3,
322 EVENT_CLASS_IO = 4,
323 EVENT_CLASS_MAX
324 } EventClassIndex;
325 #define EVENT_CLASS_MASK(index) (1 << (31 - index))
326
327 static const char * const event_names[EVENT_CLASS_MAX] = {
328 [EVENT_CLASS_INTERNAL_ERRORS] = "internal-errors",
329 [EVENT_CLASS_EPOW] = "epow-events",
330 [EVENT_CLASS_HOT_PLUG] = "hot-plug-events",
331 [EVENT_CLASS_IO] = "ibm,io-events",
332 };
333
334 struct SpaprEventSource {
335 int irq;
336 uint32_t mask;
337 bool enabled;
338 };
339
340 static SpaprEventSource *spapr_event_sources_new(void)
341 {
342 return g_new0(SpaprEventSource, EVENT_CLASS_MAX);
343 }
344
345 static void spapr_event_sources_register(SpaprEventSource *event_sources,
346 EventClassIndex index, int irq)
347 {
348 /* we only support 1 irq per event class at the moment */
349 g_assert(event_sources);
350 g_assert(!event_sources[index].enabled);
351 event_sources[index].irq = irq;
352 event_sources[index].mask = EVENT_CLASS_MASK(index);
353 event_sources[index].enabled = true;
354 }
355
356 static const SpaprEventSource *
357 spapr_event_sources_get_source(SpaprEventSource *event_sources,
358 EventClassIndex index)
359 {
360 g_assert(index < EVENT_CLASS_MAX);
361 g_assert(event_sources);
362
363 return &event_sources[index];
364 }
365
366 void spapr_dt_events(SpaprMachineState *spapr, void *fdt)
367 {
368 uint32_t irq_ranges[EVENT_CLASS_MAX * 2];
369 int i, count = 0, event_sources;
370 SpaprEventSource *events = spapr->event_sources;
371
372 g_assert(events);
373
374 _FDT(event_sources = fdt_add_subnode(fdt, 0, "event-sources"));
375
376 for (i = 0, count = 0; i < EVENT_CLASS_MAX; i++) {
377 int node_offset;
378 uint32_t interrupts[2];
379 const SpaprEventSource *source =
380 spapr_event_sources_get_source(events, i);
381 const char *source_name = event_names[i];
382
383 if (!source->enabled) {
384 continue;
385 }
386
387 spapr_dt_irq(interrupts, source->irq, false);
388
389 _FDT(node_offset = fdt_add_subnode(fdt, event_sources, source_name));
390 _FDT(fdt_setprop(fdt, node_offset, "interrupts", interrupts,
391 sizeof(interrupts)));
392
393 irq_ranges[count++] = interrupts[0];
394 irq_ranges[count++] = cpu_to_be32(1);
395 }
396
397 _FDT((fdt_setprop(fdt, event_sources, "interrupt-controller", NULL, 0)));
398 _FDT((fdt_setprop_cell(fdt, event_sources, "#interrupt-cells", 2)));
399 _FDT((fdt_setprop(fdt, event_sources, "interrupt-ranges",
400 irq_ranges, count * sizeof(uint32_t))));
401 }
402
403 static const SpaprEventSource *
404 rtas_event_log_to_source(SpaprMachineState *spapr, int log_type)
405 {
406 const SpaprEventSource *source;
407
408 g_assert(spapr->event_sources);
409
410 switch (log_type) {
411 case RTAS_LOG_TYPE_HOTPLUG:
412 source = spapr_event_sources_get_source(spapr->event_sources,
413 EVENT_CLASS_HOT_PLUG);
414 if (spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)) {
415 g_assert(source->enabled);
416 break;
417 }
418 /* fall through back to epow for legacy hotplug interrupt source */
419 case RTAS_LOG_TYPE_EPOW:
420 source = spapr_event_sources_get_source(spapr->event_sources,
421 EVENT_CLASS_EPOW);
422 break;
423 default:
424 source = NULL;
425 }
426
427 return source;
428 }
429
430 static int rtas_event_log_to_irq(SpaprMachineState *spapr, int log_type)
431 {
432 const SpaprEventSource *source;
433
434 source = rtas_event_log_to_source(spapr, log_type);
435 g_assert(source);
436 g_assert(source->enabled);
437
438 return source->irq;
439 }
440
441 static uint32_t spapr_event_log_entry_type(SpaprEventLogEntry *entry)
442 {
443 return entry->summary & RTAS_LOG_TYPE_MASK;
444 }
445
446 static void rtas_event_log_queue(SpaprMachineState *spapr,
447 SpaprEventLogEntry *entry)
448 {
449 QTAILQ_INSERT_TAIL(&spapr->pending_events, entry, next);
450 }
451
452 static SpaprEventLogEntry *rtas_event_log_dequeue(SpaprMachineState *spapr,
453 uint32_t event_mask)
454 {
455 SpaprEventLogEntry *entry = NULL;
456
457 QTAILQ_FOREACH(entry, &spapr->pending_events, next) {
458 const SpaprEventSource *source =
459 rtas_event_log_to_source(spapr,
460 spapr_event_log_entry_type(entry));
461
462 g_assert(source);
463 if (source->mask & event_mask) {
464 break;
465 }
466 }
467
468 if (entry) {
469 QTAILQ_REMOVE(&spapr->pending_events, entry, next);
470 }
471
472 return entry;
473 }
474
475 static bool rtas_event_log_contains(uint32_t event_mask)
476 {
477 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
478 SpaprEventLogEntry *entry = NULL;
479
480 QTAILQ_FOREACH(entry, &spapr->pending_events, next) {
481 const SpaprEventSource *source =
482 rtas_event_log_to_source(spapr,
483 spapr_event_log_entry_type(entry));
484
485 if (source->mask & event_mask) {
486 return true;
487 }
488 }
489
490 return false;
491 }
492
493 static uint32_t next_plid;
494
495 static void spapr_init_v6hdr(struct rtas_event_log_v6 *v6hdr)
496 {
497 v6hdr->b0 = RTAS_LOG_V6_B0_VALID | RTAS_LOG_V6_B0_NEW_LOG
498 | RTAS_LOG_V6_B0_BIGENDIAN;
499 v6hdr->b2 = RTAS_LOG_V6_B2_POWERPC_FORMAT
500 | RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT;
501 v6hdr->company = cpu_to_be32(RTAS_LOG_V6_COMPANY_IBM);
502 }
503
504 static void spapr_init_maina(struct rtas_event_log_v6_maina *maina,
505 int section_count)
506 {
507 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
508 struct tm tm;
509 int year;
510
511 maina->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINA);
512 maina->hdr.section_length = cpu_to_be16(sizeof(*maina));
513 /* FIXME: section version, subtype and creator id? */
514 spapr_rtc_read(&spapr->rtc, &tm, NULL);
515 year = tm.tm_year + 1900;
516 maina->creation_date = cpu_to_be32((to_bcd(year / 100) << 24)
517 | (to_bcd(year % 100) << 16)
518 | (to_bcd(tm.tm_mon + 1) << 8)
519 | to_bcd(tm.tm_mday));
520 maina->creation_time = cpu_to_be32((to_bcd(tm.tm_hour) << 24)
521 | (to_bcd(tm.tm_min) << 16)
522 | (to_bcd(tm.tm_sec) << 8));
523 maina->creator_id = 'H'; /* Hypervisor */
524 maina->section_count = section_count;
525 maina->plid = next_plid++;
526 }
527
528 static void spapr_powerdown_req(Notifier *n, void *opaque)
529 {
530 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
531 SpaprEventLogEntry *entry;
532 struct rtas_event_log_v6 *v6hdr;
533 struct rtas_event_log_v6_maina *maina;
534 struct rtas_event_log_v6_mainb *mainb;
535 struct rtas_event_log_v6_epow *epow;
536 struct epow_extended_log *new_epow;
537
538 entry = g_new(SpaprEventLogEntry, 1);
539 new_epow = g_malloc0(sizeof(*new_epow));
540 entry->extended_log = new_epow;
541
542 v6hdr = &new_epow->v6hdr;
543 maina = &new_epow->maina;
544 mainb = &new_epow->mainb;
545 epow = &new_epow->epow;
546
547 entry->summary = RTAS_LOG_VERSION_6
548 | RTAS_LOG_SEVERITY_EVENT
549 | RTAS_LOG_DISPOSITION_NOT_RECOVERED
550 | RTAS_LOG_OPTIONAL_PART_PRESENT
551 | RTAS_LOG_TYPE_EPOW;
552 entry->extended_length = sizeof(*new_epow);
553
554 spapr_init_v6hdr(v6hdr);
555 spapr_init_maina(maina, 3 /* Main-A, Main-B and EPOW */);
556
557 mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB);
558 mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb));
559 /* FIXME: section version, subtype and creator id? */
560 mainb->subsystem_id = 0xa0; /* External environment */
561 mainb->event_severity = 0x00; /* Informational / non-error */
562 mainb->event_subtype = 0xd0; /* Normal shutdown */
563
564 epow->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_EPOW);
565 epow->hdr.section_length = cpu_to_be16(sizeof(*epow));
566 epow->hdr.section_version = 2; /* includes extended modifier */
567 /* FIXME: section subtype and creator id? */
568 epow->sensor_value = RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN;
569 epow->event_modifier = RTAS_LOG_V6_EPOW_MODIFIER_NORMAL;
570 epow->extended_modifier = RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC;
571
572 rtas_event_log_queue(spapr, entry);
573
574 qemu_irq_pulse(spapr_qirq(spapr,
575 rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_EPOW)));
576 }
577
578 static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action,
579 SpaprDrcType drc_type,
580 union drc_identifier *drc_id)
581 {
582 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
583 SpaprEventLogEntry *entry;
584 struct hp_extended_log *new_hp;
585 struct rtas_event_log_v6 *v6hdr;
586 struct rtas_event_log_v6_maina *maina;
587 struct rtas_event_log_v6_mainb *mainb;
588 struct rtas_event_log_v6_hp *hp;
589
590 entry = g_new(SpaprEventLogEntry, 1);
591 new_hp = g_malloc0(sizeof(struct hp_extended_log));
592 entry->extended_log = new_hp;
593
594 v6hdr = &new_hp->v6hdr;
595 maina = &new_hp->maina;
596 mainb = &new_hp->mainb;
597 hp = &new_hp->hp;
598
599 entry->summary = RTAS_LOG_VERSION_6
600 | RTAS_LOG_SEVERITY_EVENT
601 | RTAS_LOG_DISPOSITION_NOT_RECOVERED
602 | RTAS_LOG_OPTIONAL_PART_PRESENT
603 | RTAS_LOG_INITIATOR_HOTPLUG
604 | RTAS_LOG_TYPE_HOTPLUG;
605 entry->extended_length = sizeof(*new_hp);
606
607 spapr_init_v6hdr(v6hdr);
608 spapr_init_maina(maina, 3 /* Main-A, Main-B, HP */);
609
610 mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB);
611 mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb));
612 mainb->subsystem_id = 0x80; /* External environment */
613 mainb->event_severity = 0x00; /* Informational / non-error */
614 mainb->event_subtype = 0x00; /* Normal shutdown */
615
616 hp->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_HOTPLUG);
617 hp->hdr.section_length = cpu_to_be16(sizeof(*hp));
618 hp->hdr.section_version = 1; /* includes extended modifier */
619 hp->hotplug_action = hp_action;
620 hp->hotplug_identifier = hp_id;
621
622 switch (drc_type) {
623 case SPAPR_DR_CONNECTOR_TYPE_PCI:
624 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PCI;
625 break;
626 case SPAPR_DR_CONNECTOR_TYPE_LMB:
627 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_MEMORY;
628 break;
629 case SPAPR_DR_CONNECTOR_TYPE_CPU:
630 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_CPU;
631 break;
632 case SPAPR_DR_CONNECTOR_TYPE_PHB:
633 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PHB;
634 break;
635 case SPAPR_DR_CONNECTOR_TYPE_PMEM:
636 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PMEM;
637 break;
638 default:
639 /* we shouldn't be signaling hotplug events for resources
640 * that don't support them
641 */
642 g_assert(false);
643 return;
644 }
645
646 if (hp_id == RTAS_LOG_V6_HP_ID_DRC_COUNT) {
647 hp->drc_id.count = cpu_to_be32(drc_id->count);
648 } else if (hp_id == RTAS_LOG_V6_HP_ID_DRC_INDEX) {
649 hp->drc_id.index = cpu_to_be32(drc_id->index);
650 } else if (hp_id == RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED) {
651 /* we should not be using count_indexed value unless the guest
652 * supports dedicated hotplug event source
653 */
654 g_assert(spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT));
655 hp->drc_id.count_indexed.count =
656 cpu_to_be32(drc_id->count_indexed.count);
657 hp->drc_id.count_indexed.index =
658 cpu_to_be32(drc_id->count_indexed.index);
659 }
660
661 rtas_event_log_queue(spapr, entry);
662
663 qemu_irq_pulse(spapr_qirq(spapr,
664 rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_HOTPLUG)));
665 }
666
667 void spapr_hotplug_req_add_by_index(SpaprDrc *drc)
668 {
669 SpaprDrcType drc_type = spapr_drc_type(drc);
670 union drc_identifier drc_id;
671
672 drc_id.index = spapr_drc_index(drc);
673 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_INDEX,
674 RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id);
675 }
676
677 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc)
678 {
679 SpaprDrcType drc_type = spapr_drc_type(drc);
680 union drc_identifier drc_id;
681
682 drc_id.index = spapr_drc_index(drc);
683 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_INDEX,
684 RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id);
685 }
686
687 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
688 uint32_t count)
689 {
690 union drc_identifier drc_id;
691
692 drc_id.count = count;
693 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT,
694 RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id);
695 }
696
697 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
698 uint32_t count)
699 {
700 union drc_identifier drc_id;
701
702 drc_id.count = count;
703 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT,
704 RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id);
705 }
706
707 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
708 uint32_t count, uint32_t index)
709 {
710 union drc_identifier drc_id;
711
712 drc_id.count_indexed.count = count;
713 drc_id.count_indexed.index = index;
714 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED,
715 RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id);
716 }
717
718 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
719 uint32_t count, uint32_t index)
720 {
721 union drc_identifier drc_id;
722
723 drc_id.count_indexed.count = count;
724 drc_id.count_indexed.index = index;
725 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED,
726 RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id);
727 }
728
729 static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered,
730 struct mc_extended_log *ext_elog)
731 {
732 int i;
733 CPUPPCState *env = &cpu->env;
734 uint32_t summary;
735 uint64_t dsisr = env->spr[SPR_DSISR];
736
737 summary = RTAS_LOG_VERSION_6 | RTAS_LOG_OPTIONAL_PART_PRESENT;
738 if (recovered) {
739 summary |= RTAS_LOG_DISPOSITION_FULLY_RECOVERED;
740 } else {
741 summary |= RTAS_LOG_DISPOSITION_NOT_RECOVERED;
742 }
743
744 if (SRR1_MC_LOADSTORE(env->spr[SPR_SRR1])) {
745 for (i = 0; i < ARRAY_SIZE(mc_derror_table); i++) {
746 if (!(dsisr & mc_derror_table[i].dsisr_value)) {
747 continue;
748 }
749
750 ext_elog->mc.error_type = mc_derror_table[i].error_type;
751 ext_elog->mc.sub_err_type = mc_derror_table[i].error_subtype;
752 if (mc_derror_table[i].dar_valid) {
753 ext_elog->mc.effective_address = cpu_to_be64(env->spr[SPR_DAR]);
754 }
755
756 summary |= mc_derror_table[i].initiator
757 | mc_derror_table[i].severity;
758
759 return summary;
760 }
761 } else {
762 for (i = 0; i < ARRAY_SIZE(mc_ierror_table); i++) {
763 if ((env->spr[SPR_SRR1] & mc_ierror_table[i].srr1_mask) !=
764 mc_ierror_table[i].srr1_value) {
765 continue;
766 }
767
768 ext_elog->mc.error_type = mc_ierror_table[i].error_type;
769 ext_elog->mc.sub_err_type = mc_ierror_table[i].error_subtype;
770 if (mc_ierror_table[i].nip_valid) {
771 ext_elog->mc.effective_address = cpu_to_be64(env->nip);
772 }
773
774 summary |= mc_ierror_table[i].initiator
775 | mc_ierror_table[i].severity;
776
777 return summary;
778 }
779 }
780
781 summary |= RTAS_LOG_INITIATOR_CPU;
782 return summary;
783 }
784
785 static void spapr_mce_dispatch_elog(PowerPCCPU *cpu, bool recovered)
786 {
787 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
788 CPUState *cs = CPU(cpu);
789 CPUPPCState *env = &cpu->env;
790 uint64_t rtas_addr;
791 struct rtas_error_log log;
792 struct mc_extended_log *ext_elog;
793 uint32_t summary;
794
795 ext_elog = g_malloc0(sizeof(*ext_elog));
796 summary = spapr_mce_get_elog_type(cpu, recovered, ext_elog);
797
798 log.summary = cpu_to_be32(summary);
799 log.extended_length = cpu_to_be32(sizeof(*ext_elog));
800
801 spapr_init_v6hdr(&ext_elog->v6hdr);
802 ext_elog->mc.hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MC);
803 ext_elog->mc.hdr.section_length =
804 cpu_to_be16(sizeof(struct rtas_event_log_v6_mc));
805 ext_elog->mc.hdr.section_version = 1;
806
807 /* get rtas addr from fdt */
808 rtas_addr = spapr_get_rtas_addr();
809 if (!rtas_addr) {
810 qemu_system_guest_panicked(NULL);
811 g_free(ext_elog);
812 return;
813 }
814
815 stq_be_phys(&address_space_memory, rtas_addr + RTAS_ERROR_LOG_OFFSET,
816 env->gpr[3]);
817 cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET +
818 sizeof(env->gpr[3]), &log, sizeof(log));
819 cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET +
820 sizeof(env->gpr[3]) + sizeof(log), ext_elog,
821 sizeof(*ext_elog));
822 g_free(ext_elog);
823
824 env->gpr[3] = rtas_addr + RTAS_ERROR_LOG_OFFSET;
825
826 ppc_cpu_do_fwnmi_machine_check(cs, spapr->fwnmi_machine_check_addr);
827 }
828
829 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered)
830 {
831 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
832 CPUState *cs = CPU(cpu);
833 int ret;
834 Error *local_err = NULL;
835
836 if (spapr->fwnmi_machine_check_addr == -1) {
837 /*
838 * This implies that we have hit a machine check either when the
839 * guest has not registered FWNMI (i.e., "ibm,nmi-register" not
840 * called) or between system reset and "ibm,nmi-register".
841 * Fall back to the old machine check behavior in such cases.
842 */
843 cs->exception_index = POWERPC_EXCP_MCHECK;
844 ppc_cpu_do_interrupt(cs);
845 return;
846 }
847
848 while (spapr->fwnmi_machine_check_interlock != -1) {
849 /*
850 * Check whether the same CPU got machine check error
851 * while still handling the mc error (i.e., before
852 * that CPU called "ibm,nmi-interlock")
853 */
854 if (spapr->fwnmi_machine_check_interlock == cpu->vcpu_id) {
855 qemu_system_guest_panicked(NULL);
856 return;
857 }
858 qemu_cond_wait_iothread(&spapr->fwnmi_machine_check_interlock_cond);
859 /* Meanwhile if the system is reset, then just return */
860 if (spapr->fwnmi_machine_check_addr == -1) {
861 return;
862 }
863 }
864
865 ret = migrate_add_blocker(spapr->fwnmi_migration_blocker, &local_err);
866 if (ret == -EBUSY) {
867 /*
868 * We don't want to abort so we let the migration to continue.
869 * In a rare case, the machine check handler will run on the target.
870 * Though this is not preferable, it is better than aborting
871 * the migration or killing the VM.
872 */
873 warn_report("Received a fwnmi while migration was in progress");
874 }
875
876 spapr->fwnmi_machine_check_interlock = cpu->vcpu_id;
877 spapr_mce_dispatch_elog(cpu, recovered);
878 }
879
880 static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr,
881 uint32_t token, uint32_t nargs,
882 target_ulong args,
883 uint32_t nret, target_ulong rets)
884 {
885 uint32_t mask, buf, len, event_len;
886 uint64_t xinfo;
887 SpaprEventLogEntry *event;
888 struct rtas_error_log header;
889 int i;
890
891 if ((nargs < 6) || (nargs > 7) || nret != 1) {
892 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
893 return;
894 }
895
896 xinfo = rtas_ld(args, 1);
897 mask = rtas_ld(args, 2);
898 buf = rtas_ld(args, 4);
899 len = rtas_ld(args, 5);
900 if (nargs == 7) {
901 xinfo |= (uint64_t)rtas_ld(args, 6) << 32;
902 }
903
904 event = rtas_event_log_dequeue(spapr, mask);
905 if (!event) {
906 goto out_no_events;
907 }
908
909 event_len = event->extended_length + sizeof(header);
910
911 if (event_len < len) {
912 len = event_len;
913 }
914
915 header.summary = cpu_to_be32(event->summary);
916 header.extended_length = cpu_to_be32(event->extended_length);
917 cpu_physical_memory_write(buf, &header, sizeof(header));
918 cpu_physical_memory_write(buf + sizeof(header), event->extended_log,
919 event->extended_length);
920 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
921 g_free(event->extended_log);
922 g_free(event);
923
924 /* according to PAPR+, the IRQ must be left asserted, or re-asserted, if
925 * there are still pending events to be fetched via check-exception. We
926 * do the latter here, since our code relies on edge-triggered
927 * interrupts.
928 */
929 for (i = 0; i < EVENT_CLASS_MAX; i++) {
930 if (rtas_event_log_contains(EVENT_CLASS_MASK(i))) {
931 const SpaprEventSource *source =
932 spapr_event_sources_get_source(spapr->event_sources, i);
933
934 g_assert(source->enabled);
935 qemu_irq_pulse(spapr_qirq(spapr, source->irq));
936 }
937 }
938
939 return;
940
941 out_no_events:
942 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
943 }
944
945 static void event_scan(PowerPCCPU *cpu, SpaprMachineState *spapr,
946 uint32_t token, uint32_t nargs,
947 target_ulong args,
948 uint32_t nret, target_ulong rets)
949 {
950 if (nargs != 4 || nret != 1) {
951 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
952 return;
953 }
954 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
955 }
956
957 void spapr_clear_pending_events(SpaprMachineState *spapr)
958 {
959 SpaprEventLogEntry *entry = NULL, *next_entry;
960
961 QTAILQ_FOREACH_SAFE(entry, &spapr->pending_events, next, next_entry) {
962 QTAILQ_REMOVE(&spapr->pending_events, entry, next);
963 g_free(entry->extended_log);
964 g_free(entry);
965 }
966 }
967
968 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr)
969 {
970 SpaprEventLogEntry *entry = NULL, *next_entry;
971
972 QTAILQ_FOREACH_SAFE(entry, &spapr->pending_events, next, next_entry) {
973 if (spapr_event_log_entry_type(entry) == RTAS_LOG_TYPE_HOTPLUG) {
974 QTAILQ_REMOVE(&spapr->pending_events, entry, next);
975 g_free(entry->extended_log);
976 g_free(entry);
977 }
978 }
979 }
980
981 void spapr_events_init(SpaprMachineState *spapr)
982 {
983 int epow_irq = SPAPR_IRQ_EPOW;
984
985 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
986 epow_irq = spapr_irq_findone(spapr, &error_fatal);
987 }
988
989 spapr_irq_claim(spapr, epow_irq, false, &error_fatal);
990
991 QTAILQ_INIT(&spapr->pending_events);
992
993 spapr->event_sources = spapr_event_sources_new();
994
995 spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_EPOW,
996 epow_irq);
997
998 /* NOTE: if machine supports modern/dedicated hotplug event source,
999 * we add it to the device-tree unconditionally. This means we may
1000 * have cases where the source is enabled in QEMU, but unused by the
1001 * guest because it does not support modern hotplug events, so we
1002 * take care to rely on checking for negotiation of OV5_HP_EVT option
1003 * before attempting to use it to signal events, rather than simply
1004 * checking that it's enabled.
1005 */
1006 if (spapr->use_hotplug_event_source) {
1007 int hp_irq = SPAPR_IRQ_HOTPLUG;
1008
1009 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
1010 hp_irq = spapr_irq_findone(spapr, &error_fatal);
1011 }
1012
1013 spapr_irq_claim(spapr, hp_irq, false, &error_fatal);
1014
1015 spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_HOT_PLUG,
1016 hp_irq);
1017 }
1018
1019 spapr->epow_notifier.notify = spapr_powerdown_req;
1020 qemu_register_powerdown_notifier(&spapr->epow_notifier);
1021 spapr_rtas_register(RTAS_CHECK_EXCEPTION, "check-exception",
1022 check_exception);
1023 spapr_rtas_register(RTAS_EVENT_SCAN, "event-scan", event_scan);
1024 }
Mirror of https://git.qemu.org/git/qemu.git