2 * QEMU Sun4u System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #define KERNEL_LOAD_ADDR 0x00404000
28 #define CMDLINE_ADDR 0x003ff000
29 #define INITRD_LOAD_ADDR 0x00300000
30 #define PROM_SIZE_MAX (512 * 1024)
31 #define PROM_ADDR 0x1fff0000000ULL
32 #define PROM_VADDR 0x000ffd00000ULL
33 #define APB_SPECIAL_BASE 0x1fe00000000ULL
34 #define APB_MEM_BASE 0x1ff00000000ULL
35 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
36 #define PROM_FILENAME "openbios-sparc64"
37 #define NVRAM_SIZE 0x2000
41 uint64_t cpu_get_tsc()
43 return qemu_get_clock(vm_clock
);
46 int DMA_get_channel_mode (int nchan
)
50 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
54 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
58 void DMA_hold_DREQ (int nchan
) {}
59 void DMA_release_DREQ (int nchan
) {}
60 void DMA_schedule(int nchan
) {}
61 void DMA_run (void) {}
62 void DMA_init (int high_page_enable
) {}
63 void DMA_register_channel (int nchan
,
64 DMA_transfer_handler transfer_handler
,
70 void NVRAM_set_byte (m48t59_t
*nvram
, uint32_t addr
, uint8_t value
)
72 m48t59_write(nvram
, addr
, value
);
75 uint8_t NVRAM_get_byte (m48t59_t
*nvram
, uint32_t addr
)
77 return m48t59_read(nvram
, addr
);
80 void NVRAM_set_word (m48t59_t
*nvram
, uint32_t addr
, uint16_t value
)
82 m48t59_write(nvram
, addr
, value
>> 8);
83 m48t59_write(nvram
, addr
+ 1, value
& 0xFF);
86 uint16_t NVRAM_get_word (m48t59_t
*nvram
, uint32_t addr
)
90 tmp
= m48t59_read(nvram
, addr
) << 8;
91 tmp
|= m48t59_read(nvram
, addr
+ 1);
96 void NVRAM_set_lword (m48t59_t
*nvram
, uint32_t addr
, uint32_t value
)
98 m48t59_write(nvram
, addr
, value
>> 24);
99 m48t59_write(nvram
, addr
+ 1, (value
>> 16) & 0xFF);
100 m48t59_write(nvram
, addr
+ 2, (value
>> 8) & 0xFF);
101 m48t59_write(nvram
, addr
+ 3, value
& 0xFF);
104 uint32_t NVRAM_get_lword (m48t59_t
*nvram
, uint32_t addr
)
108 tmp
= m48t59_read(nvram
, addr
) << 24;
109 tmp
|= m48t59_read(nvram
, addr
+ 1) << 16;
110 tmp
|= m48t59_read(nvram
, addr
+ 2) << 8;
111 tmp
|= m48t59_read(nvram
, addr
+ 3);
116 void NVRAM_set_string (m48t59_t
*nvram
, uint32_t addr
,
117 const unsigned char *str
, uint32_t max
)
121 for (i
= 0; i
< max
&& str
[i
] != '\0'; i
++) {
122 m48t59_write(nvram
, addr
+ i
, str
[i
]);
124 m48t59_write(nvram
, addr
+ max
- 1, '\0');
127 int NVRAM_get_string (m48t59_t
*nvram
, uint8_t *dst
, uint16_t addr
, int max
)
132 for (i
= 0; i
< max
; i
++) {
133 dst
[i
] = NVRAM_get_byte(nvram
, addr
+ i
);
141 static uint16_t NVRAM_crc_update (uint16_t prev
, uint16_t value
)
144 uint16_t pd
, pd1
, pd2
;
149 pd2
= ((pd
>> 4) & 0x000F) ^ pd1
;
150 tmp
^= (pd1
<< 3) | (pd1
<< 8);
151 tmp
^= pd2
| (pd2
<< 7) | (pd2
<< 12);
156 uint16_t NVRAM_compute_crc (m48t59_t
*nvram
, uint32_t start
, uint32_t count
)
159 uint16_t crc
= 0xFFFF;
164 for (i
= 0; i
!= count
; i
++) {
165 crc
= NVRAM_crc_update(crc
, NVRAM_get_word(nvram
, start
+ i
));
168 crc
= NVRAM_crc_update(crc
, NVRAM_get_byte(nvram
, start
+ i
) << 8);
174 static uint32_t nvram_set_var (m48t59_t
*nvram
, uint32_t addr
,
175 const unsigned char *str
)
179 len
= strlen(str
) + 1;
180 NVRAM_set_string(nvram
, addr
, str
, len
);
185 static void nvram_finish_partition (m48t59_t
*nvram
, uint32_t start
,
190 // Length divided by 16
191 m48t59_write(nvram
, start
+ 2, ((end
- start
) >> 12) & 0xff);
192 m48t59_write(nvram
, start
+ 3, ((end
- start
) >> 4) & 0xff);
194 sum
= m48t59_read(nvram
, start
);
195 for (i
= 0; i
< 14; i
++) {
196 sum
+= m48t59_read(nvram
, start
+ 2 + i
);
197 sum
= (sum
+ ((sum
& 0xff00) >> 8)) & 0xff;
199 m48t59_write(nvram
, start
+ 1, sum
& 0xff);
202 extern int nographic
;
204 int sun4u_NVRAM_set_params (m48t59_t
*nvram
, uint16_t NVRAM_size
,
205 const unsigned char *arch
,
206 uint32_t RAM_size
, int boot_device
,
207 uint32_t kernel_image
, uint32_t kernel_size
,
209 uint32_t initrd_image
, uint32_t initrd_size
,
210 uint32_t NVRAM_image
,
211 int width
, int height
, int depth
)
217 /* Set parameters for Open Hack'Ware BIOS */
218 NVRAM_set_string(nvram
, 0x00, "QEMU_BIOS", 16);
219 NVRAM_set_lword(nvram
, 0x10, 0x00000002); /* structure v2 */
220 NVRAM_set_word(nvram
, 0x14, NVRAM_size
);
221 NVRAM_set_string(nvram
, 0x20, arch
, 16);
222 NVRAM_set_byte(nvram
, 0x2f, nographic
& 0xff);
223 NVRAM_set_lword(nvram
, 0x30, RAM_size
);
224 NVRAM_set_byte(nvram
, 0x34, boot_device
);
225 NVRAM_set_lword(nvram
, 0x38, kernel_image
);
226 NVRAM_set_lword(nvram
, 0x3C, kernel_size
);
228 /* XXX: put the cmdline in NVRAM too ? */
229 strcpy(phys_ram_base
+ CMDLINE_ADDR
, cmdline
);
230 NVRAM_set_lword(nvram
, 0x40, CMDLINE_ADDR
);
231 NVRAM_set_lword(nvram
, 0x44, strlen(cmdline
));
233 NVRAM_set_lword(nvram
, 0x40, 0);
234 NVRAM_set_lword(nvram
, 0x44, 0);
236 NVRAM_set_lword(nvram
, 0x48, initrd_image
);
237 NVRAM_set_lword(nvram
, 0x4C, initrd_size
);
238 NVRAM_set_lword(nvram
, 0x50, NVRAM_image
);
240 NVRAM_set_word(nvram
, 0x54, width
);
241 NVRAM_set_word(nvram
, 0x56, height
);
242 NVRAM_set_word(nvram
, 0x58, depth
);
243 crc
= NVRAM_compute_crc(nvram
, 0x00, 0xF8);
244 NVRAM_set_word(nvram
, 0xFC, crc
);
246 // OpenBIOS nvram variables
247 // Variable partition
249 m48t59_write(nvram
, start
, 0x70);
250 NVRAM_set_string(nvram
, start
+ 4, "system", 12);
253 for (i
= 0; i
< nb_prom_envs
; i
++)
254 end
= nvram_set_var(nvram
, end
, prom_envs
[i
]);
256 m48t59_write(nvram
, end
++ , 0);
257 end
= start
+ ((end
- start
+ 15) & ~15);
258 nvram_finish_partition(nvram
, start
, end
);
262 m48t59_write(nvram
, start
, 0x7f);
263 NVRAM_set_string(nvram
, start
+ 4, "free", 12);
266 nvram_finish_partition(nvram
, start
, end
);
279 void qemu_system_powerdown(void)
283 static void main_cpu_reset(void *opaque
)
285 CPUState
*env
= opaque
;
288 ptimer_set_limit(env
->tick
, 0x7fffffffffffffffULL
, 1);
289 ptimer_run(env
->tick
, 0);
290 ptimer_set_limit(env
->stick
, 0x7fffffffffffffffULL
, 1);
291 ptimer_run(env
->stick
, 0);
292 ptimer_set_limit(env
->hstick
, 0x7fffffffffffffffULL
, 1);
293 ptimer_run(env
->hstick
, 0);
296 void tick_irq(void *opaque
)
298 CPUState
*env
= opaque
;
300 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
303 void stick_irq(void *opaque
)
305 CPUState
*env
= opaque
;
307 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
310 void hstick_irq(void *opaque
)
312 CPUState
*env
= opaque
;
314 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
317 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
321 static const int ide_iobase
[2] = { 0x1f0, 0x170 };
322 static const int ide_iobase2
[2] = { 0x3f6, 0x376 };
323 static const int ide_irq
[2] = { 14, 15 };
325 static const int serial_io
[MAX_SERIAL_PORTS
] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
326 static const int serial_irq
[MAX_SERIAL_PORTS
] = { 4, 3, 4, 3 };
328 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
329 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
331 static fdctrl_t
*floppy_controller
;
333 /* Sun4u hardware initialisation */
334 static void sun4u_init(int ram_size
, int vga_ram_size
, int boot_device
,
335 DisplayState
*ds
, const char **fd_filename
, int snapshot
,
336 const char *kernel_filename
, const char *kernel_cmdline
,
337 const char *initrd_filename
, const char *cpu_model
)
344 long prom_offset
, initrd_size
, kernel_size
;
346 const sparc_def_t
*def
;
350 linux_boot
= (kernel_filename
!= NULL
);
353 if (cpu_model
== NULL
)
354 cpu_model
= "TI UltraSparc II";
355 sparc_find_by_name(cpu_model
, &def
);
357 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
361 cpu_sparc_register(env
, def
);
362 bh
= qemu_bh_new(tick_irq
, env
);
363 env
->tick
= ptimer_init(bh
);
364 ptimer_set_period(env
->tick
, 1ULL);
366 bh
= qemu_bh_new(stick_irq
, env
);
367 env
->stick
= ptimer_init(bh
);
368 ptimer_set_period(env
->stick
, 1ULL);
370 bh
= qemu_bh_new(hstick_irq
, env
);
371 env
->hstick
= ptimer_init(bh
);
372 ptimer_set_period(env
->hstick
, 1ULL);
373 register_savevm("cpu", 0, 3, cpu_save
, cpu_load
, env
);
374 qemu_register_reset(main_cpu_reset
, env
);
378 cpu_register_physical_memory(0, ram_size
, 0);
380 prom_offset
= ram_size
+ vga_ram_size
;
381 cpu_register_physical_memory(PROM_ADDR
,
382 (PROM_SIZE_MAX
+ TARGET_PAGE_SIZE
) & TARGET_PAGE_MASK
,
383 prom_offset
| IO_MEM_ROM
);
385 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, PROM_FILENAME
);
386 ret
= load_elf(buf
, PROM_ADDR
- PROM_VADDR
, NULL
, NULL
, NULL
);
388 fprintf(stderr
, "qemu: could not load prom '%s'\n",
396 /* XXX: put correct offset */
397 kernel_size
= load_elf(kernel_filename
, 0, NULL
, NULL
, NULL
);
399 kernel_size
= load_aout(kernel_filename
, phys_ram_base
+ KERNEL_LOAD_ADDR
);
401 kernel_size
= load_image(kernel_filename
, phys_ram_base
+ KERNEL_LOAD_ADDR
);
402 if (kernel_size
< 0) {
403 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
409 if (initrd_filename
) {
410 initrd_size
= load_image(initrd_filename
, phys_ram_base
+ INITRD_LOAD_ADDR
);
411 if (initrd_size
< 0) {
412 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
417 if (initrd_size
> 0) {
418 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
419 if (ldl_raw(phys_ram_base
+ KERNEL_LOAD_ADDR
+ i
)
420 == 0x48647253) { // HdrS
421 stl_raw(phys_ram_base
+ KERNEL_LOAD_ADDR
+ i
+ 16, INITRD_LOAD_ADDR
);
422 stl_raw(phys_ram_base
+ KERNEL_LOAD_ADDR
+ i
+ 20, initrd_size
);
428 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, NULL
);
429 isa_mem_base
= VGA_BASE
;
430 pci_cirrus_vga_init(pci_bus
, ds
, phys_ram_base
+ ram_size
, ram_size
, vga_ram_size
);
432 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
434 serial_init(serial_io
[i
], NULL
/*serial_irq[i]*/, serial_hds
[i
]);
438 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
439 if (parallel_hds
[i
]) {
440 parallel_init(parallel_io
[i
], NULL
/*parallel_irq[i]*/, parallel_hds
[i
]);
444 for(i
= 0; i
< nb_nics
; i
++) {
445 if (!nd_table
[i
].model
)
446 nd_table
[i
].model
= "ne2k_pci";
447 pci_nic_init(pci_bus
, &nd_table
[i
], -1);
450 irq
= qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, 32);
451 // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
452 pci_piix3_ide_init(pci_bus
, bs_table
, -1, irq
);
453 /* FIXME: wire up interrupts. */
454 i8042_init(NULL
/*1*/, NULL
/*12*/, 0x60);
455 floppy_controller
= fdctrl_init(NULL
/*6*/, 2, 0, 0x3f0, fd_table
);
456 nvram
= m48t59_init(NULL
/*8*/, 0, 0x0074, NVRAM_SIZE
, 59);
457 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", ram_size
, boot_device
,
458 KERNEL_LOAD_ADDR
, kernel_size
,
460 INITRD_LOAD_ADDR
, initrd_size
,
461 /* XXX: need an option to load a NVRAM image */
463 graphic_width
, graphic_height
, graphic_depth
);
467 QEMUMachine sun4u_machine
= {