hw/timer/pl031.c

   1 /*
   2  * ARM AMBA PrimeCell PL031 RTC
   3  *
   4  * Copyright (c) 2007 CodeSourcery
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Contributions after 2012-01-13 are licensed under the terms of the
  11  * GNU GPL, version 2 or (at your option) any later version.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/sysbus.h"
  16 #include "qemu/timer.h"
  17 #include "sysemu/sysemu.h"
  18 #include "qemu/cutils.h"
  19
  20 //#define DEBUG_PL031
  21
  22 #ifdef DEBUG_PL031
  23 #define DPRINTF(fmt, ...) \
  24 do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
  25 #else
  26 #define DPRINTF(fmt, ...) do {} while(0)
  27 #endif
  28
  29 #define RTC_DR      0x00    /* Data read register */
  30 #define RTC_MR      0x04    /* Match register */
  31 #define RTC_LR      0x08    /* Data load register */
  32 #define RTC_CR      0x0c    /* Control register */
  33 #define RTC_IMSC    0x10    /* Interrupt mask and set register */
  34 #define RTC_RIS     0x14    /* Raw interrupt status register */
  35 #define RTC_MIS     0x18    /* Masked interrupt status register */
  36 #define RTC_ICR     0x1c    /* Interrupt clear register */
  37
  38 #define TYPE_PL031 "pl031"
  39 #define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
  40
  41 typedef struct PL031State {
  42     SysBusDevice parent_obj;
  43
  44     MemoryRegion iomem;
  45     QEMUTimer *timer;
  46     qemu_irq irq;
  47
  48     /* Needed to preserve the tick_count across migration, even if the
  49      * absolute value of the rtc_clock is different on the source and
  50      * destination.
  51      */
  52     uint32_t tick_offset_vmstate;
  53     uint32_t tick_offset;
  54
  55     uint32_t mr;
  56     uint32_t lr;
  57     uint32_t cr;
  58     uint32_t im;
  59     uint32_t is;
  60 } PL031State;
  61
  62 static const unsigned char pl031_id[] = {
  63     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
  64     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
  65 };
  66
  67 static void pl031_update(PL031State *s)
  68 {
  69     qemu_set_irq(s->irq, s->is & s->im);
  70 }
  71
  72 static void pl031_interrupt(void * opaque)
  73 {
  74     PL031State *s = (PL031State *)opaque;
  75
  76     s->is = 1;
  77     DPRINTF("Alarm raised\n");
  78     pl031_update(s);
  79 }
  80
  81 static uint32_t pl031_get_count(PL031State *s)
  82 {
  83     int64_t now = qemu_clock_get_ns(rtc_clock);
  84     return s->tick_offset + now / NANOSECONDS_PER_SECOND;
  85 }
  86
  87 static void pl031_set_alarm(PL031State *s)
  88 {
  89     uint32_t ticks;
  90
  91     /* The timer wraps around.  This subtraction also wraps in the same way,
  92        and gives correct results when alarm < now_ticks.  */
  93     ticks = s->mr - pl031_get_count(s);
  94     DPRINTF("Alarm set in %ud ticks\n", ticks);
  95     if (ticks == 0) {
  96         timer_del(s->timer);
  97         pl031_interrupt(s);
  98     } else {
  99         int64_t now = qemu_clock_get_ns(rtc_clock);
 100         timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
 101     }
 102 }
 103
 104 static uint64_t pl031_read(void *opaque, hwaddr offset,
 105                            unsigned size)
 106 {
 107     PL031State *s = (PL031State *)opaque;
 108
 109     if (offset >= 0xfe0  &&  offset < 0x1000)
 110         return pl031_id[(offset - 0xfe0) >> 2];
 111
 112     switch (offset) {
 113     case RTC_DR:
 114         return pl031_get_count(s);
 115     case RTC_MR:
 116         return s->mr;
 117     case RTC_IMSC:
 118         return s->im;
 119     case RTC_RIS:
 120         return s->is;
 121     case RTC_LR:
 122         return s->lr;
 123     case RTC_CR:
 124         /* RTC is permanently enabled.  */
 125         return 1;
 126     case RTC_MIS:
 127         return s->is & s->im;
 128     case RTC_ICR:
 129         qemu_log_mask(LOG_GUEST_ERROR,
 130                       "pl031: read of write-only register at offset 0x%x\n",
 131                       (int)offset);
 132         break;
 133     default:
 134         qemu_log_mask(LOG_GUEST_ERROR,
 135                       "pl031_read: Bad offset 0x%x\n", (int)offset);
 136         break;
 137     }
 138
 139     return 0;
 140 }
 141
 142 static void pl031_write(void * opaque, hwaddr offset,
 143                         uint64_t value, unsigned size)
 144 {
 145     PL031State *s = (PL031State *)opaque;
 146
 147
 148     switch (offset) {
 149     case RTC_LR:
 150         s->tick_offset += value - pl031_get_count(s);
 151         pl031_set_alarm(s);
 152         break;
 153     case RTC_MR:
 154         s->mr = value;
 155         pl031_set_alarm(s);
 156         break;
 157     case RTC_IMSC:
 158         s->im = value & 1;
 159         DPRINTF("Interrupt mask %d\n", s->im);
 160         pl031_update(s);
 161         break;
 162     case RTC_ICR:
 163         /* The PL031 documentation (DDI0224B) states that the interrupt is
 164            cleared when bit 0 of the written value is set.  However the
 165            arm926e documentation (DDI0287B) states that the interrupt is
 166            cleared when any value is written.  */
 167         DPRINTF("Interrupt cleared");
 168         s->is = 0;
 169         pl031_update(s);
 170         break;
 171     case RTC_CR:
 172         /* Written value is ignored.  */
 173         break;
 174
 175     case RTC_DR:
 176     case RTC_MIS:
 177     case RTC_RIS:
 178         qemu_log_mask(LOG_GUEST_ERROR,
 179                       "pl031: write to read-only register at offset 0x%x\n",
 180                       (int)offset);
 181         break;
 182
 183     default:
 184         qemu_log_mask(LOG_GUEST_ERROR,
 185                       "pl031_write: Bad offset 0x%x\n", (int)offset);
 186         break;
 187     }
 188 }
 189
 190 static const MemoryRegionOps pl031_ops = {
 191     .read = pl031_read,
 192     .write = pl031_write,
 193     .endianness = DEVICE_NATIVE_ENDIAN,
 194 };
 195
 196 static void pl031_init(Object *obj)
 197 {
 198     PL031State *s = PL031(obj);
 199     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 200     struct tm tm;
 201
 202     memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
 203     sysbus_init_mmio(dev, &s->iomem);
 204
 205     sysbus_init_irq(dev, &s->irq);
 206     qemu_get_timedate(&tm, 0);
 207     s->tick_offset = mktimegm(&tm) -
 208         qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 209
 210     s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
 211 }
 212
 213 static void pl031_pre_save(void *opaque)
 214 {
 215     PL031State *s = opaque;
 216
 217     /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
 218      * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility.  */
 219     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 220     s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
 221 }
 222
 223 static int pl031_post_load(void *opaque, int version_id)
 224 {
 225     PL031State *s = opaque;
 226
 227     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 228     s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
 229     pl031_set_alarm(s);
 230     return 0;
 231 }
 232
 233 static const VMStateDescription vmstate_pl031 = {
 234     .name = "pl031",
 235     .version_id = 1,
 236     .minimum_version_id = 1,
 237     .pre_save = pl031_pre_save,
 238     .post_load = pl031_post_load,
 239     .fields = (VMStateField[]) {
 240         VMSTATE_UINT32(tick_offset_vmstate, PL031State),
 241         VMSTATE_UINT32(mr, PL031State),
 242         VMSTATE_UINT32(lr, PL031State),
 243         VMSTATE_UINT32(cr, PL031State),
 244         VMSTATE_UINT32(im, PL031State),
 245         VMSTATE_UINT32(is, PL031State),
 246         VMSTATE_END_OF_LIST()
 247     }
 248 };
 249
 250 static void pl031_class_init(ObjectClass *klass, void *data)
 251 {
 252     DeviceClass *dc = DEVICE_CLASS(klass);
 253
 254     dc->vmsd = &vmstate_pl031;
 255 }
 256
 257 static const TypeInfo pl031_info = {
 258     .name          = TYPE_PL031,
 259     .parent        = TYPE_SYS_BUS_DEVICE,
 260     .instance_size = sizeof(PL031State),
 261     .instance_init = pl031_init,
 262     .class_init    = pl031_class_init,
 263 };
 264
 265 static void pl031_register_types(void)
 266 {
 267     type_register_static(&pl031_info);
 268 }
 269
 270 type_init(pl031_register_types)