2 * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
4 * Copyright (c) 2017 Xilinx Inc.
6 * Written-by: Alistair Francis <alistair.francis@xilinx.com>
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "hw/sysbus.h"
29 #include "hw/register.h"
30 #include "qemu/bitops.h"
32 #include "qemu/module.h"
33 #include "hw/ptimer.h"
34 #include "qemu/cutils.h"
35 #include "sysemu/sysemu.h"
37 #include "hw/timer/xlnx-zynqmp-rtc.h"
39 #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
40 #define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
43 static void rtc_int_update_irq(XlnxZynqMPRTC
*s
)
45 bool pending
= s
->regs
[R_RTC_INT_STATUS
] & ~s
->regs
[R_RTC_INT_MASK
];
46 qemu_set_irq(s
->irq_rtc_int
, pending
);
49 static void addr_error_int_update_irq(XlnxZynqMPRTC
*s
)
51 bool pending
= s
->regs
[R_ADDR_ERROR
] & ~s
->regs
[R_ADDR_ERROR_INT_MASK
];
52 qemu_set_irq(s
->irq_addr_error_int
, pending
);
55 static uint32_t rtc_get_count(XlnxZynqMPRTC
*s
)
57 int64_t now
= qemu_clock_get_ns(rtc_clock
);
58 return s
->tick_offset
+ now
/ NANOSECONDS_PER_SECOND
;
61 static uint64_t current_time_postr(RegisterInfo
*reg
, uint64_t val64
)
63 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(reg
->opaque
);
65 return rtc_get_count(s
);
68 static void rtc_int_status_postw(RegisterInfo
*reg
, uint64_t val64
)
70 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(reg
->opaque
);
71 rtc_int_update_irq(s
);
74 static uint64_t rtc_int_en_prew(RegisterInfo
*reg
, uint64_t val64
)
76 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(reg
->opaque
);
78 s
->regs
[R_RTC_INT_MASK
] &= (uint32_t) ~val64
;
79 rtc_int_update_irq(s
);
83 static uint64_t rtc_int_dis_prew(RegisterInfo
*reg
, uint64_t val64
)
85 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(reg
->opaque
);
87 s
->regs
[R_RTC_INT_MASK
] |= (uint32_t) val64
;
88 rtc_int_update_irq(s
);
92 static void addr_error_postw(RegisterInfo
*reg
, uint64_t val64
)
94 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(reg
->opaque
);
95 addr_error_int_update_irq(s
);
98 static uint64_t addr_error_int_en_prew(RegisterInfo
*reg
, uint64_t val64
)
100 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(reg
->opaque
);
102 s
->regs
[R_ADDR_ERROR_INT_MASK
] &= (uint32_t) ~val64
;
103 addr_error_int_update_irq(s
);
107 static uint64_t addr_error_int_dis_prew(RegisterInfo
*reg
, uint64_t val64
)
109 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(reg
->opaque
);
111 s
->regs
[R_ADDR_ERROR_INT_MASK
] |= (uint32_t) val64
;
112 addr_error_int_update_irq(s
);
116 static const RegisterAccessInfo rtc_regs_info
[] = {
117 { .name
= "SET_TIME_WRITE", .addr
= A_SET_TIME_WRITE
,
118 .unimp
= MAKE_64BIT_MASK(0, 32),
119 },{ .name
= "SET_TIME_READ", .addr
= A_SET_TIME_READ
,
121 .post_read
= current_time_postr
,
122 },{ .name
= "CALIB_WRITE", .addr
= A_CALIB_WRITE
,
123 .unimp
= MAKE_64BIT_MASK(0, 32),
124 },{ .name
= "CALIB_READ", .addr
= A_CALIB_READ
,
126 },{ .name
= "CURRENT_TIME", .addr
= A_CURRENT_TIME
,
128 .post_read
= current_time_postr
,
129 },{ .name
= "CURRENT_TICK", .addr
= A_CURRENT_TICK
,
131 },{ .name
= "ALARM", .addr
= A_ALARM
,
132 },{ .name
= "RTC_INT_STATUS", .addr
= A_RTC_INT_STATUS
,
134 .post_write
= rtc_int_status_postw
,
135 },{ .name
= "RTC_INT_MASK", .addr
= A_RTC_INT_MASK
,
138 },{ .name
= "RTC_INT_EN", .addr
= A_RTC_INT_EN
,
139 .pre_write
= rtc_int_en_prew
,
140 },{ .name
= "RTC_INT_DIS", .addr
= A_RTC_INT_DIS
,
141 .pre_write
= rtc_int_dis_prew
,
142 },{ .name
= "ADDR_ERROR", .addr
= A_ADDR_ERROR
,
144 .post_write
= addr_error_postw
,
145 },{ .name
= "ADDR_ERROR_INT_MASK", .addr
= A_ADDR_ERROR_INT_MASK
,
148 },{ .name
= "ADDR_ERROR_INT_EN", .addr
= A_ADDR_ERROR_INT_EN
,
149 .pre_write
= addr_error_int_en_prew
,
150 },{ .name
= "ADDR_ERROR_INT_DIS", .addr
= A_ADDR_ERROR_INT_DIS
,
151 .pre_write
= addr_error_int_dis_prew
,
152 },{ .name
= "CONTROL", .addr
= A_CONTROL
,
155 },{ .name
= "SAFETY_CHK", .addr
= A_SAFETY_CHK
,
159 static void rtc_reset(DeviceState
*dev
)
161 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(dev
);
164 for (i
= 0; i
< ARRAY_SIZE(s
->regs_info
); ++i
) {
165 register_reset(&s
->regs_info
[i
]);
168 rtc_int_update_irq(s
);
169 addr_error_int_update_irq(s
);
172 static const MemoryRegionOps rtc_ops
= {
173 .read
= register_read_memory
,
174 .write
= register_write_memory
,
175 .endianness
= DEVICE_LITTLE_ENDIAN
,
177 .min_access_size
= 4,
178 .max_access_size
= 4,
182 static void rtc_init(Object
*obj
)
184 XlnxZynqMPRTC
*s
= XLNX_ZYNQMP_RTC(obj
);
185 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
186 RegisterInfoArray
*reg_array
;
187 struct tm current_tm
;
189 memory_region_init(&s
->iomem
, obj
, TYPE_XLNX_ZYNQMP_RTC
,
190 XLNX_ZYNQMP_RTC_R_MAX
* 4);
192 register_init_block32(DEVICE(obj
), rtc_regs_info
,
193 ARRAY_SIZE(rtc_regs_info
),
194 s
->regs_info
, s
->regs
,
196 XLNX_ZYNQMP_RTC_ERR_DEBUG
,
197 XLNX_ZYNQMP_RTC_R_MAX
* 4);
198 memory_region_add_subregion(&s
->iomem
,
201 sysbus_init_mmio(sbd
, &s
->iomem
);
202 sysbus_init_irq(sbd
, &s
->irq_rtc_int
);
203 sysbus_init_irq(sbd
, &s
->irq_addr_error_int
);
205 qemu_get_timedate(¤t_tm
, 0);
206 s
->tick_offset
= mktimegm(¤t_tm
) -
207 qemu_clock_get_ns(rtc_clock
) / NANOSECONDS_PER_SECOND
;
209 trace_xlnx_zynqmp_rtc_gettime(current_tm
.tm_year
, current_tm
.tm_mon
,
210 current_tm
.tm_mday
, current_tm
.tm_hour
,
211 current_tm
.tm_min
, current_tm
.tm_sec
);
214 static int rtc_pre_save(void *opaque
)
216 XlnxZynqMPRTC
*s
= opaque
;
217 int64_t now
= qemu_clock_get_ns(rtc_clock
) / NANOSECONDS_PER_SECOND
;
219 /* Add the time at migration */
220 s
->tick_offset
= s
->tick_offset
+ now
;
225 static int rtc_post_load(void *opaque
, int version_id
)
227 XlnxZynqMPRTC
*s
= opaque
;
228 int64_t now
= qemu_clock_get_ns(rtc_clock
) / NANOSECONDS_PER_SECOND
;
230 /* Subtract the time after migration. This combined with the pre_save
231 * action results in us having subtracted the time that the guest was
232 * stopped to the offset.
234 s
->tick_offset
= s
->tick_offset
- now
;
239 static const VMStateDescription vmstate_rtc
= {
240 .name
= TYPE_XLNX_ZYNQMP_RTC
,
242 .minimum_version_id
= 1,
243 .pre_save
= rtc_pre_save
,
244 .post_load
= rtc_post_load
,
245 .fields
= (VMStateField
[]) {
246 VMSTATE_UINT32_ARRAY(regs
, XlnxZynqMPRTC
, XLNX_ZYNQMP_RTC_R_MAX
),
247 VMSTATE_UINT32(tick_offset
, XlnxZynqMPRTC
),
248 VMSTATE_END_OF_LIST(),
252 static void rtc_class_init(ObjectClass
*klass
, void *data
)
254 DeviceClass
*dc
= DEVICE_CLASS(klass
);
256 dc
->reset
= rtc_reset
;
257 dc
->vmsd
= &vmstate_rtc
;
260 static const TypeInfo rtc_info
= {
261 .name
= TYPE_XLNX_ZYNQMP_RTC
,
262 .parent
= TYPE_SYS_BUS_DEVICE
,
263 .instance_size
= sizeof(XlnxZynqMPRTC
),
264 .class_init
= rtc_class_init
,
265 .instance_init
= rtc_init
,
268 static void rtc_register_types(void)
270 type_register_static(&rtc_info
);
273 type_init(rtc_register_types
)