]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/altera.h
tools: image: fix "algo" property of public key for verified boot
[people/ms/u-boot.git] / include / altera.h
1 /*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <fpga.h>
9
10 #ifndef _ALTERA_H_
11 #define _ALTERA_H_
12
13 /*
14 * For the StratixV FPGA programming via SPI, the following
15 * information is coded in the 32bit cookie:
16 * Bit 31 ... Bit 0
17 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
18 */
19 #define FPGA_COOKIE(bus, dev, config, done) \
20 (((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done))
21 #define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff)
22 #define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff)
23 #define COOKIE2CONFIG(c) (((c) >> 8) & 0xff)
24 #define COOKIE2DONE(c) ((c) & 0xff)
25
26 enum altera_iface {
27 /* insert all new types after this */
28 min_altera_iface_type,
29 /* serial data and external clock */
30 passive_serial,
31 /* parallel data */
32 passive_parallel_synchronous,
33 /* parallel data */
34 passive_parallel_asynchronous,
35 /* serial data w/ internal clock (not used) */
36 passive_serial_asynchronous,
37 /* jtag/tap serial (not used ) */
38 altera_jtag_mode,
39 /* fast passive parallel (FPP) */
40 fast_passive_parallel,
41 /* fast passive parallel with security (FPPS) */
42 fast_passive_parallel_security,
43 /* insert all new types before this */
44 max_altera_iface_type,
45 };
46
47 enum altera_family {
48 /* insert all new types after this */
49 min_altera_type,
50 /* ACEX1K Family */
51 Altera_ACEX1K,
52 /* CYCLONII Family */
53 Altera_CYC2,
54 /* StratixII Family */
55 Altera_StratixII,
56 /* StratixV Family */
57 Altera_StratixV,
58 /* SoCFPGA Family */
59 Altera_SoCFPGA,
60
61 /* Add new models here */
62
63 /* insert all new types before this */
64 max_altera_type,
65 };
66
67 typedef struct {
68 /* part type */
69 enum altera_family family;
70 /* interface type */
71 enum altera_iface iface;
72 /* bytes of data part can accept */
73 size_t size;
74 /* interface function table */
75 void *iface_fns;
76 /* base interface address */
77 void *base;
78 /* implementation specific cookie */
79 int cookie;
80 } Altera_desc;
81
82 /* Generic Altera Functions
83 *********************************************************************/
84 extern int altera_load(Altera_desc *desc, const void *image, size_t size);
85 extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
86 extern int altera_info(Altera_desc *desc);
87
88 /* Board specific implementation specific function types
89 *********************************************************************/
90 typedef int (*Altera_pre_fn)( int cookie );
91 typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
92 typedef int (*Altera_status_fn)( int cookie );
93 typedef int (*Altera_done_fn)( int cookie );
94 typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
95 typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
96 typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
97 typedef int (*Altera_abort_fn)( int cookie );
98 typedef int (*Altera_post_fn)( int cookie );
99
100 typedef struct {
101 Altera_pre_fn pre;
102 Altera_config_fn config;
103 Altera_status_fn status;
104 Altera_done_fn done;
105 Altera_clk_fn clk;
106 Altera_data_fn data;
107 Altera_write_fn write;
108 Altera_abort_fn abort;
109 Altera_post_fn post;
110 } altera_board_specific_func;
111
112 #ifdef CONFIG_FPGA_SOCFPGA
113 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
114 #endif
115
116 #ifdef CONFIG_FPGA_STRATIX_V
117 int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
118 #endif
119
120 #endif /* _ALTERA_H_ */