include/asm-arm/arch-at91rm9200/AT91RM9200.h

   1 /*
   2  * (C) Copyright 2003
   3  * AT91RM9200 definitions
   4  * Author : ATMEL AT91 application group
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef AT91RM9200_H
  26 #define AT91RM9200_H
  27
  28 typedef volatile unsigned int AT91_REG;/* Hardware register definition */
  29
  30 /* ***************************************************************************** */
  31 /*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
  32 /* ***************************************************************************** */
  33 typedef struct _AT91S_TC {
  34         AT91_REG         TC_CCR;        /* Channel Control Register */
  35         AT91_REG         TC_CMR;        /* Channel Mode Register */
  36         AT91_REG         Reserved0[2];  /*  */
  37         AT91_REG         TC_CV;         /* Counter Value */
  38         AT91_REG         TC_RA;         /* Register A */
  39         AT91_REG         TC_RB;         /* Register B */
  40         AT91_REG         TC_RC;         /* Register C */
  41         AT91_REG         TC_SR;         /* Status Register */
  42         AT91_REG         TC_IER;        /* Interrupt Enable Register */
  43         AT91_REG         TC_IDR;        /* Interrupt Disable Register */
  44         AT91_REG         TC_IMR;        /* Interrupt Mask Register */
  45 } AT91S_TC, *AT91PS_TC;
  46
  47 #define AT91C_TC_TIMER_DIV1_CLOCK      ((unsigned int) 0x0 <<  0) /* (TC) MCK/2 */
  48 #define AT91C_TC_TIMER_DIV2_CLOCK      ((unsigned int) 0x1 <<  0) /* (TC) MCK/8 */
  49 #define AT91C_TC_TIMER_DIV3_CLOCK      ((unsigned int) 0x2 <<  0) /* (TC) MCK/32 */
  50 #define AT91C_TC_TIMER_DIV4_CLOCK      ((unsigned int) 0x3 <<  0) /* (TC) MCK/128 */
  51 #define AT91C_TC_SLOW_CLOCK            ((unsigned int) 0x4 <<  0) /* (TC) SLOW CLK */
  52 #define AT91C_TC_XC0_CLOCK             ((unsigned int) 0x5 <<  0) /* (TC) XC0 */
  53 #define AT91C_TC_XC1_CLOCK             ((unsigned int) 0x6 <<  0) /* (TC) XC1 */
  54 #define AT91C_TC_XC2_CLOCK             ((unsigned int) 0x7 <<  0) /* (TC) XC2 */
  55 #define         AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
  56 #define         AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) /* (TCB) None signal connected to XC1 */
  57 #define         AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) /* (TCB) None signal connected to XC2 */
  58 #define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) /* (TC) Counter Clock Disable Command */
  59 #define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) /* (TC) Software Trigger Command */
  60 #define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) /* (TC) Counter Clock Enable Command */
  61
  62 /* ***************************************************************************** */
  63 /*              SOFTWARE API DEFINITION  FOR Usart */
  64 /* ***************************************************************************** */
  65 typedef struct _AT91S_USART {
  66         AT91_REG         US_CR;         /* Control Register */
  67         AT91_REG         US_MR;         /* Mode Register */
  68         AT91_REG         US_IER;        /* Interrupt Enable Register */
  69         AT91_REG         US_IDR;        /* Interrupt Disable Register */
  70         AT91_REG         US_IMR;        /* Interrupt Mask Register */
  71         AT91_REG         US_CSR;        /* Channel Status Register */
  72         AT91_REG         US_RHR;        /* Receiver Holding Register */
  73         AT91_REG         US_THR;        /* Transmitter Holding Register */
  74         AT91_REG         US_BRGR;       /* Baud Rate Generator Register */
  75         AT91_REG         US_RTOR;       /* Receiver Time-out Register */
  76         AT91_REG         US_TTGR;       /* Transmitter Time-guard Register */
  77         AT91_REG         Reserved0[5];  /*  */
  78         AT91_REG         US_FIDI;       /* FI_DI_Ratio Register */
  79         AT91_REG         US_NER;        /* Nb Errors Register */
  80         AT91_REG         US_XXR;        /* XON_XOFF Register */
  81         AT91_REG         US_IF;         /* IRDA_FILTER Register */
  82         AT91_REG         Reserved1[44];         /*  */
  83         AT91_REG         US_RPR;        /* Receive Pointer Register */
  84         AT91_REG         US_RCR;        /* Receive Counter Register */
  85         AT91_REG         US_TPR;        /* Transmit Pointer Register */
  86         AT91_REG         US_TCR;        /* Transmit Counter Register */
  87         AT91_REG         US_RNPR;       /* Receive Next Pointer Register */
  88         AT91_REG         US_RNCR;       /* Receive Next Counter Register */
  89         AT91_REG         US_TNPR;       /* Transmit Next Pointer Register */
  90         AT91_REG         US_TNCR;       /* Transmit Next Counter Register */
  91         AT91_REG         US_PTCR;       /* PDC Transfer Control Register */
  92         AT91_REG         US_PTSR;       /* PDC Transfer Status Register */
  93 } AT91S_USART, *AT91PS_USART;
  94
  95 /* ***************************************************************************** */
  96 /*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler */
  97 /* ***************************************************************************** */
  98 typedef struct _AT91S_PIO {
  99         AT91_REG         PIO_PER;       /* PIO Enable Register */
 100         AT91_REG         PIO_PDR;       /* PIO Disable Register */
 101         AT91_REG         PIO_PSR;       /* PIO Status Register */
 102         AT91_REG         Reserved0[1];  /*  */
 103         AT91_REG         PIO_OER;       /* Output Enable Register */
 104         AT91_REG         PIO_ODR;       /* Output Disable Registerr */
 105         AT91_REG         PIO_OSR;       /* Output Status Register */
 106         AT91_REG         Reserved1[1];  /*  */
 107         AT91_REG         PIO_IFER;      /* Input Filter Enable Register */
 108         AT91_REG         PIO_IFDR;      /* Input Filter Disable Register */
 109         AT91_REG         PIO_IFSR;      /* Input Filter Status Register */
 110         AT91_REG         Reserved2[1];  /*  */
 111         AT91_REG         PIO_SODR;      /* Set Output Data Register */
 112         AT91_REG         PIO_CODR;      /* Clear Output Data Register */
 113         AT91_REG         PIO_ODSR;      /* Output Data Status Register */
 114         AT91_REG         PIO_PDSR;      /* Pin Data Status Register */
 115         AT91_REG         PIO_IER;       /* Interrupt Enable Register */
 116         AT91_REG         PIO_IDR;       /* Interrupt Disable Register */
 117         AT91_REG         PIO_IMR;       /* Interrupt Mask Register */
 118         AT91_REG         PIO_ISR;       /* Interrupt Status Register */
 119         AT91_REG         PIO_MDER;      /* Multi-driver Enable Register */
 120         AT91_REG         PIO_MDDR;      /* Multi-driver Disable Register */
 121         AT91_REG         PIO_MDSR;      /* Multi-driver Status Register */
 122         AT91_REG         Reserved3[1];  /*  */
 123         AT91_REG         PIO_PPUDR;     /* Pull-up Disable Register */
 124         AT91_REG         PIO_PPUER;     /* Pull-up Enable Register */
 125         AT91_REG         PIO_PPUSR;     /* Pad Pull-up Status Register */
 126         AT91_REG         Reserved4[1];  /*  */
 127         AT91_REG         PIO_ASR;       /* Select A Register */
 128         AT91_REG         PIO_BSR;       /* Select B Register */
 129         AT91_REG         PIO_ABSR;      /* AB Select Status Register */
 130         AT91_REG         Reserved5[9];  /*  */
 131         AT91_REG         PIO_OWER;      /* Output Write Enable Register */
 132         AT91_REG         PIO_OWDR;      /* Output Write Disable Register */
 133         AT91_REG         PIO_OWSR;      /* Output Write Status Register */
 134 } AT91S_PIO, *AT91PS_PIO;
 135
 136
 137 /* ***************************************************************************** */
 138 /*              SOFTWARE API DEFINITION  FOR Debug Unit */
 139 /* ***************************************************************************** */
 140 typedef struct _AT91S_DBGU {
 141         AT91_REG         DBGU_CR;       /* Control Register */
 142         AT91_REG         DBGU_MR;       /* Mode Register */
 143         AT91_REG         DBGU_IER;      /* Interrupt Enable Register */
 144         AT91_REG         DBGU_IDR;      /* Interrupt Disable Register */
 145         AT91_REG         DBGU_IMR;      /* Interrupt Mask Register */
 146         AT91_REG         DBGU_CSR;      /* Channel Status Register */
 147         AT91_REG         DBGU_RHR;      /* Receiver Holding Register */
 148         AT91_REG         DBGU_THR;      /* Transmitter Holding Register */
 149         AT91_REG         DBGU_BRGR;     /* Baud Rate Generator Register */
 150         AT91_REG         Reserved0[7];  /*  */
 151         AT91_REG         DBGU_C1R;      /* Chip ID1 Register */
 152         AT91_REG         DBGU_C2R;      /* Chip ID2 Register */
 153         AT91_REG         DBGU_FNTR;     /* Force NTRST Register */
 154         AT91_REG         Reserved1[45];         /*  */
 155         AT91_REG         DBGU_RPR;      /* Receive Pointer Register */
 156         AT91_REG         DBGU_RCR;      /* Receive Counter Register */
 157         AT91_REG         DBGU_TPR;      /* Transmit Pointer Register */
 158         AT91_REG         DBGU_TCR;      /* Transmit Counter Register */
 159         AT91_REG         DBGU_RNPR;     /* Receive Next Pointer Register */
 160         AT91_REG         DBGU_RNCR;     /* Receive Next Counter Register */
 161         AT91_REG         DBGU_TNPR;     /* Transmit Next Pointer Register */
 162         AT91_REG         DBGU_TNCR;     /* Transmit Next Counter Register */
 163         AT91_REG         DBGU_PTCR;     /* PDC Transfer Control Register */
 164         AT91_REG         DBGU_PTSR;     /* PDC Transfer Status Register */
 165 } AT91S_DBGU, *AT91PS_DBGU;
 166
 167 /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------  */
 168 #define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) /* (DBGU) RXRDY Interrupt */
 169 #define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) /* (DBGU) TXRDY Interrupt */
 170 #define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) /* (DBGU) End of Receive Transfer Interrupt */
 171 #define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) /* (DBGU) End of Transmit Interrupt */
 172 #define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) /* (DBGU) Overrun Interrupt */
 173 #define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) /* (DBGU) Framing Error Interrupt */
 174 #define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) /* (DBGU) Parity Error Interrupt */
 175 #define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) /* (DBGU) TXEMPTY Interrupt */
 176 #define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
 177 #define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
 178 #define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
 179 #define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
 180
 181 /* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------  */
 182 #define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) /* (DBGU) Reset Receiver */
 183 #define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) /* (DBGU) Reset Transmitter */
 184 #define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) /* (DBGU) Receiver Enable */
 185 #define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) /* (DBGU) Receiver Disable */
 186 #define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) /* (DBGU) Transmitter Enable */
 187 #define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) /* (DBGU) Transmitter Disable */
 188
 189 #define AT91C_US_CLKS_CLOCK             ((unsigned int) 0x0 <<  4) /* (USART) Clock */
 190 #define AT91C_US_CHRL_8_BITS            ((unsigned int) 0x3 <<  6) /* (USART) Character Length: 8 bits */
 191 #define AT91C_US_PAR_NONE               ((unsigned int) 0x4 <<  9) /* (DBGU) No Parity */
 192 #define AT91C_US_NBSTOP_1_BIT           ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
 193
 194 /* ***************************************************************************** */
 195 /*              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface */
 196 /* ***************************************************************************** */
 197 typedef struct _AT91S_SMC2 {
 198         AT91_REG         SMC2_CSR[8];   /* SMC2 Chip Select Register */
 199 } AT91S_SMC2, *AT91PS_SMC2;
 200
 201 /* ***************************************************************************** */
 202 /*              SOFTWARE API DEFINITION  FOR Power Management Controler         */
 203 /* ******************************************************************************/
 204 typedef struct _AT91S_PMC {
 205         AT91_REG         PMC_SCER;      /* System Clock Enable Register */
 206         AT91_REG         PMC_SCDR;      /* System Clock Disable Register */
 207         AT91_REG         PMC_SCSR;      /* System Clock Status Register */
 208         AT91_REG         Reserved0[1];  /* */
 209         AT91_REG         PMC_PCER;      /* Peripheral Clock Enable Register */
 210         AT91_REG         PMC_PCDR;      /* Peripheral Clock Disable Register */
 211         AT91_REG         PMC_PCSR;      /* Peripheral Clock Status Register */
 212         AT91_REG         Reserved1[5];  /* */
 213         AT91_REG         PMC_MCKR;      /* Master Clock Register */
 214         AT91_REG         Reserved2[3];  /* */
 215         AT91_REG         PMC_PCKR[8];   /* Programmable Clock Register */
 216         AT91_REG         PMC_IER;       /* Interrupt Enable Register */
 217         AT91_REG         PMC_IDR;       /* Interrupt Disable Register */
 218         AT91_REG         PMC_SR;        /* Status Register */
 219         AT91_REG         PMC_IMR;       /* Interrupt Mask Register */
 220 } AT91S_PMC, *AT91PS_PMC;
 221
 222
 223 /* ***************************************************************************** */
 224 /*              SOFTWARE API DEFINITION  FOR Ethernet MAC */
 225 /* ***************************************************************************** */
 226 typedef struct _AT91S_EMAC {
 227         AT91_REG         EMAC_CTL;      /* Network Control Register */
 228         AT91_REG         EMAC_CFG;      /* Network Configuration Register */
 229         AT91_REG         EMAC_SR;       /* Network Status Register */
 230         AT91_REG         EMAC_TAR;      /* Transmit Address Register */
 231         AT91_REG         EMAC_TCR;      /* Transmit Control Register */
 232         AT91_REG         EMAC_TSR;      /* Transmit Status Register */
 233         AT91_REG         EMAC_RBQP;     /* Receive Buffer Queue Pointer */
 234         AT91_REG         Reserved0[1];  /*  */
 235         AT91_REG         EMAC_RSR;      /* Receive Status Register */
 236         AT91_REG         EMAC_ISR;      /* Interrupt Status Register */
 237         AT91_REG         EMAC_IER;      /* Interrupt Enable Register */
 238         AT91_REG         EMAC_IDR;      /* Interrupt Disable Register */
 239         AT91_REG         EMAC_IMR;      /* Interrupt Mask Register */
 240         AT91_REG         EMAC_MAN;      /* PHY Maintenance Register */
 241         AT91_REG         Reserved1[2];  /*  */
 242         AT91_REG         EMAC_FRA;      /* Frames Transmitted OK Register */
 243         AT91_REG         EMAC_SCOL;     /* Single Collision Frame Register */
 244         AT91_REG         EMAC_MCOL;     /* Multiple Collision Frame Register */
 245         AT91_REG         EMAC_OK;       /* Frames Received OK Register */
 246         AT91_REG         EMAC_SEQE;     /* Frame Check Sequence Error Register */
 247         AT91_REG         EMAC_ALE;      /* Alignment Error Register */
 248         AT91_REG         EMAC_DTE;      /* Deferred Transmission Frame Register */
 249         AT91_REG         EMAC_LCOL;     /* Late Collision Register */
 250         AT91_REG         EMAC_ECOL;     /* Excessive Collision Register */
 251         AT91_REG         EMAC_CSE;      /* Carrier Sense Error Register */
 252         AT91_REG         EMAC_TUE;      /* Transmit Underrun Error Register */
 253         AT91_REG         EMAC_CDE;      /* Code Error Register */
 254         AT91_REG         EMAC_ELR;      /* Excessive Length Error Register */
 255         AT91_REG         EMAC_RJB;      /* Receive Jabber Register */
 256         AT91_REG         EMAC_USF;      /* Undersize Frame Register */
 257         AT91_REG         EMAC_SQEE;     /* SQE Test Error Register */
 258         AT91_REG         EMAC_DRFC;     /* Discarded RX Frame Register */
 259         AT91_REG         Reserved2[3];  /*  */
 260         AT91_REG         EMAC_HSH;      /* Hash Address High[63:32] */
 261         AT91_REG         EMAC_HSL;      /* Hash Address Low[31:0] */
 262         AT91_REG         EMAC_SA1L;     /* Specific Address 1 Low, First 4 bytes */
 263         AT91_REG         EMAC_SA1H;     /* Specific Address 1 High, Last 2 bytes */
 264         AT91_REG         EMAC_SA2L;     /* Specific Address 2 Low, First 4 bytes */
 265         AT91_REG         EMAC_SA2H;     /* Specific Address 2 High, Last 2 bytes */
 266         AT91_REG         EMAC_SA3L;     /* Specific Address 3 Low, First 4 bytes */
 267         AT91_REG         EMAC_SA3H;     /* Specific Address 3 High, Last 2 bytes */
 268         AT91_REG         EMAC_SA4L;     /* Specific Address 4 Low, First 4 bytes */
 269         AT91_REG         EMAC_SA4H;     /* Specific Address 4 High, Last 2 bytesr */
 270 } AT91S_EMAC, *AT91PS_EMAC;
 271
 272 /* -------- EMAC_CTL : (EMAC Offset: 0x0)  --------  */
 273 #define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
 274 #define AT91C_EMAC_LBL        ((unsigned int) 0x1 <<  1) /* (EMAC) Loopback local. */
 275 #define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) /* (EMAC) Receive enable. */
 276 #define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) /* (EMAC) Transmit enable. */
 277 #define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) /* (EMAC) Management port enable. */
 278 #define AT91C_EMAC_CSR        ((unsigned int) 0x1 <<  5) /* (EMAC) Clear statistics registers. */
 279 #define AT91C_EMAC_ISR        ((unsigned int) 0x1 <<  6) /* (EMAC) Increment statistics registers. */
 280 #define AT91C_EMAC_WES        ((unsigned int) 0x1 <<  7) /* (EMAC) Write enable for statistics registers. */
 281 #define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) /* (EMAC) Back pressure. */
 282 /* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------  */
 283 #define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) /* (EMAC) Speed. */
 284 #define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) /* (EMAC) Full duplex. */
 285 #define AT91C_EMAC_BR         ((unsigned int) 0x1 <<  2) /* (EMAC) Bit rate. */
 286 #define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) /* (EMAC) Copy all frames. */
 287 #define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) /* (EMAC) No broadcast. */
 288 #define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) /* (EMAC) Multicast hash enable */
 289 #define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) /* (EMAC) Unicast hash enable. */
 290 #define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) /* (EMAC) Receive 1522 bytes. */
 291 #define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) /* (EMAC) External address match enable. */
 292 #define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) /* (EMAC) */
 293 #define         AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
 294 #define         AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
 295 #define         AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
 296 #define         AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
 297 #define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) /* (EMAC) */
 298 #define AT91C_EMAC_RMII       ((unsigned int) 0x1 << 13) /* (EMAC) */
 299 /* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------  */
 300 #define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) /* (EMAC) */
 301 #define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) /* (EMAC) */
 302 /* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
 303 #define AT91C_EMAC_LEN        ((unsigned int) 0x7FF <<  0) /* (EMAC) */
 304 #define AT91C_EMAC_NCRC       ((unsigned int) 0x1 << 15) /* (EMAC) */
 305 /* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
 306 #define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  0) /* (EMAC) */
 307 #define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) /* (EMAC) */
 308 #define AT91C_EMAC_RLE        ((unsigned int) 0x1 <<  2) /* (EMAC) */
 309 #define AT91C_EMAC_TXIDLE     ((unsigned int) 0x1 <<  3) /* (EMAC) */
 310 #define AT91C_EMAC_BNQ        ((unsigned int) 0x1 <<  4) /* (EMAC) */
 311 #define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) /* (EMAC) */
 312 #define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) /* (EMAC) */
 313 /* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
 314 #define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) /* (EMAC) */
 315 #define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) /* (EMAC) */
 316 #define AT91C_EMAC_RSR_OVR    ((unsigned int) 0x1 <<  2) /* (EMAC) */
 317 /* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
 318 #define AT91C_EMAC_DONE       ((unsigned int) 0x1 <<  0) /* (EMAC) */
 319 #define AT91C_EMAC_RCOM       ((unsigned int) 0x1 <<  1) /* (EMAC) */
 320 #define AT91C_EMAC_RBNA       ((unsigned int) 0x1 <<  2) /* (EMAC) */
 321 #define AT91C_EMAC_TOVR       ((unsigned int) 0x1 <<  3) /* (EMAC) */
 322 #define AT91C_EMAC_TUND       ((unsigned int) 0x1 <<  4) /* (EMAC) */
 323 #define AT91C_EMAC_RTRY       ((unsigned int) 0x1 <<  5) /* (EMAC) */
 324 #define AT91C_EMAC_TBRE       ((unsigned int) 0x1 <<  6) /* (EMAC) */
 325 #define AT91C_EMAC_TCOM       ((unsigned int) 0x1 <<  7) /* (EMAC) */
 326 #define AT91C_EMAC_TIDLE      ((unsigned int) 0x1 <<  8) /* (EMAC) */
 327 #define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) /* (EMAC) */
 328 #define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) /* (EMAC) */
 329 #define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) /* (EMAC) */
 330 /* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
 331 /* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
 332 /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
 333 /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
 334 #define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) /* (EMAC) */
 335 #define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) /* (EMAC) */
 336 #define         AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */
 337 #define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) /* (EMAC) */
 338 #define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) /* (EMAC) */
 339 #define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) /* (EMAC) */
 340 #define         AT91C_EMAC_RW_R       ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */
 341 #define         AT91C_EMAC_RW_W       ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */
 342 #define AT91C_EMAC_HIGH       ((unsigned int) 0x1 << 30) /* (EMAC) */
 343 #define AT91C_EMAC_LOW        ((unsigned int) 0x1 << 31) /* (EMAC) */
 344
 345 /* ***************************************************************************** */
 346 /*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface          */
 347 /* ***************************************************************************** */
 348 typedef struct _AT91S_SPI {
 349         AT91_REG         SPI_CR;        /* Control Register */
 350         AT91_REG         SPI_MR;        /* Mode Register */
 351         AT91_REG         SPI_RDR;       /* Receive Data Register */
 352         AT91_REG         SPI_TDR;       /* Transmit Data Register */
 353         AT91_REG         SPI_SR;        /* Status Register */
 354         AT91_REG         SPI_IER;       /* Interrupt Enable Register */
 355         AT91_REG         SPI_IDR;       /* Interrupt Disable Register */
 356         AT91_REG         SPI_IMR;       /* Interrupt Mask Register */
 357         AT91_REG         Reserved0[4];  /* */
 358         AT91_REG         SPI_CSR[4];    /* Chip Select Register */
 359         AT91_REG         Reserved1[48]; /* */
 360         AT91_REG         SPI_RPR;       /* Receive Pointer Register */
 361         AT91_REG         SPI_RCR;       /* Receive Counter Register */
 362         AT91_REG         SPI_TPR;       /* Transmit Pointer Register */
 363         AT91_REG         SPI_TCR;       /* Transmit Counter Register */
 364         AT91_REG         SPI_RNPR;      /* Receive Next Pointer Register */
 365         AT91_REG         SPI_RNCR;      /* Receive Next Counter Register */
 366         AT91_REG         SPI_TNPR;      /* Transmit Next Pointer Register */
 367         AT91_REG         SPI_TNCR;      /* Transmit Next Counter Register */
 368         AT91_REG         SPI_PTCR;      /* PDC Transfer Control Register */
 369         AT91_REG         SPI_PTSR;      /* PDC Transfer Status Register */
 370 } AT91S_SPI, *AT91PS_SPI;
 371
 372 /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
 373 #define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) /* (SPI) SPI Enable */
 374 #define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) /* (SPI) SPI Disable */
 375 #define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) /* (SPI) SPI Software reset */
 376 /* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
 377 #define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) /* (SPI) Master/Slave Mode */
 378 #define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) /* (SPI) Peripheral Select */
 379 #define         AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) /* (SPI) Fixed Peripheral Select */
 380 #define         AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) /* (SPI) Variable Peripheral Select */
 381 #define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) /* (SPI) Chip Select Decode */
 382 #define AT91C_SPI_DIV32       ((unsigned int) 0x1 <<  3) /* (SPI) Clock Selection */
 383 #define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) /* (SPI) Mode Fault Detection */
 384 #define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) /* (SPI) Clock Selection */
 385 #define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
 386 #define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
 387 /* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
 388 #define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) /* (SPI) Receive Data */
 389 #define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
 390 /* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
 391 #define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) /* (SPI) Transmit Data */
 392 #define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
 393 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
 394 #define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) /* (SPI) Receive Data Register Full */
 395 #define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) /* (SPI) Transmit Data Register Empty */
 396 #define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) /* (SPI) Mode Fault Error */
 397 #define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) /* (SPI) Overrun Error Status */
 398 #define AT91C_SPI_SPENDRX     ((unsigned int) 0x1 <<  4) /* (SPI) End of Receiver Transfer */
 399 #define AT91C_SPI_SPENDTX     ((unsigned int) 0x1 <<  5) /* (SPI) End of Receiver Transfer */
 400 #define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) /* (SPI) RXBUFF Interrupt */
 401 #define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) /* (SPI) TXBUFE Interrupt */
 402 #define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
 403 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
 404 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
 405 /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
 406 /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
 407 #define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) /* (SPI) Clock Polarity */
 408 #define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) /* (SPI) Clock Phase */
 409 #define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) /* (SPI) Bits Per Transfer */
 410 #define         AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) /* (SPI) 8 Bits Per transfer */
 411 #define         AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) /* (SPI) 9 Bits Per transfer */
 412 #define         AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) /* (SPI) 10 Bits Per transfer */
 413 #define         AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) /* (SPI) 11 Bits Per transfer */
 414 #define         AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) /* (SPI) 12 Bits Per transfer */
 415 #define         AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) /* (SPI) 13 Bits Per transfer */
 416 #define         AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) /* (SPI) 14 Bits Per transfer */
 417 #define         AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) /* (SPI) 15 Bits Per transfer */
 418 #define         AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) /* (SPI) 16 Bits Per transfer */
 419 #define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) /* (SPI) Serial Clock Baud Rate */
 420 #define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
 421 #define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
 422
 423 /* ***************************************************************************** */
 424 /*              SOFTWARE API DEFINITION  FOR Peripheral Data Controller         */
 425 /* ***************************************************************************** */
 426 typedef struct _AT91S_PDC {
 427         AT91_REG         PDC_RPR;       /* Receive Pointer Register */
 428         AT91_REG         PDC_RCR;       /* Receive Counter Register */
 429         AT91_REG         PDC_TPR;       /* Transmit Pointer Register */
 430         AT91_REG         PDC_TCR;       /* Transmit Counter Register */
 431         AT91_REG         PDC_RNPR;      /* Receive Next Pointer Register */
 432         AT91_REG         PDC_RNCR;      /* Receive Next Counter Register */
 433         AT91_REG         PDC_TNPR;      /* Transmit Next Pointer Register */
 434         AT91_REG         PDC_TNCR;      /* Transmit Next Counter Register */
 435         AT91_REG         PDC_PTCR;      /* PDC Transfer Control Register */
 436         AT91_REG         PDC_PTSR;      /* PDC Transfer Status Register */
 437 } AT91S_PDC, *AT91PS_PDC;
 438
 439 /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
 440 #define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) /* (PDC) Receiver Transfer Enable */
 441 #define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) /* (PDC) Receiver Transfer Disable */
 442 #define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) /* (PDC) Transmitter Transfer Enable */
 443 #define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) /* (PDC) Transmitter Transfer Disable */
 444 /* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------  */
 445
 446 /* ========== Register definition ==================================== */
 447 #define AT91C_SPI_CSR   ((AT91_REG *)   0xFFFE0030) /* (SPI) Chip Select Register */
 448 #define AT91C_PMC_PCER  ((AT91_REG *)   0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
 449 #define AT91C_PIOA_PDR  ((AT91_REG *)   0xFFFFF404) /* (PIOA) PIO Disable Register */
 450
 451 #define AT91C_PIO_PA30       ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
 452 #define AT91C_PIO_PC0        ((unsigned int) 1 <<  0) /* Pin Controlled by PC0 */
 453 #define AT91C_PC0_BFCK     ((unsigned int) AT91C_PIO_PC0) /*  Burst Flash Clock */
 454 #define AT91C_PA30_DRXD     ((unsigned int) AT91C_PIO_PA30) /*  DBGU Debug Receive Data */
 455 #define AT91C_PIO_PA31       ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */
 456 #define AT91C_PA31_DTXD     ((unsigned int) AT91C_PIO_PA31) /*  DBGU Debug Transmit Data */
 457
 458 #define AT91C_ID_SYS    ((unsigned int)  1) /* System Peripheral */
 459 #define AT91C_ID_TC0    ((unsigned int) 17) /* Timer Counter 0 */
 460 #define AT91C_ID_EMAC   ((unsigned int) 24) /* Ethernet MAC */
 461 #define AT91C_ID_SPI    ((unsigned int) 13) /* Serial Peripheral Interface */
 462
 463 #define AT91C_PIO_PC1        ((unsigned int) 1 <<  1) /* Pin Controlled by PC1 */
 464 #define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /*  Burst Flash Ready */
 465 #define AT91C_PIO_PC3        ((unsigned int) 1 <<  3) /* Pin Controlled by PC3 */
 466 #define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /*  Burst Flash Address Advance / SmartMedia Write Enable */
 467 #define AT91C_PIO_PC2        ((unsigned int) 1 <<  2) /* Pin Controlled by PC2 */
 468 #define AT91C_PC2_BFAVD    ((unsigned int) AT91C_PIO_PC2) /*  Burst Flash Address Valid */
 469 #define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) /* Pin Controlled by PB1 */
 470
 471 #define AT91C_PIO_PA23       ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */
 472 #define AT91C_PA23_TXD2     ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */
 473
 474 #define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) /* Pin Controlled by PA0 */
 475 #define AT91C_PA0_MISO     ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */
 476 #define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) /* Pin Controlled by PA1 */
 477 #define AT91C_PA1_MOSI     ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */
 478 #define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) /* Pin Controlled by PA2 */
 479 #define AT91C_PA2_SPCK     ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */
 480 #define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) /* Pin Controlled by PA3 */
 481 #define AT91C_PA3_NPCS0    ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */
 482 #define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) /* Pin Controlled by PA4 */
 483 #define AT91C_PA4_NPCS1    ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */
 484 #define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) /* Pin Controlled by PA5 */
 485 #define AT91C_PA5_NPCS2    ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */
 486 #define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) /* Pin Controlled by PA6 */
 487 #define AT91C_PA6_NPCS3    ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */
 488
 489
 490 #define AT91C_PIO_PA16       ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
 491 #define AT91C_PA16_EMDIO    ((unsigned int) AT91C_PIO_PA16) /*  Ethernet MAC Management Data Input/Output */
 492 #define AT91C_PIO_PA15       ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
 493 #define AT91C_PA15_EMDC     ((unsigned int) AT91C_PIO_PA15) /*  Ethernet MAC Management Data Clock */
 494 #define AT91C_PIO_PA14       ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */
 495 #define AT91C_PA14_ERXER    ((unsigned int) AT91C_PIO_PA14) /*  Ethernet MAC Receive Error */
 496 #define AT91C_PIO_PA13       ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */
 497 #define AT91C_PA13_ERX1     ((unsigned int) AT91C_PIO_PA13) /*  Ethernet MAC Receive Data 1 */
 498 #define AT91C_PIO_PA12       ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */
 499 #define AT91C_PA12_ERX0     ((unsigned int) AT91C_PIO_PA12) /*  Ethernet MAC Receive Data 0 */
 500 #define AT91C_PIO_PA11       ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */
 501 #define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /*  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
 502 #define AT91C_PIO_PA10       ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */
 503 #define AT91C_PA10_ETX1     ((unsigned int) AT91C_PIO_PA10) /*  Ethernet MAC Transmit Data 1 */
 504 #define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) /* Pin Controlled by PA9 */
 505 #define AT91C_PA9_ETX0     ((unsigned int) AT91C_PIO_PA9) /*  Ethernet MAC Transmit Data 0 */
 506 #define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) /* Pin Controlled by PA8 */
 507 #define AT91C_PA8_ETXEN    ((unsigned int) AT91C_PIO_PA8) /*  Ethernet MAC Transmit Enable */
 508 #define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) /* Pin Controlled by PA7 */
 509 #define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /*  Ethernet MAC Transmit Clock/Reference Clock */
 510
 511 #define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) /* Pin Controlled by PB7 */
 512 #define AT91C_PIO_PB25       ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
 513 #define AT91C_PB25_DSR1     ((unsigned int) AT91C_PIO_PB25) /*  USART 1 Data Set ready */
 514 #define AT91C_PB25_EF100    ((unsigned int) AT91C_PIO_PB25) /*  Ethernet MAC Force 100 Mbits */
 515 #define AT91C_PIO_PB19       ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */
 516 #define AT91C_PB19_DTR1     ((unsigned int) AT91C_PIO_PB19) /*  USART 1 Data Terminal ready */
 517 #define AT91C_PB19_ERXCK    ((unsigned int) AT91C_PIO_PB19) /*  Ethernet MAC Receive Clock */
 518 #define AT91C_PIO_PB18       ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */
 519 #define AT91C_PB18_RI1      ((unsigned int) AT91C_PIO_PB18) /*  USART 1 Ring Indicator */
 520 #define AT91C_PB18_ECOL     ((unsigned int) AT91C_PIO_PB18) /*  Ethernet MAC Collision Detected */
 521 #define AT91C_PIO_PB17       ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */
 522 #define AT91C_PB17_RF2      ((unsigned int) AT91C_PIO_PB17) /*  SSC Receive Frame Sync 2 */
 523 #define AT91C_PB17_ERXDV    ((unsigned int) AT91C_PIO_PB17) /*  Ethernet MAC Receive Data Valid */
 524 #define AT91C_PIO_PB16       ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */
 525 #define AT91C_PB16_RK2      ((unsigned int) AT91C_PIO_PB16) /*  SSC Receive Clock 2 */
 526 #define AT91C_PB16_ERX3     ((unsigned int) AT91C_PIO_PB16) /*  Ethernet MAC Receive Data 3 */
 527 #define AT91C_PIO_PB15       ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */
 528 #define AT91C_PB15_RD2      ((unsigned int) AT91C_PIO_PB15) /*  SSC Receive Data 2 */
 529 #define AT91C_PB15_ERX2     ((unsigned int) AT91C_PIO_PB15) /*  Ethernet MAC Receive Data 2 */
 530 #define AT91C_PIO_PB14       ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */
 531 #define AT91C_PB14_TD2      ((unsigned int) AT91C_PIO_PB14) /*  SSC Transmit Data 2 */
 532 #define AT91C_PB14_ETXER    ((unsigned int) AT91C_PIO_PB14) /*  Ethernet MAC Transmikt Coding Error */
 533 #define AT91C_PIO_PB13       ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */
 534 #define AT91C_PB13_TK2      ((unsigned int) AT91C_PIO_PB13) /*  SSC Transmit Clock 2 */
 535 #define AT91C_PB13_ETX3     ((unsigned int) AT91C_PIO_PB13) /*  Ethernet MAC Transmit Data 3 */
 536 #define AT91C_PIO_PB12       ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */
 537 #define AT91C_PB12_TF2      ((unsigned int) AT91C_PIO_PB12) /*  SSC Transmit Frame Sync 2 */
 538 #define AT91C_PB12_ETX2     ((unsigned int) AT91C_PIO_PB12) /*  Ethernet MAC Transmit Data 2 */
 539
 540 #define AT91C_PIOB_BSR  ((AT91_REG *)   0xFFFFF674) /* (PIOB) Select B Register */
 541 #define AT91C_PIOB_PDR  ((AT91_REG *)   0xFFFFF604) /* (PIOB) PIO Disable Register */
 542
 543 #define         AT91C_EBI_CS3A_SMC_SmartMedia       ((unsigned int) 0x1 <<  3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
 544 #define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
 545 #define AT91C_SMC2_DBW_8      ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
 546 #define AT91C_SMC2_WSEN       ((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
 547 #define AT91C_PIOC_ASR  ((AT91_REG *)   0xFFFFF870) /* (PIOC) Select A Register */
 548 #define AT91C_PIOC_SODR ((AT91_REG *)   0xFFFFF830) /* (PIOC) Set Output Data Register */
 549 #define AT91C_PIOC_CODR ((AT91_REG *)   0xFFFFF834) /* (PIOC) Clear Output Data Register */
 550 #define AT91C_PIOC_PDSR ((AT91_REG *)   0xFFFFF83C) /* (PIOC) Pin Data Status Register */
 551
 552 #define AT91C_BASE_SPI       ((AT91PS_SPI)      0xFFFE0000) /* (SPI) Base Address */
 553 #define AT91C_BASE_EMAC      ((AT91PS_EMAC)     0xFFFBC000) /* (EMAC) Base Address */
 554 #define AT91C_BASE_PMC       ((AT91PS_PMC)      0xFFFFFC00) /* (PMC) Base Address */
 555 #define AT91C_BASE_TC0       ((AT91PS_TC)       0xFFFA0000) /* (TC0) Base Address */
 556 #define AT91C_BASE_DBGU      ((AT91PS_DBGU)     0xFFFFF200) /* (DBGU) Base Address */
 557 #define AT91C_BASE_PIOB      ((AT91PS_PIO)      0xFFFFF600) /* (PIOB) Base Address */
 558 #define AT91C_BASE_PIOA      ((AT91PS_PIO)      0xFFFFF400) /* (PIOA) Base Address */
 559 #define AT91C_EBI_CSA   ((AT91_REG *)   0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
 560 #define AT91C_BASE_SMC2      ((AT91PS_SMC2)     0xFFFFFF70) /* (SMC2) Base Address */
 561 #define AT91C_BASE_US1       ((AT91PS_USART)    0xFFFC4000) /* (US1) Base Address */
 562 #define AT91C_TCB0_BMR  ((AT91_REG *)   0xFFFA00C4) /* (TCB0) TC Block Mode Register */
 563 #define AT91C_TCB0_BCR  ((AT91_REG *)   0xFFFA00C0) /* (TCB0) TC Block Control Register */
 564 #define AT91C_PIOC_PDR  ((AT91_REG *)   0xFFFFF804) /* (PIOC) PIO Disable Register */
 565 #define AT91C_PIOC_PER  ((AT91_REG *)   0xFFFFF800) /* (PIOC) PIO Enable Register */
 566 #define AT91C_PIOC_ODR  ((AT91_REG *)   0xFFFFF814) /* (PIOC) Output Disable Registerr */
 567 #define AT91C_PIOB_PER  ((AT91_REG *)   0xFFFFF600) /* (PIOB) PIO Enable Register */
 568 #define AT91C_PIOB_ODR  ((AT91_REG *)   0xFFFFF614) /* (PIOB) Output Disable Registerr */
 569 #define AT91C_PIOB_PDSR ((AT91_REG *)   0xFFFFF63C) /* (PIOB) Pin Data Status Register */
 570
 571 #endif