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[people/ms/u-boot.git] / include / asm-arm / arch-pxa / pxa-regs.h
1 /*
2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13
14 /* FIXME hack so that SA-1111.h will work [cb] */
15
16 #ifndef __ASSEMBLY__
17 typedef unsigned short Word16 ;
18 typedef unsigned int Word32 ;
19 typedef Word32 Word ;
20 typedef Word Quad [4] ;
21 typedef void *Address ;
22 typedef void (*ExcpHndlr) (void) ;
23 #endif
24
25 #ifndef __ASSEMBLY__
26 #define io_p2v(PhAdd) (PhAdd)
27 #define __REG(x) (*((volatile u32 *)io_p2v(x)))
28 #else
29 #define __REG(x) (x)
30 #endif
31
32 /*
33 * PXA Chip selects
34 */
35
36 #define PXA_CS0_PHYS 0x00000000
37 #define PXA_CS1_PHYS 0x04000000
38 #define PXA_CS2_PHYS 0x08000000
39 #define PXA_CS3_PHYS 0x0C000000
40 #define PXA_CS4_PHYS 0x10000000
41 #define PXA_CS5_PHYS 0x14000000
42
43
44 /*
45 * Personal Computer Memory Card International Association (PCMCIA) sockets
46 */
47
48 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
49 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
50 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
51 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
52 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
53
54 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
55 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
56 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
57 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
58
59 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
60 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
61 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
62 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
63
64 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
65 (0x20000000 + (Nb)*PCMCIASp)
66 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
67 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
68 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
69 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
70 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
71
72 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
73 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
74 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
75 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
76
77 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
78 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
79 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
80 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
81
82
83
84 /*
85 * DMA Controller
86 */
87
88 #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
89 #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
90 #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
91 #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
92 #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
93 #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
94 #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
95 #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
96 #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
97 #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
98 #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
99 #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
100 #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
101 #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
102 #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
103 #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
104
105 #define DCSR(x) __REG2(0x40000000, (x) << 2)
106
107 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
108 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
109 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
110 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
111 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
112 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
113 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
114 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
115
116 #define DINT __REG(0x400000f0) /* DMA Interrupt Register */
117
118 #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
119 #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
120 #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
121 #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
122 #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
123 #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
124 #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
125 #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
126 #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
127 #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
128 #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
129 #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
130 #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
131 #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
132 #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
133 #define DRCMR15 __REG(0x4000013c) /* Reserved */
134 #define DRCMR16 __REG(0x40000140) /* Reserved */
135 #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
136 #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
137 #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
138 #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
139 #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
140 #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
141 #define DRCMR23 __REG(0x4000015c) /* Reserved */
142 #define DRCMR24 __REG(0x40000160) /* Reserved */
143 #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
144 #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
145 #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
146 #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
147 #define DRCMR29 __REG(0x40000174) /* Reserved */
148 #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
149 #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
150 #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
151 #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
152 #define DRCMR34 __REG(0x40000188) /* Reserved */
153 #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
154 #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
155 #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
156 #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
157 #define DRCMR39 __REG(0x4000019C) /* Reserved */
158
159 #define DRCMRRXSADR DRCMR2
160 #define DRCMRTXSADR DRCMR3
161 #define DRCMRRXBTRBR DRCMR4
162 #define DRCMRTXBTTHR DRCMR5
163 #define DRCMRRXFFRBR DRCMR6
164 #define DRCMRTXFFTHR DRCMR7
165 #define DRCMRRXMCDR DRCMR8
166 #define DRCMRRXMODR DRCMR9
167 #define DRCMRTXMODR DRCMR10
168 #define DRCMRRXPCDR DRCMR11
169 #define DRCMRTXPCDR DRCMR12
170 #define DRCMRRXSSDR DRCMR13
171 #define DRCMRTXSSDR DRCMR14
172 #define DRCMRRXICDR DRCMR17
173 #define DRCMRTXICDR DRCMR18
174 #define DRCMRRXSTRBR DRCMR19
175 #define DRCMRTXSTTHR DRCMR20
176 #define DRCMRRXMMC DRCMR21
177 #define DRCMRTXMMC DRCMR22
178
179 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
180 #define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
181
182 #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
183 #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
184 #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
185 #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
186 #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
187 #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
188 #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
189 #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
190 #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
191 #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
192 #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
193 #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
194 #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
195 #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
196 #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
197 #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
198 #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
199 #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
200 #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
201 #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
202 #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
203 #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
204 #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
205 #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
206 #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
207 #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
208 #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
209 #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
210 #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
211 #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
212 #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
213 #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
214 #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
215 #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
216 #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
217 #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
218 #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
219 #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
220 #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
221 #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
222 #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
223 #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
224 #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
225 #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
226 #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
227 #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
228 #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
229 #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
230 #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
231 #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
232 #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
233 #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
234 #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
235 #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
236 #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
237 #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
238 #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
239 #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
240 #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
241 #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
242 #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
243 #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
244 #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
245 #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
246
247 #define DDADR(x) __REG2(0x40000200, (x) << 4)
248 #define DSADR(x) __REG2(0x40000204, (x) << 4)
249 #define DTADR(x) __REG2(0x40000208, (x) << 4)
250 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
251
252 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
253 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
254
255 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
256 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
257 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
258 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
259 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
260 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
261 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
262 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
263 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
264 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
265 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
266 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
267 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
268 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
269
270 /* default combinations */
271 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
272 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
273 #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
274
275
276 /*
277 * UARTs
278 */
279
280 /* Full Function UART (FFUART) */
281 #define FFUART FFRBR
282 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
283 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
284 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
285 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
286 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
287 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
288 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
289 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
290 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
291 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
292 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
293 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
294 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
295
296 /* Bluetooth UART (BTUART) */
297 #define BTUART BTRBR
298 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
299 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
300 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
301 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
302 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
303 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
304 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
305 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
306 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
307 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
308 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
309 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
310 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
311
312 /* Standard UART (STUART) */
313 #define STUART STRBR
314 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
315 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
316 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
317 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
318 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
319 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
320 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
321 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
322 #define STMSR __REG(0x40700018) /* Reserved */
323 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
324 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
325 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
326 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
327
328 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
329 #define IER_UUE (1 << 6) /* UART Unit Enable */
330 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
331 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
332 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
333 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
334 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
335 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
336
337 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
338 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
339 #define IIR_TOD (1 << 3) /* Time Out Detected */
340 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
341 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
342 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
343
344 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
345 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
346 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
347 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
348 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
349 #define FCR_ITL_1 (0)
350 #define FCR_ITL_8 (FCR_ITL1)
351 #define FCR_ITL_16 (FCR_ITL2)
352 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
353
354 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
355 #define LCR_SB (1 << 6) /* Set Break */
356 #define LCR_STKYP (1 << 5) /* Sticky Parity */
357 #define LCR_EPS (1 << 4) /* Even Parity Select */
358 #define LCR_PEN (1 << 3) /* Parity Enable */
359 #define LCR_STB (1 << 2) /* Stop Bit */
360 #define LCR_WLS1 (1 << 1) /* Word Length Select */
361 #define LCR_WLS0 (1 << 0) /* Word Length Select */
362
363 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
364 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
365 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
366 #define LSR_BI (1 << 4) /* Break Interrupt */
367 #define LSR_FE (1 << 3) /* Framing Error */
368 #define LSR_PE (1 << 2) /* Parity Error */
369 #define LSR_OE (1 << 1) /* Overrun Error */
370 #define LSR_DR (1 << 0) /* Data Ready */
371
372 #define MCR_LOOP (1 << 4) */
373 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
374 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
375 #define MCR_RTS (1 << 1) /* Request to Send */
376 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
377
378 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
379 #define MSR_RI (1 << 6) /* Ring Indicator */
380 #define MSR_DSR (1 << 5) /* Data Set Ready */
381 #define MSR_CTS (1 << 4) /* Clear To Send */
382 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
383 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
384 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
385 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
386
387 /*
388 * IrSR (Infrared Selection Register)
389 */
390 #define IrSR_OFFSET 0x20
391
392 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
393 #define IrSR_RXPL_POS_IS_ZERO 0x0
394 #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
395 #define IrSR_TXPL_POS_IS_ZERO 0x0
396 #define IrSR_XMODE_PULSE_1_6 (1<<2)
397 #define IrSR_XMODE_PULSE_3_16 0x0
398 #define IrSR_RCVEIR_IR_MODE (1<<1)
399 #define IrSR_RCVEIR_UART_MODE 0x0
400 #define IrSR_XMITIR_IR_MODE (1<<0)
401 #define IrSR_XMITIR_UART_MODE 0x0
402
403 #define IrSR_IR_RECEIVE_ON (\
404 IrSR_RXPL_NEG_IS_ZERO | \
405 IrSR_TXPL_POS_IS_ZERO | \
406 IrSR_XMODE_PULSE_3_16 | \
407 IrSR_RCVEIR_IR_MODE | \
408 IrSR_XMITIR_UART_MODE)
409
410 #define IrSR_IR_TRANSMIT_ON (\
411 IrSR_RXPL_NEG_IS_ZERO | \
412 IrSR_TXPL_POS_IS_ZERO | \
413 IrSR_XMODE_PULSE_3_16 | \
414 IrSR_RCVEIR_UART_MODE | \
415 IrSR_XMITIR_IR_MODE)
416
417
418 /*
419 * I2C registers
420 */
421
422 #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
423 #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
424 #define ICR __REG(0x40301690) /* I2C Control Register - ICR */
425 #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
426 #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
427
428
429 /*
430 * Serial Audio Controller
431 */
432
433
434 /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
435 * short defines because there is too much chance of namespace collision */
436
437 /*#define SACR0 __REG(0x40400000) / Global Control Register */
438 /*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */
439 /*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
440 /*#define SAIMR __REG(0x40400014) / Serial Audio Interrupt Mask Register */
441 /*#define SAICR __REG(0x40400018) / Serial Audio Interrupt Clear Register */
442 /*#define SADIV __REG(0x40400060) / Audio Clock Divider Register. */
443 /*#define SADR __REG(0x40400080) / Serial Audio Data Register (TX and RX FIFO access Register). */
444
445
446 /*
447 * AC97 Controller registers
448 */
449
450 #define POCR __REG(0x40500000) /* PCM Out Control Register */
451 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
452
453 #define PICR __REG(0x40500004) /* PCM In Control Register */
454 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
455
456 #define MCCR __REG(0x40500008) /* Mic In Control Register */
457 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
458
459 #define GCR __REG(0x4050000C) /* Global Control Register */
460 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
461 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
462 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
463 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
464 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
465 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
466 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
467 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
468 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
469 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
470
471 #define POSR __REG(0x40500010) /* PCM Out Status Register */
472 #define POSR_FIFOE (1 << 4) /* FIFO error */
473
474 #define PISR __REG(0x40500014) /* PCM In Status Register */
475 #define PISR_FIFOE (1 << 4) /* FIFO error */
476
477 #define MCSR __REG(0x40500018) /* Mic In Status Register */
478 #define MCSR_FIFOE (1 << 4) /* FIFO error */
479
480 #define GSR __REG(0x4050001C) /* Global Status Register */
481 #define GSR_CDONE (1 << 19) /* Command Done */
482 #define GSR_SDONE (1 << 18) /* Status Done */
483 #define GSR_RDCS (1 << 15) /* Read Completion Status */
484 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
485 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
486 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
487 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
488 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
489 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
490 #define GSR_PCR (1 << 8) /* Primary Codec Ready */
491 #define GSR_MINT (1 << 7) /* Mic In Interrupt */
492 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
493 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
494 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
495 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
496 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
497
498 #define CAR __REG(0x40500020) /* CODEC Access Register */
499 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */
500
501 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
502 #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
503
504 #define MOCR __REG(0x40500100) /* Modem Out Control Register */
505 #define MOCR_FEIE (1 << 3) /* FIFO Error */
506
507 #define MICR __REG(0x40500108) /* Modem In Control Register */
508 #define MICR_FEIE (1 << 3) /* FIFO Error */
509
510 #define MOSR __REG(0x40500110) /* Modem Out Status Register */
511 #define MOSR_FIFOE (1 << 4) /* FIFO error */
512
513 #define MISR __REG(0x40500118) /* Modem In Status Register */
514 #define MISR_FIFOE (1 << 4) /* FIFO error */
515
516 #define MODR __REG(0x40500140) /* Modem FIFO Data Register */
517
518 #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
519 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
520 #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
521 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
522
523
524 /*
525 * USB Device Controller
526 */
527
528 #define UDCCR __REG(0x40600000) /* UDC Control Register */
529 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
530 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
531 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
532 #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
533 #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
534 #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
535 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
536 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
537 #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
538 #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
539 #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
540 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
541 #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
542 #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
543 #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
544 #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
545 #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
546 #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
547 #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
548 #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
549 #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
550 #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
551 #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
552 #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
553 #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
554 #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
555 #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
556 #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
557 #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
558 #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
559 #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
560 #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
561 #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
562 #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
563 #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
564 #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
565 #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
566 #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
567 #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
568 #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
569 #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
570 #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
571 #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
572 #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
573
574
575 /*
576 * Fast Infrared Communication Port
577 */
578
579 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
580 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
581 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
582 #define ICDR __REG(0x4080000c) /* ICP Data Register */
583 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
584 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
585
586
587 /*
588 * Real Time Clock
589 */
590
591 #define RCNR __REG(0x40900000) /* RTC Count Register */
592 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
593 #define RTSR __REG(0x40900008) /* RTC Status Register */
594 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
595
596 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
597 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
598 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
599 #define RTSR_AL (1 << 0) /* RTC alarm detected */
600
601
602 /*
603 * OS Timer & Match Registers
604 */
605
606 #define OSMR0 __REG(0x40A00000) /* */
607 #define OSMR1 __REG(0x40A00004) /* */
608 #define OSMR2 __REG(0x40A00008) /* */
609 #define OSMR3 __REG(0x40A0000C) /* */
610 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
611 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
612 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
613 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
614
615 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
616 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
617 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
618 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
619
620 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
621
622 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
623 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
624 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
625 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
626
627
628 /*
629 * Pulse Width Modulator
630 */
631
632 #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
633 #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
634 #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
635
636 #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
637 #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
638 #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
639
640
641 /*
642 * Interrupt Controller
643 */
644
645 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
646 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
647 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
648 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
649 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
650 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
651
652
653 /*
654 * General Purpose I/O
655 */
656
657 #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
658 #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
659 #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
660
661 #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
662 #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
663 #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
664
665 #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
666 #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
667 #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
668
669 #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
670 #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
671 #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
672
673 #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
674 #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
675 #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
676
677 #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
678 #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
679 #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
680
681 #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
682 #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
683 #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
684
685 #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
686 #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
687 #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
688 #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
689 #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
690 #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
691
692 /* More handy macros. The argument is a literal GPIO number. */
693
694 #define GPIO_bit(x) (1 << ((x) & 0x1f))
695 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
696 #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
697 #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
698 #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
699 #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
700 #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
701 #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
702 #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
703
704 /* GPIO alternate function assignments */
705
706 #define GPIO1_RST 1 /* reset */
707 #define GPIO6_MMCCLK 6 /* MMC Clock */
708 #define GPIO8_48MHz 7 /* 48 MHz clock output */
709 #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
710 #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
711 #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
712 #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
713 #define GPIO12_32KHz 12 /* 32 kHz out */
714 #define GPIO13_MBGNT 13 /* memory controller grant */
715 #define GPIO14_MBREQ 14 /* alternate bus master request */
716 #define GPIO15_nCS_1 15 /* chip select 1 */
717 #define GPIO16_PWM0 16 /* PWM0 output */
718 #define GPIO17_PWM1 17 /* PWM1 output */
719 #define GPIO18_RDY 18 /* Ext. Bus Ready */
720 #define GPIO19_DREQ1 19 /* External DMA Request */
721 #define GPIO20_DREQ0 20 /* External DMA Request */
722 #define GPIO23_SCLK 23 /* SSP clock */
723 #define GPIO24_SFRM 24 /* SSP Frame */
724 #define GPIO25_STXD 25 /* SSP transmit */
725 #define GPIO26_SRXD 26 /* SSP receive */
726 #define GPIO27_SEXTCLK 27 /* SSP ext_clk */
727 #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
728 #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
729 #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
730 #define GPIO31_SYNC 31 /* AC97/I2S sync */
731 #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
732 #define GPIO33_nCS_5 33 /* chip select 5 */
733 #define GPIO34_FFRXD 34 /* FFUART receive */
734 #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
735 #define GPIO35_FFCTS 35 /* FFUART Clear to send */
736 #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
737 #define GPIO37_FFDSR 37 /* FFUART data set ready */
738 #define GPIO38_FFRI 38 /* FFUART Ring Indicator */
739 #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
740 #define GPIO39_FFTXD 39 /* FFUART transmit data */
741 #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
742 #define GPIO41_FFRTS 41 /* FFUART request to send */
743 #define GPIO42_BTRXD 42 /* BTUART receive data */
744 #define GPIO43_BTTXD 43 /* BTUART transmit data */
745 #define GPIO44_BTCTS 44 /* BTUART clear to send */
746 #define GPIO45_BTRTS 45 /* BTUART request to send */
747 #define GPIO46_ICPRXD 46 /* ICP receive data */
748 #define GPIO46_STRXD 46 /* STD_UART receive data */
749 #define GPIO47_ICPTXD 47 /* ICP transmit data */
750 #define GPIO47_STTXD 47 /* STD_UART transmit data */
751 #define GPIO48_nPOE 48 /* Output Enable for Card Space */
752 #define GPIO49_nPWE 49 /* Write Enable for Card Space */
753 #define GPIO50_nPIOR 50 /* I/O Read for Card Space */
754 #define GPIO51_nPIOW 51 /* I/O Write for Card Space */
755 #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
756 #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
757 #define GPIO53_MMCCLK 53 /* MMC Clock */
758 #define GPIO54_MMCCLK 54 /* MMC Clock */
759 #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
760 #define GPIO55_nPREG 55 /* Card Address bit 26 */
761 #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
762 #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
763 #define GPIO58_LDD_0 58 /* LCD data pin 0 */
764 #define GPIO59_LDD_1 59 /* LCD data pin 1 */
765 #define GPIO60_LDD_2 60 /* LCD data pin 2 */
766 #define GPIO61_LDD_3 61 /* LCD data pin 3 */
767 #define GPIO62_LDD_4 62 /* LCD data pin 4 */
768 #define GPIO63_LDD_5 63 /* LCD data pin 5 */
769 #define GPIO64_LDD_6 64 /* LCD data pin 6 */
770 #define GPIO65_LDD_7 65 /* LCD data pin 7 */
771 #define GPIO66_LDD_8 66 /* LCD data pin 8 */
772 #define GPIO66_MBREQ 66 /* alternate bus master req */
773 #define GPIO67_LDD_9 67 /* LCD data pin 9 */
774 #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
775 #define GPIO68_LDD_10 68 /* LCD data pin 10 */
776 #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
777 #define GPIO69_LDD_11 69 /* LCD data pin 11 */
778 #define GPIO69_MMCCLK 69 /* MMC_CLK */
779 #define GPIO70_LDD_12 70 /* LCD data pin 12 */
780 #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
781 #define GPIO71_LDD_13 71 /* LCD data pin 13 */
782 #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
783 #define GPIO72_LDD_14 72 /* LCD data pin 14 */
784 #define GPIO72_32kHz 72 /* 32 kHz clock */
785 #define GPIO73_LDD_15 73 /* LCD data pin 15 */
786 #define GPIO73_MBGNT 73 /* Memory controller grant */
787 #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
788 #define GPIO75_LCD_LCLK 75 /* LCD line clock */
789 #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
790 #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
791 #define GPIO78_nCS_2 78 /* chip select 2 */
792 #define GPIO79_nCS_3 79 /* chip select 3 */
793 #define GPIO80_nCS_4 80 /* chip select 4 */
794
795 /* GPIO alternate function mode & direction */
796
797 #define GPIO_IN 0x000
798 #define GPIO_OUT 0x080
799 #define GPIO_ALT_FN_1_IN 0x100
800 #define GPIO_ALT_FN_1_OUT 0x180
801 #define GPIO_ALT_FN_2_IN 0x200
802 #define GPIO_ALT_FN_2_OUT 0x280
803 #define GPIO_ALT_FN_3_IN 0x300
804 #define GPIO_ALT_FN_3_OUT 0x380
805 #define GPIO_MD_MASK_NR 0x07f
806 #define GPIO_MD_MASK_DIR 0x080
807 #define GPIO_MD_MASK_FN 0x300
808
809 #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
810 #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
811 #define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT)
812 #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
813 #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
814 #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
815 #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
816 #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
817 #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
818 #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
819 #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
820 #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
821 #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
822 #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
823 #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
824 #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
825 #define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT)
826 #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
827 #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
828 #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
829 #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
830 #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
831 #define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN)
832 #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
833 #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
834 #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
835 #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
836 #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
837 #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
838 #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
839 #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
840 #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
841 #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
842 #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
843 #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
844 #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
845 #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
846 #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
847 #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
848 #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
849 #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
850 #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
851 #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
852 #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
853 #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
854 #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
855 #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
856 #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
857 #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
858 #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
859 #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
860 #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
861 #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
862 #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
863 #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
864 #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
865 #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
866 #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
867 #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
868 #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
869 #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
870 #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
871 #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
872 #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
873 #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
874 #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
875 #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
876 #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
877 #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
878 #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
879 #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
880 #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
881 #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
882 #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
883 #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
884 #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
885 #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
886 #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
887 #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
888 #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
889 #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
890 #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
891 #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
892 #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
893 #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
894 #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
895 #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
896 #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
897 #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
898 #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
899 #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
900 #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
901
902
903 /*
904 * Power Manager
905 */
906
907 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
908 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
909 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
910 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
911 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
912 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
913 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
914 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
915 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
916 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
917 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
918 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
919
920
921 /*
922 * SSP Serial Port Registers
923 */
924
925 #define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */
926 #define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */
927 #define SSSR __REG(0x41000008) /* SSP Status Register */
928 #define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */
929 #define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
930
931
932 /*
933 * MultiMediaCard (MMC) controller
934 */
935
936 #define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
937 #define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
938 #define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
939 #define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
940 #define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
941 #define MMC_RESTO __REG(0x41100014) /* Expected response time out */
942 #define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
943 #define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
944 #define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
945 #define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
946 #define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
947 #define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
948 #define MMC_CMD __REG(0x41100030) /* Index of current command */
949 #define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
950 #define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
951 #define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
952 #define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
953 #define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
954
955
956 /*
957 * Core Clock
958 */
959
960 #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
961 #define CKEN __REG(0x41300004) /* Clock Enable Register */
962 #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
963
964 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
965 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
966 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
967
968 #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
969 #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
970 #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
971 #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
972 #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
973 #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
974 #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
975 #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
976 #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
977 #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
978 #define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
979 #define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
980 #define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
981
982 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
983 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
984
985 #define CCCR_L09 (0x1F)
986 #define CCCR_L27 (0x1)
987 #define CCCR_L32 (0x2)
988 #define CCCR_L36 (0x3)
989 #define CCCR_L40 (0x4)
990 #define CCCR_L45 (0x5)
991
992 #define CCCR_M1 (0x1 << 5)
993 #define CCCR_M2 (0x2 << 5)
994 #define CCCR_M4 (0x3 << 5)
995
996 #define CCCR_N10 (0x2 << 7)
997 #define CCCR_N15 (0x3 << 7)
998 #define CCCR_N20 (0x4 << 7)
999 #define CCCR_N25 (0x5 << 7)
1000 #define CCCR_N30 (0x6 << 7)
1001
1002 /*
1003 * LCD
1004 */
1005
1006 #define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
1007 #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
1008 #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
1009 #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
1010 #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1011 #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1012 #define LCSR __REG(0x44000038) /* LCD Controller Status Register */
1013 #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
1014 #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
1015 #define TMEDCR __REG(0x44000044) /* TMED Control Register */
1016
1017 #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1018 #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1019 #define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
1020 #define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
1021 #define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
1022 #define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
1023 #define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
1024 #define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
1025
1026 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
1027 #define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */
1028 #define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */
1029 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
1030 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
1031 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
1032 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
1033 #define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */
1034 #define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */
1035 #define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
1036 #define LCCR0_DIS (1 << 10) /* LCD Disable */
1037 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
1038 #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
1039 #define LCCR0_PDD_S 12
1040 #define LCCR0_BM (1 << 20) /* Branch mask */
1041 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
1042
1043 #define LCCR3_PCD (0xff) /* Pixel clock divisor */
1044 #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
1045 #define LCCR3_ACB_S 8
1046 #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
1047 #define LCCR3_API_S 16
1048 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */
1049 #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
1050 #define LCCR3_PCP (1 << 22) /* pixel clock polarity */
1051 #define LCCR3_OEP (1 << 23) /* output enable polarity */
1052 #define LCCR3_BPP (7 << 24) /* bits per pixel */
1053 #define LCCR3_BPP_S 24
1054 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
1055
1056 #define LCSR_LDD (1 << 0) /* LCD Disable Done */
1057 #define LCSR_SOF (1 << 1) /* Start of frame */
1058 #define LCSR_BER (1 << 2) /* Bus error */
1059 #define LCSR_ABC (1 << 3) /* AC Bias count */
1060 #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1061 #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1062 #define LCSR_OU (1 << 6) /* output FIFO underrun */
1063 #define LCSR_QD (1 << 7) /* quick disable */
1064 #define LCSR_EOF (1 << 8) /* end of frame */
1065 #define LCSR_BS (1 << 9) /* branch status */
1066 #define LCSR_SINT (1 << 10) /* subsequent interrupt */
1067
1068 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1069
1070 /*
1071 * Memory controller
1072 */
1073
1074 #define MEMC_BASE __REG(0x48000000) /* Base of Memoriy Controller */
1075 #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
1076 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
1077 #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
1078 #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
1079 #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
1080 #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
1081 #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
1082 #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
1083 #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
1084 #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
1085 #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
1086 #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
1087 #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
1088 #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
1089 #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
1090 #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
1091 #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
1092
1093 #define MDCNFG_DE0 0x00000001
1094 #define MDCNFG_DE1 0x00000002
1095 #define MDCNFG_DE2 0x00010000
1096 #define MDCNFG_DE3 0x00020000
1097 #define MDCNFG_DWID0 0x00000004
1098
1099 #define MDREFR_E0PIN 0x00001000
1100 #define MDREFR_K0RUN 0x00002000
1101 #define MDREFR_K0DB2 0x00004000
1102 #define MDREFR_E1PIN 0x00008000
1103 #define MDREFR_K1RUN 0x00010000
1104 #define MDREFR_K1DB2 0x00020000
1105 #define MDREFR_K2RUN 0x00040000
1106 #define MDREFR_K2DB2 0x00080000
1107 #define MDREFR_APD 0x00100000
1108 #define MDREFR_SLFRSH 0x00400000
1109 #define MDREFR_K0FREE 0x00800000
1110 #define MDREFR_K1FREE 0x01000000
1111 #define MDREFR_K2FREE 0x02000000
1112
1113 #define MDCNFG_OFFSET 0x0
1114 #define MDREFR_OFFSET 0x4
1115 #define MSC0_OFFSET 0x8
1116 #define MSC1_OFFSET 0xC
1117 #define MSC2_OFFSET 0x10
1118 #define MECR_OFFSET 0x14
1119 #define SXLCR_OFFSET 0x18
1120 #define SXCNFG_OFFSET 0x1C
1121 #define FLYCNFG_OFFSET 0x20
1122 #define SXMRS_OFFSET 0x24
1123 #define MCMEM0_OFFSET 0x28
1124 #define MCMEM1_OFFSET 0x2C
1125 #define MCATT0_OFFSET 0x30
1126 #define MCATT1_OFFSET 0x34
1127 #define MCIO0_OFFSET 0x38
1128 #define MCIO1_OFFSET 0x3C
1129 #define MDMRS_OFFSET 0x40
1130
1131
1132
1133
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