include/asm-i386/cpufeature.h

   1 /*
   2  * cpufeature.h
   3  *
   4  * Defines x86 CPU feature bits
   5  */
   6
   7 #ifndef __ASM_I386_CPUFEATURE_H
   8 #define __ASM_I386_CPUFEATURE_H
   9
  10 #include <linux/bitops.h>
  11
  12 #define NCAPINTS        7       /* N 32-bit words worth of info */
  13
  14 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
  15 #define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
  16 #define X86_FEATURE_VME         (0*32+ 1) /* Virtual Mode Extensions */
  17 #define X86_FEATURE_DE          (0*32+ 2) /* Debugging Extensions */
  18 #define X86_FEATURE_PSE         (0*32+ 3) /* Page Size Extensions */
  19 #define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
  20 #define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
  21 #define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
  22 #define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Architecture */
  23 #define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
  24 #define X86_FEATURE_APIC        (0*32+ 9) /* Onboard APIC */
  25 #define X86_FEATURE_SEP         (0*32+11) /* SYSENTER/SYSEXIT */
  26 #define X86_FEATURE_MTRR        (0*32+12) /* Memory Type Range Registers */
  27 #define X86_FEATURE_PGE         (0*32+13) /* Page Global Enable */
  28 #define X86_FEATURE_MCA         (0*32+14) /* Machine Check Architecture */
  29 #define X86_FEATURE_CMOV        (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
  30 #define X86_FEATURE_PAT         (0*32+16) /* Page Attribute Table */
  31 #define X86_FEATURE_PSE36       (0*32+17) /* 36-bit PSEs */
  32 #define X86_FEATURE_PN          (0*32+18) /* Processor serial number */
  33 #define X86_FEATURE_CLFLSH      (0*32+19) /* Supports the CLFLUSH instruction */
  34 #define X86_FEATURE_DTES        (0*32+21) /* Debug Trace Store */
  35 #define X86_FEATURE_ACPI        (0*32+22) /* ACPI via MSR */
  36 #define X86_FEATURE_MMX         (0*32+23) /* Multimedia Extensions */
  37 #define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
  38                                           /* of FPU context), and CR4.OSFXSR available */
  39 #define X86_FEATURE_XMM         (0*32+25) /* Streaming SIMD Extensions */
  40 #define X86_FEATURE_XMM2        (0*32+26) /* Streaming SIMD Extensions-2 */
  41 #define X86_FEATURE_SELFSNOOP   (0*32+27) /* CPU self snoop */
  42 #define X86_FEATURE_HT          (0*32+28) /* Hyper-Threading */
  43 #define X86_FEATURE_ACC         (0*32+29) /* Automatic clock control */
  44 #define X86_FEATURE_IA64        (0*32+30) /* IA-64 processor */
  45
  46 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
  47 /* Don't duplicate feature flags which are redundant with Intel! */
  48 #define X86_FEATURE_SYSCALL     (1*32+11) /* SYSCALL/SYSRET */
  49 #define X86_FEATURE_MP          (1*32+19) /* MP Capable. */
  50 #define X86_FEATURE_NX          (1*32+20) /* Execute Disable */
  51 #define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
  52 #define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
  53 #define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
  54 #define X86_FEATURE_3DNOW       (1*32+31) /* 3DNow! */
  55
  56 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
  57 #define X86_FEATURE_RECOVERY    (2*32+ 0) /* CPU in recovery mode */
  58 #define X86_FEATURE_LONGRUN     (2*32+ 1) /* Longrun power control */
  59 #define X86_FEATURE_LRTI        (2*32+ 3) /* LongRun table interface */
  60
  61 /* Other features, Linux-defined mapping, word 3 */
  62 /* This range is used for feature bits which conflict or are synthesized */
  63 #define X86_FEATURE_CXMMX       (3*32+ 0) /* Cyrix MMX extensions */
  64 #define X86_FEATURE_K6_MTRR     (3*32+ 1) /* AMD K6 nonstandard MTRRs */
  65 #define X86_FEATURE_CYRIX_ARR   (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
  66 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
  67 /* cpu types for specific tunings: */
  68 #define X86_FEATURE_K8          (3*32+ 4) /* Opteron, Athlon64 */
  69 #define X86_FEATURE_K7          (3*32+ 5) /* Athlon */
  70 #define X86_FEATURE_P3          (3*32+ 6) /* P3 */
  71 #define X86_FEATURE_P4          (3*32+ 7) /* P4 */
  72
  73 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
  74 #define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
  75 #define X86_FEATURE_MWAIT       (4*32+ 3) /* Monitor/Mwait support */
  76 #define X86_FEATURE_DSCPL       (4*32+ 4) /* CPL Qualified Debug Store */
  77 #define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
  78 #define X86_FEATURE_TM2         (4*32+ 8) /* Thermal Monitor 2 */
  79 #define X86_FEATURE_CID         (4*32+10) /* Context ID */
  80 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
  81 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
  82
  83 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
  84 #define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
  85 #define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* on-CPU RNG enabled */
  86 #define X86_FEATURE_XCRYPT      (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
  87 #define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* on-CPU crypto enabled */
  88
  89 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
  90 #define X86_FEATURE_LAHF_LM     (5*32+ 0) /* LAHF/SAHF in long mode */
  91 #define X86_FEATURE_CMP_LEGACY  (5*32+ 1) /* If yes HyperThreading not valid */
  92
  93 #define cpu_has(c, bit)         test_bit(bit, (c)->x86_capability)
  94 #define boot_cpu_has(bit)       test_bit(bit, boot_cpu_data.x86_capability)
  95
  96 #define cpu_has_fpu             boot_cpu_has(X86_FEATURE_FPU)
  97 #define cpu_has_vme             boot_cpu_has(X86_FEATURE_VME)
  98 #define cpu_has_de              boot_cpu_has(X86_FEATURE_DE)
  99 #define cpu_has_pse             boot_cpu_has(X86_FEATURE_PSE)
 100 #define cpu_has_tsc             boot_cpu_has(X86_FEATURE_TSC)
 101 #define cpu_has_pae             boot_cpu_has(X86_FEATURE_PAE)
 102 #define cpu_has_pge             boot_cpu_has(X86_FEATURE_PGE)
 103 #define cpu_has_apic            boot_cpu_has(X86_FEATURE_APIC)
 104 #define cpu_has_sep             boot_cpu_has(X86_FEATURE_SEP)
 105 #define cpu_has_mtrr            boot_cpu_has(X86_FEATURE_MTRR)
 106 #define cpu_has_mmx             boot_cpu_has(X86_FEATURE_MMX)
 107 #define cpu_has_fxsr            boot_cpu_has(X86_FEATURE_FXSR)
 108 #define cpu_has_xmm             boot_cpu_has(X86_FEATURE_XMM)
 109 #define cpu_has_xmm2            boot_cpu_has(X86_FEATURE_XMM2)
 110 #define cpu_has_xmm3            boot_cpu_has(X86_FEATURE_XMM3)
 111 #define cpu_has_ht              boot_cpu_has(X86_FEATURE_HT)
 112 #define cpu_has_mp              boot_cpu_has(X86_FEATURE_MP)
 113 #define cpu_has_nx              boot_cpu_has(X86_FEATURE_NX)
 114 #define cpu_has_k6_mtrr         boot_cpu_has(X86_FEATURE_K6_MTRR)
 115 #define cpu_has_cyrix_arr       boot_cpu_has(X86_FEATURE_CYRIX_ARR)
 116 #define cpu_has_centaur_mcr     boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
 117 #define cpu_has_xstore          boot_cpu_has(X86_FEATURE_XSTORE)
 118 #define cpu_has_xstore_enabled  boot_cpu_has(X86_FEATURE_XSTORE_EN)
 119 #define cpu_has_xcrypt          boot_cpu_has(X86_FEATURE_XCRYPT)
 120 #define cpu_has_xcrypt_enabled  boot_cpu_has(X86_FEATURE_XCRYPT_EN)
 121
 122 #endif /* __ASM_I386_CPUFEATURE_H */
 123
 124 /*
 125  * Local Variables:
 126  * mode:c
 127  * comment-column:42
 128  * End:
 129  */