include/asm-m68k/m5445x.h

   1 /*
   2  * MCF5445x Internal Memory Map
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __MCF5445X__
  27 #define __MCF5445X__
  28
  29 /*********************************************************************
  30 * Cross-bar switch (XBS)
  31 *********************************************************************/
  32
  33 /* Bit definitions and macros for PRS group */
  34 #define XBS_PRS_M0(x)                   (((x)&0x00000007))      /* Core */
  35 #define XBS_PRS_M1(x)                   (((x)&0x00000007)<<4)   /* eDMA */
  36 #define XBS_PRS_M2(x)                   (((x)&0x00000007)<<8)   /* FEC0 */
  37 #define XBS_PRS_M3(x)                   (((x)&0x00000007)<<12)  /* FEC1 */
  38 #define XBS_PRS_M5(x)                   (((x)&0x00000007)<<20)  /* PCI controller */
  39 #define XBS_PRS_M6(x)                   (((x)&0x00000007)<<24)  /* USB OTG */
  40 #define XBS_PRS_M7(x)                   (((x)&0x00000007)<<28)  /* Serial Boot */
  41
  42 /* Bit definitions and macros for CRS group */
  43 #define XBS_CRS_PARK(x)                 (((x)&0x00000007))      /* Master parking ctrl */
  44 #define XBS_CRS_PCTL(x)                 (((x)&0x00000003)<<4)   /* Parking mode ctrl */
  45 #define XBS_CRS_ARB                     (0x00000100)    /* Arbitration Mode */
  46 #define XBS_CRS_RO                      (0x80000000)    /* Read Only */
  47
  48 #define XBS_CRS_PCTL_PARK_FIELD         (0)
  49 #define XBS_CRS_PCTL_PARK_ON_LAST       (1)
  50 #define XBS_CRS_PCTL_PARK_NONE          (2)
  51 #define XBS_CRS_PCTL_PARK_CORE          (0)
  52 #define XBS_CRS_PCTL_PARK_EDMA          (1)
  53 #define XBS_CRS_PCTL_PARK_FEC0          (2)
  54 #define XBS_CRS_PCTL_PARK_FEC1          (3)
  55 #define XBS_CRS_PCTL_PARK_PCI           (5)
  56 #define XBS_CRS_PCTL_PARK_USB           (6)
  57 #define XBS_CRS_PCTL_PARK_SBF           (7)
  58
  59 /*********************************************************************
  60 * FlexBus Chip Selects (FBCS)
  61 *********************************************************************/
  62
  63 /* Bit definitions and macros for CSAR group */
  64 #define FBCS_CSAR_BA(x)                 ((x)&0xFFFF0000)
  65
  66 /* Bit definitions and macros for CSMR group */
  67 #define FBCS_CSMR_V                     (0x00000001)    /* Valid bit */
  68 #define FBCS_CSMR_WP                    (0x00000100)    /* Write protect */
  69 #define FBCS_CSMR_BAM(x)                (((x)&0x0000FFFF)<<16)  /* Base address mask */
  70 #define FBCS_CSMR_BAM_4G                (0xFFFF0000)
  71 #define FBCS_CSMR_BAM_2G                (0x7FFF0000)
  72 #define FBCS_CSMR_BAM_1G                (0x3FFF0000)
  73 #define FBCS_CSMR_BAM_1024M             (0x3FFF0000)
  74 #define FBCS_CSMR_BAM_512M              (0x1FFF0000)
  75 #define FBCS_CSMR_BAM_256M              (0x0FFF0000)
  76 #define FBCS_CSMR_BAM_128M              (0x07FF0000)
  77 #define FBCS_CSMR_BAM_64M               (0x03FF0000)
  78 #define FBCS_CSMR_BAM_32M               (0x01FF0000)
  79 #define FBCS_CSMR_BAM_16M               (0x00FF0000)
  80 #define FBCS_CSMR_BAM_8M                (0x007F0000)
  81 #define FBCS_CSMR_BAM_4M                (0x003F0000)
  82 #define FBCS_CSMR_BAM_2M                (0x001F0000)
  83 #define FBCS_CSMR_BAM_1M                (0x000F0000)
  84 #define FBCS_CSMR_BAM_1024K             (0x000F0000)
  85 #define FBCS_CSMR_BAM_512K              (0x00070000)
  86 #define FBCS_CSMR_BAM_256K              (0x00030000)
  87 #define FBCS_CSMR_BAM_128K              (0x00010000)
  88 #define FBCS_CSMR_BAM_64K               (0x00000000)
  89
  90 /* Bit definitions and macros for CSCR group */
  91 #define FBCS_CSCR_BSTW                  (0x00000008)    /* Burst-write enable */
  92 #define FBCS_CSCR_BSTR                  (0x00000010)    /* Burst-read enable */
  93 #define FBCS_CSCR_BEM                   (0x00000020)    /* Byte-enable mode */
  94 #define FBCS_CSCR_PS(x)                 (((x)&0x00000003)<<6)   /* Port size */
  95 #define FBCS_CSCR_AA                    (0x00000100)    /* Auto-acknowledge */
  96 #define FBCS_CSCR_WS(x)                 (((x)&0x0000003F)<<10)  /* Wait states */
  97 #define FBCS_CSCR_WRAH(x)               (((x)&0x00000003)<<16)  /* Write address hold or deselect */
  98 #define FBCS_CSCR_RDAH(x)               (((x)&0x00000003)<<18)  /* Read address hold or deselect */
  99 #define FBCS_CSCR_ASET(x)               (((x)&0x00000003)<<20)  /* Address setup */
 100 #define FBCS_CSCR_SWSEN                 (0x00800000)    /* Secondary wait state enable */
 101 #define FBCS_CSCR_SWS(x)                (((x)&0x0000003F)<<26)  /* Secondary wait states */
 102
 103 #define FBCS_CSCR_PS_8                  (0x00000040)
 104 #define FBCS_CSCR_PS_16                 (0x00000080)
 105 #define FBCS_CSCR_PS_32                 (0x00000000)
 106
 107 /*********************************************************************
 108 * Interrupt Controller (INTC)
 109 *********************************************************************/
 110 #define INT0_LO_RSVD0                   (0)
 111 #define INT0_LO_EPORT1                  (1)
 112 #define INT0_LO_EPORT2                  (2)
 113 #define INT0_LO_EPORT3                  (3)
 114 #define INT0_LO_EPORT4                  (4)
 115 #define INT0_LO_EPORT5                  (5)
 116 #define INT0_LO_EPORT6                  (6)
 117 #define INT0_LO_EPORT7                  (7)
 118 #define INT0_LO_EDMA_00                 (8)
 119 #define INT0_LO_EDMA_01                 (9)
 120 #define INT0_LO_EDMA_02                 (10)
 121 #define INT0_LO_EDMA_03                 (11)
 122 #define INT0_LO_EDMA_04                 (12)
 123 #define INT0_LO_EDMA_05                 (13)
 124 #define INT0_LO_EDMA_06                 (14)
 125 #define INT0_LO_EDMA_07                 (15)
 126 #define INT0_LO_EDMA_08                 (16)
 127 #define INT0_LO_EDMA_09                 (17)
 128 #define INT0_LO_EDMA_10                 (18)
 129 #define INT0_LO_EDMA_11                 (19)
 130 #define INT0_LO_EDMA_12                 (20)
 131 #define INT0_LO_EDMA_13                 (21)
 132 #define INT0_LO_EDMA_14                 (22)
 133 #define INT0_LO_EDMA_15                 (23)
 134 #define INT0_LO_EDMA_ERR                (24)
 135 #define INT0_LO_SCM                     (25)
 136 #define INT0_LO_UART0                   (26)
 137 #define INT0_LO_UART1                   (27)
 138 #define INT0_LO_UART2                   (28)
 139 #define INT0_LO_RSVD1                   (29)
 140 #define INT0_LO_I2C                     (30)
 141 #define INT0_LO_QSPI                    (31)
 142 #define INT0_HI_DTMR0                   (32)
 143 #define INT0_HI_DTMR1                   (33)
 144 #define INT0_HI_DTMR2                   (34)
 145 #define INT0_HI_DTMR3                   (35)
 146 #define INT0_HI_FEC0_TXF                (36)
 147 #define INT0_HI_FEC0_TXB                (37)
 148 #define INT0_HI_FEC0_UN                 (38)
 149 #define INT0_HI_FEC0_RL                 (39)
 150 #define INT0_HI_FEC0_RXF                (40)
 151 #define INT0_HI_FEC0_RXB                (41)
 152 #define INT0_HI_FEC0_MII                (42)
 153 #define INT0_HI_FEC0_LC                 (43)
 154 #define INT0_HI_FEC0_HBERR              (44)
 155 #define INT0_HI_FEC0_GRA                (45)
 156 #define INT0_HI_FEC0_EBERR              (46)
 157 #define INT0_HI_FEC0_BABT               (47)
 158 #define INT0_HI_FEC0_BABR               (48)
 159 #define INT0_HI_FEC1_TXF                (49)
 160 #define INT0_HI_FEC1_TXB                (50)
 161 #define INT0_HI_FEC1_UN                 (51)
 162 #define INT0_HI_FEC1_RL                 (52)
 163 #define INT0_HI_FEC1_RXF                (53)
 164 #define INT0_HI_FEC1_RXB                (54)
 165 #define INT0_HI_FEC1_MII                (55)
 166 #define INT0_HI_FEC1_LC                 (56)
 167 #define INT0_HI_FEC1_HBERR              (57)
 168 #define INT0_HI_FEC1_GRA                (58)
 169 #define INT0_HI_FEC1_EBERR              (59)
 170 #define INT0_HI_FEC1_BABT               (60)
 171 #define INT0_HI_FEC1_BABR               (61)
 172 #define INT0_HI_SCMIR                   (62)
 173 #define INT0_HI_RTC_ISR                 (63)
 174
 175 #define INT1_HI_DSPI_EOQF               (33)
 176 #define INT1_HI_DSPI_TFFF               (34)
 177 #define INT1_HI_DSPI_TCF                (35)
 178 #define INT1_HI_DSPI_TFUF               (36)
 179 #define INT1_HI_DSPI_RFDF               (37)
 180 #define INT1_HI_DSPI_RFOF               (38)
 181 #define INT1_HI_DSPI_RFOF_TFUF          (39)
 182 #define INT1_HI_RNG_EI                  (40)
 183 #define INT1_HI_PIT0_PIF                (43)
 184 #define INT1_HI_PIT1_PIF                (44)
 185 #define INT1_HI_PIT2_PIF                (45)
 186 #define INT1_HI_PIT3_PIF                (46)
 187 #define INT1_HI_USBOTG_USBSTS           (47)
 188 #define INT1_HI_SSI_ISR                 (49)
 189 #define INT1_HI_CCM_UOCSR               (53)
 190 #define INT1_HI_ATA_ISR                 (54)
 191 #define INT1_HI_PCI_SCR                 (55)
 192 #define INT1_HI_PCI_ASR                 (56)
 193 #define INT1_HI_PLL_LOCKS               (57)
 194
 195 /* Bit definitions and macros for IPRH */
 196 #define INTC_IPRH_INT32                 (0x00000001)
 197 #define INTC_IPRH_INT33                 (0x00000002)
 198 #define INTC_IPRH_INT34                 (0x00000004)
 199 #define INTC_IPRH_INT35                 (0x00000008)
 200 #define INTC_IPRH_INT36                 (0x00000010)
 201 #define INTC_IPRH_INT37                 (0x00000020)
 202 #define INTC_IPRH_INT38                 (0x00000040)
 203 #define INTC_IPRH_INT39                 (0x00000080)
 204 #define INTC_IPRH_INT40                 (0x00000100)
 205 #define INTC_IPRH_INT41                 (0x00000200)
 206 #define INTC_IPRH_INT42                 (0x00000400)
 207 #define INTC_IPRH_INT43                 (0x00000800)
 208 #define INTC_IPRH_INT44                 (0x00001000)
 209 #define INTC_IPRH_INT45                 (0x00002000)
 210 #define INTC_IPRH_INT46                 (0x00004000)
 211 #define INTC_IPRH_INT47                 (0x00008000)
 212 #define INTC_IPRH_INT48                 (0x00010000)
 213 #define INTC_IPRH_INT49                 (0x00020000)
 214 #define INTC_IPRH_INT50                 (0x00040000)
 215 #define INTC_IPRH_INT51                 (0x00080000)
 216 #define INTC_IPRH_INT52                 (0x00100000)
 217 #define INTC_IPRH_INT53                 (0x00200000)
 218 #define INTC_IPRH_INT54                 (0x00400000)
 219 #define INTC_IPRH_INT55                 (0x00800000)
 220 #define INTC_IPRH_INT56                 (0x01000000)
 221 #define INTC_IPRH_INT57                 (0x02000000)
 222 #define INTC_IPRH_INT58                 (0x04000000)
 223 #define INTC_IPRH_INT59                 (0x08000000)
 224 #define INTC_IPRH_INT60                 (0x10000000)
 225 #define INTC_IPRH_INT61                 (0x20000000)
 226 #define INTC_IPRH_INT62                 (0x40000000)
 227 #define INTC_IPRH_INT63                 (0x80000000)
 228
 229 /* Bit definitions and macros for IPRL */
 230 #define INTC_IPRL_INT0                  (0x00000001)
 231 #define INTC_IPRL_INT1                  (0x00000002)
 232 #define INTC_IPRL_INT2                  (0x00000004)
 233 #define INTC_IPRL_INT3                  (0x00000008)
 234 #define INTC_IPRL_INT4                  (0x00000010)
 235 #define INTC_IPRL_INT5                  (0x00000020)
 236 #define INTC_IPRL_INT6                  (0x00000040)
 237 #define INTC_IPRL_INT7                  (0x00000080)
 238 #define INTC_IPRL_INT8                  (0x00000100)
 239 #define INTC_IPRL_INT9                  (0x00000200)
 240 #define INTC_IPRL_INT10                 (0x00000400)
 241 #define INTC_IPRL_INT11                 (0x00000800)
 242 #define INTC_IPRL_INT12                 (0x00001000)
 243 #define INTC_IPRL_INT13                 (0x00002000)
 244 #define INTC_IPRL_INT14                 (0x00004000)
 245 #define INTC_IPRL_INT15                 (0x00008000)
 246 #define INTC_IPRL_INT16                 (0x00010000)
 247 #define INTC_IPRL_INT17                 (0x00020000)
 248 #define INTC_IPRL_INT18                 (0x00040000)
 249 #define INTC_IPRL_INT19                 (0x00080000)
 250 #define INTC_IPRL_INT20                 (0x00100000)
 251 #define INTC_IPRL_INT21                 (0x00200000)
 252 #define INTC_IPRL_INT22                 (0x00400000)
 253 #define INTC_IPRL_INT23                 (0x00800000)
 254 #define INTC_IPRL_INT24                 (0x01000000)
 255 #define INTC_IPRL_INT25                 (0x02000000)
 256 #define INTC_IPRL_INT26                 (0x04000000)
 257 #define INTC_IPRL_INT27                 (0x08000000)
 258 #define INTC_IPRL_INT28                 (0x10000000)
 259 #define INTC_IPRL_INT29                 (0x20000000)
 260 #define INTC_IPRL_INT30                 (0x40000000)
 261 #define INTC_IPRL_INT31                 (0x80000000)
 262
 263 /* Bit definitions and macros for IMRH */
 264 #define INTC_IMRH_INT_MASK32            (0x00000001)
 265 #define INTC_IMRH_INT_MASK33            (0x00000002)
 266 #define INTC_IMRH_INT_MASK34            (0x00000004)
 267 #define INTC_IMRH_INT_MASK35            (0x00000008)
 268 #define INTC_IMRH_INT_MASK36            (0x00000010)
 269 #define INTC_IMRH_INT_MASK37            (0x00000020)
 270 #define INTC_IMRH_INT_MASK38            (0x00000040)
 271 #define INTC_IMRH_INT_MASK39            (0x00000080)
 272 #define INTC_IMRH_INT_MASK40            (0x00000100)
 273 #define INTC_IMRH_INT_MASK41            (0x00000200)
 274 #define INTC_IMRH_INT_MASK42            (0x00000400)
 275 #define INTC_IMRH_INT_MASK43            (0x00000800)
 276 #define INTC_IMRH_INT_MASK44            (0x00001000)
 277 #define INTC_IMRH_INT_MASK45            (0x00002000)
 278 #define INTC_IMRH_INT_MASK46            (0x00004000)
 279 #define INTC_IMRH_INT_MASK47            (0x00008000)
 280 #define INTC_IMRH_INT_MASK48            (0x00010000)
 281 #define INTC_IMRH_INT_MASK49            (0x00020000)
 282 #define INTC_IMRH_INT_MASK50            (0x00040000)
 283 #define INTC_IMRH_INT_MASK51            (0x00080000)
 284 #define INTC_IMRH_INT_MASK52            (0x00100000)
 285 #define INTC_IMRH_INT_MASK53            (0x00200000)
 286 #define INTC_IMRH_INT_MASK54            (0x00400000)
 287 #define INTC_IMRH_INT_MASK55            (0x00800000)
 288 #define INTC_IMRH_INT_MASK56            (0x01000000)
 289 #define INTC_IMRH_INT_MASK57            (0x02000000)
 290 #define INTC_IMRH_INT_MASK58            (0x04000000)
 291 #define INTC_IMRH_INT_MASK59            (0x08000000)
 292 #define INTC_IMRH_INT_MASK60            (0x10000000)
 293 #define INTC_IMRH_INT_MASK61            (0x20000000)
 294 #define INTC_IMRH_INT_MASK62            (0x40000000)
 295 #define INTC_IMRH_INT_MASK63            (0x80000000)
 296
 297 /* Bit definitions and macros for IMRL */
 298 #define INTC_IMRL_INT_MASK0             (0x00000001)
 299 #define INTC_IMRL_INT_MASK1             (0x00000002)
 300 #define INTC_IMRL_INT_MASK2             (0x00000004)
 301 #define INTC_IMRL_INT_MASK3             (0x00000008)
 302 #define INTC_IMRL_INT_MASK4             (0x00000010)
 303 #define INTC_IMRL_INT_MASK5             (0x00000020)
 304 #define INTC_IMRL_INT_MASK6             (0x00000040)
 305 #define INTC_IMRL_INT_MASK7             (0x00000080)
 306 #define INTC_IMRL_INT_MASK8             (0x00000100)
 307 #define INTC_IMRL_INT_MASK9             (0x00000200)
 308 #define INTC_IMRL_INT_MASK10            (0x00000400)
 309 #define INTC_IMRL_INT_MASK11            (0x00000800)
 310 #define INTC_IMRL_INT_MASK12            (0x00001000)
 311 #define INTC_IMRL_INT_MASK13            (0x00002000)
 312 #define INTC_IMRL_INT_MASK14            (0x00004000)
 313 #define INTC_IMRL_INT_MASK15            (0x00008000)
 314 #define INTC_IMRL_INT_MASK16            (0x00010000)
 315 #define INTC_IMRL_INT_MASK17            (0x00020000)
 316 #define INTC_IMRL_INT_MASK18            (0x00040000)
 317 #define INTC_IMRL_INT_MASK19            (0x00080000)
 318 #define INTC_IMRL_INT_MASK20            (0x00100000)
 319 #define INTC_IMRL_INT_MASK21            (0x00200000)
 320 #define INTC_IMRL_INT_MASK22            (0x00400000)
 321 #define INTC_IMRL_INT_MASK23            (0x00800000)
 322 #define INTC_IMRL_INT_MASK24            (0x01000000)
 323 #define INTC_IMRL_INT_MASK25            (0x02000000)
 324 #define INTC_IMRL_INT_MASK26            (0x04000000)
 325 #define INTC_IMRL_INT_MASK27            (0x08000000)
 326 #define INTC_IMRL_INT_MASK28            (0x10000000)
 327 #define INTC_IMRL_INT_MASK29            (0x20000000)
 328 #define INTC_IMRL_INT_MASK30            (0x40000000)
 329 #define INTC_IMRL_INT_MASK31            (0x80000000)
 330
 331 /* Bit definitions and macros for INTFRCH */
 332 #define INTC_INTFRCH_INTFRC32           (0x00000001)
 333 #define INTC_INTFRCH_INTFRC33           (0x00000002)
 334 #define INTC_INTFRCH_INTFRC34           (0x00000004)
 335 #define INTC_INTFRCH_INTFRC35           (0x00000008)
 336 #define INTC_INTFRCH_INTFRC36           (0x00000010)
 337 #define INTC_INTFRCH_INTFRC37           (0x00000020)
 338 #define INTC_INTFRCH_INTFRC38           (0x00000040)
 339 #define INTC_INTFRCH_INTFRC39           (0x00000080)
 340 #define INTC_INTFRCH_INTFRC40           (0x00000100)
 341 #define INTC_INTFRCH_INTFRC41           (0x00000200)
 342 #define INTC_INTFRCH_INTFRC42           (0x00000400)
 343 #define INTC_INTFRCH_INTFRC43           (0x00000800)
 344 #define INTC_INTFRCH_INTFRC44           (0x00001000)
 345 #define INTC_INTFRCH_INTFRC45           (0x00002000)
 346 #define INTC_INTFRCH_INTFRC46           (0x00004000)
 347 #define INTC_INTFRCH_INTFRC47           (0x00008000)
 348 #define INTC_INTFRCH_INTFRC48           (0x00010000)
 349 #define INTC_INTFRCH_INTFRC49           (0x00020000)
 350 #define INTC_INTFRCH_INTFRC50           (0x00040000)
 351 #define INTC_INTFRCH_INTFRC51           (0x00080000)
 352 #define INTC_INTFRCH_INTFRC52           (0x00100000)
 353 #define INTC_INTFRCH_INTFRC53           (0x00200000)
 354 #define INTC_INTFRCH_INTFRC54           (0x00400000)
 355 #define INTC_INTFRCH_INTFRC55           (0x00800000)
 356 #define INTC_INTFRCH_INTFRC56           (0x01000000)
 357 #define INTC_INTFRCH_INTFRC57           (0x02000000)
 358 #define INTC_INTFRCH_INTFRC58           (0x04000000)
 359 #define INTC_INTFRCH_INTFRC59           (0x08000000)
 360 #define INTC_INTFRCH_INTFRC60           (0x10000000)
 361 #define INTC_INTFRCH_INTFRC61           (0x20000000)
 362 #define INTC_INTFRCH_INTFRC62           (0x40000000)
 363 #define INTC_INTFRCH_INTFRC63           (0x80000000)
 364
 365 /* Bit definitions and macros for INTFRCL */
 366 #define INTC_INTFRCL_INTFRC0            (0x00000001)
 367 #define INTC_INTFRCL_INTFRC1            (0x00000002)
 368 #define INTC_INTFRCL_INTFRC2            (0x00000004)
 369 #define INTC_INTFRCL_INTFRC3            (0x00000008)
 370 #define INTC_INTFRCL_INTFRC4            (0x00000010)
 371 #define INTC_INTFRCL_INTFRC5            (0x00000020)
 372 #define INTC_INTFRCL_INTFRC6            (0x00000040)
 373 #define INTC_INTFRCL_INTFRC7            (0x00000080)
 374 #define INTC_INTFRCL_INTFRC8            (0x00000100)
 375 #define INTC_INTFRCL_INTFRC9            (0x00000200)
 376 #define INTC_INTFRCL_INTFRC10           (0x00000400)
 377 #define INTC_INTFRCL_INTFRC11           (0x00000800)
 378 #define INTC_INTFRCL_INTFRC12           (0x00001000)
 379 #define INTC_INTFRCL_INTFRC13           (0x00002000)
 380 #define INTC_INTFRCL_INTFRC14           (0x00004000)
 381 #define INTC_INTFRCL_INTFRC15           (0x00008000)
 382 #define INTC_INTFRCL_INTFRC16           (0x00010000)
 383 #define INTC_INTFRCL_INTFRC17           (0x00020000)
 384 #define INTC_INTFRCL_INTFRC18           (0x00040000)
 385 #define INTC_INTFRCL_INTFRC19           (0x00080000)
 386 #define INTC_INTFRCL_INTFRC20           (0x00100000)
 387 #define INTC_INTFRCL_INTFRC21           (0x00200000)
 388 #define INTC_INTFRCL_INTFRC22           (0x00400000)
 389 #define INTC_INTFRCL_INTFRC23           (0x00800000)
 390 #define INTC_INTFRCL_INTFRC24           (0x01000000)
 391 #define INTC_INTFRCL_INTFRC25           (0x02000000)
 392 #define INTC_INTFRCL_INTFRC26           (0x04000000)
 393 #define INTC_INTFRCL_INTFRC27           (0x08000000)
 394 #define INTC_INTFRCL_INTFRC28           (0x10000000)
 395 #define INTC_INTFRCL_INTFRC29           (0x20000000)
 396 #define INTC_INTFRCL_INTFRC30           (0x40000000)
 397 #define INTC_INTFRCL_INTFRC31           (0x80000000)
 398
 399 /* Bit definitions and macros for ICONFIG */
 400 #define INTC_ICONFIG_EMASK              (0x0020)
 401 #define INTC_ICONFIG_ELVLPRI1           (0x0200)
 402 #define INTC_ICONFIG_ELVLPRI2           (0x0400)
 403 #define INTC_ICONFIG_ELVLPRI3           (0x0800)
 404 #define INTC_ICONFIG_ELVLPRI4           (0x1000)
 405 #define INTC_ICONFIG_ELVLPRI5           (0x2000)
 406 #define INTC_ICONFIG_ELVLPRI6           (0x4000)
 407 #define INTC_ICONFIG_ELVLPRI7           (0x8000)
 408
 409 /* Bit definitions and macros for SIMR */
 410 #define INTC_SIMR_SIMR(x)               (((x)&0x7F))
 411
 412 /* Bit definitions and macros for CIMR */
 413 #define INTC_CIMR_CIMR(x)               (((x)&0x7F))
 414
 415 /* Bit definitions and macros for CLMASK */
 416 #define INTC_CLMASK_CLMASK(x)           (((x)&0x0F))
 417
 418 /* Bit definitions and macros for SLMASK */
 419 #define INTC_SLMASK_SLMASK(x)           (((x)&0x0F))
 420
 421 /* Bit definitions and macros for ICR group */
 422 #define INTC_ICR_IL(x)                  (((x)&0x07))
 423
 424 /*********************************************************************
 425 * DMA Serial Peripheral Interface (DSPI)
 426 *********************************************************************/
 427
 428 /* Bit definitions and macros for DMCR */
 429 #define DSPI_DMCR_HALT                  (0x00000001)
 430 #define DSPI_DMCR_SMPL_PT(x)            (((x)&0x00000003)<<8)
 431 #define DSPI_DMCR_CRXF                  (0x00000400)
 432 #define DSPI_DMCR_CTXF                  (0x00000800)
 433 #define DSPI_DMCR_DRXF                  (0x00001000)
 434 #define DSPI_DMCR_DTXF                  (0x00002000)
 435 #define DSPI_DMCR_CSIS0                 (0x00010000)
 436 #define DSPI_DMCR_CSIS2                 (0x00040000)
 437 #define DSPI_DMCR_CSIS3                 (0x00080000)
 438 #define DSPI_DMCR_CSIS5                 (0x00200000)
 439 #define DSPI_DMCR_ROOE                  (0x01000000)
 440 #define DSPI_DMCR_PCSSE                 (0x02000000)
 441 #define DSPI_DMCR_MTFE                  (0x04000000)
 442 #define DSPI_DMCR_FRZ                   (0x08000000)
 443 #define DSPI_DMCR_DCONF(x)              (((x)&0x00000003)<<28)
 444 #define DSPI_DMCR_CSCK                  (0x40000000)
 445 #define DSPI_DMCR_MSTR                  (0x80000000)
 446
 447 /* Bit definitions and macros for DTCR */
 448 #define DSPI_DTCR_SPI_TCNT(x)           (((x)&0x0000FFFF)<<16)
 449
 450 /* Bit definitions and macros for DCTAR group */
 451 #define DSPI_DCTAR_BR(x)                (((x)&0x0000000F))
 452 #define DSPI_DCTAR_DT(x)                (((x)&0x0000000F)<<4)
 453 #define DSPI_DCTAR_ASC(x)               (((x)&0x0000000F)<<8)
 454 #define DSPI_DCTAR_CSSCK(x)             (((x)&0x0000000F)<<12)
 455 #define DSPI_DCTAR_PBR(x)               (((x)&0x00000003)<<16)
 456 #define DSPI_DCTAR_PDT(x)               (((x)&0x00000003)<<18)
 457 #define DSPI_DCTAR_PASC(x)              (((x)&0x00000003)<<20)
 458 #define DSPI_DCTAR_PCSSCK(x)            (((x)&0x00000003)<<22)
 459 #define DSPI_DCTAR_LSBFE                (0x01000000)
 460 #define DSPI_DCTAR_CPHA                 (0x02000000)
 461 #define DSPI_DCTAR_CPOL                 (0x04000000)
 462 #define DSPI_DCTAR_TRSZ(x)              (((x)&0x0000000F)<<27)
 463 #define DSPI_DCTAR_PCSSCK_1CLK          (0x00000000)
 464 #define DSPI_DCTAR_PCSSCK_3CLK          (0x00400000)
 465 #define DSPI_DCTAR_PCSSCK_5CLK          (0x00800000)
 466 #define DSPI_DCTAR_PCSSCK_7CLK          (0x00A00000)
 467 #define DSPI_DCTAR_PASC_1CLK            (0x00000000)
 468 #define DSPI_DCTAR_PASC_3CLK            (0x00100000)
 469 #define DSPI_DCTAR_PASC_5CLK            (0x00200000)
 470 #define DSPI_DCTAR_PASC_7CLK            (0x00300000)
 471 #define DSPI_DCTAR_PDT_1CLK             (0x00000000)
 472 #define DSPI_DCTAR_PDT_3CLK             (0x00040000)
 473 #define DSPI_DCTAR_PDT_5CLK             (0x00080000)
 474 #define DSPI_DCTAR_PDT_7CLK             (0x000A0000)
 475 #define DSPI_DCTAR_PBR_1CLK             (0x00000000)
 476 #define DSPI_DCTAR_PBR_3CLK             (0x00010000)
 477 #define DSPI_DCTAR_PBR_5CLK             (0x00020000)
 478 #define DSPI_DCTAR_PBR_7CLK             (0x00030000)
 479
 480 /* Bit definitions and macros for DSR */
 481 #define DSPI_DSR_RXPTR(x)               (((x)&0x0000000F))
 482 #define DSPI_DSR_RXCTR(x)               (((x)&0x0000000F)<<4)
 483 #define DSPI_DSR_TXPTR(x)               (((x)&0x0000000F)<<8)
 484 #define DSPI_DSR_TXCTR(x)               (((x)&0x0000000F)<<12)
 485 #define DSPI_DSR_RFDF                   (0x00020000)
 486 #define DSPI_DSR_RFOF                   (0x00080000)
 487 #define DSPI_DSR_TFFF                   (0x02000000)
 488 #define DSPI_DSR_TFUF                   (0x08000000)
 489 #define DSPI_DSR_EOQF                   (0x10000000)
 490 #define DSPI_DSR_TXRXS                  (0x40000000)
 491 #define DSPI_DSR_TCF                    (0x80000000)
 492
 493 /* Bit definitions and macros for DIRSR */
 494 #define DSPI_DIRSR_RFDFS                (0x00010000)
 495 #define DSPI_DIRSR_RFDFE                (0x00020000)
 496 #define DSPI_DIRSR_RFOFE                (0x00080000)
 497 #define DSPI_DIRSR_TFFFS                (0x01000000)
 498 #define DSPI_DIRSR_TFFFE                (0x02000000)
 499 #define DSPI_DIRSR_TFUFE                (0x08000000)
 500 #define DSPI_DIRSR_EOQFE                (0x10000000)
 501 #define DSPI_DIRSR_TCFE                 (0x80000000)
 502
 503 /* Bit definitions and macros for DTFR */
 504 #define DSPI_DTFR_TXDATA(x)             (((x)&0x0000FFFF))
 505 #define DSPI_DTFR_CS0                   (0x00010000)
 506 #define DSPI_DTFR_CS2                   (0x00040000)
 507 #define DSPI_DTFR_CS3                   (0x00080000)
 508 #define DSPI_DTFR_CS5                   (0x00200000)
 509 #define DSPI_DTFR_CTCNT                 (0x04000000)
 510 #define DSPI_DTFR_EOQ                   (0x08000000)
 511 #define DSPI_DTFR_CTAS(x)               (((x)&0x00000007)<<28)
 512 #define DSPI_DTFR_CONT                  (0x80000000)
 513
 514 /* Bit definitions and macros for DRFR */
 515 #define DSPI_DRFR_RXDATA(x)             (((x)&0x0000FFFF))
 516
 517 /* Bit definitions and macros for DTFDR group */
 518 #define DSPI_DTFDR_TXDATA(x)            (((x)&0x0000FFFF))
 519 #define DSPI_DTFDR_TXCMD(x)             (((x)&0x0000FFFF)<<16)
 520
 521 /* Bit definitions and macros for DRFDR group */
 522 #define DSPI_DRFDR_RXDATA(x)            (((x)&0x0000FFFF))
 523
 524 /*********************************************************************
 525 * Edge Port Module (EPORT)
 526 *********************************************************************/
 527
 528 /* Bit definitions and macros for EPPAR */
 529 #define EPORT_EPPAR_EPPA1(x)            (((x)&0x0003)<<2)
 530 #define EPORT_EPPAR_EPPA2(x)            (((x)&0x0003)<<4)
 531 #define EPORT_EPPAR_EPPA3(x)            (((x)&0x0003)<<6)
 532 #define EPORT_EPPAR_EPPA4(x)            (((x)&0x0003)<<8)
 533 #define EPORT_EPPAR_EPPA5(x)            (((x)&0x0003)<<10)
 534 #define EPORT_EPPAR_EPPA6(x)            (((x)&0x0003)<<12)
 535 #define EPORT_EPPAR_EPPA7(x)            (((x)&0x0003)<<14)
 536 #define EPORT_EPPAR_LEVEL               (0)
 537 #define EPORT_EPPAR_RISING              (1)
 538 #define EPORT_EPPAR_FALLING             (2)
 539 #define EPORT_EPPAR_BOTH                (3)
 540 #define EPORT_EPPAR_EPPA7_LEVEL         (0x0000)
 541 #define EPORT_EPPAR_EPPA7_RISING        (0x4000)
 542 #define EPORT_EPPAR_EPPA7_FALLING       (0x8000)
 543 #define EPORT_EPPAR_EPPA7_BOTH          (0xC000)
 544 #define EPORT_EPPAR_EPPA6_LEVEL         (0x0000)
 545 #define EPORT_EPPAR_EPPA6_RISING        (0x1000)
 546 #define EPORT_EPPAR_EPPA6_FALLING       (0x2000)
 547 #define EPORT_EPPAR_EPPA6_BOTH          (0x3000)
 548 #define EPORT_EPPAR_EPPA5_LEVEL         (0x0000)
 549 #define EPORT_EPPAR_EPPA5_RISING        (0x0400)
 550 #define EPORT_EPPAR_EPPA5_FALLING       (0x0800)
 551 #define EPORT_EPPAR_EPPA5_BOTH          (0x0C00)
 552 #define EPORT_EPPAR_EPPA4_LEVEL         (0x0000)
 553 #define EPORT_EPPAR_EPPA4_RISING        (0x0100)
 554 #define EPORT_EPPAR_EPPA4_FALLING       (0x0200)
 555 #define EPORT_EPPAR_EPPA4_BOTH          (0x0300)
 556 #define EPORT_EPPAR_EPPA3_LEVEL         (0x0000)
 557 #define EPORT_EPPAR_EPPA3_RISING        (0x0040)
 558 #define EPORT_EPPAR_EPPA3_FALLING       (0x0080)
 559 #define EPORT_EPPAR_EPPA3_BOTH          (0x00C0)
 560 #define EPORT_EPPAR_EPPA2_LEVEL         (0x0000)
 561 #define EPORT_EPPAR_EPPA2_RISING        (0x0010)
 562 #define EPORT_EPPAR_EPPA2_FALLING       (0x0020)
 563 #define EPORT_EPPAR_EPPA2_BOTH          (0x0030)
 564 #define EPORT_EPPAR_EPPA1_LEVEL         (0x0000)
 565 #define EPORT_EPPAR_EPPA1_RISING        (0x0004)
 566 #define EPORT_EPPAR_EPPA1_FALLING       (0x0008)
 567 #define EPORT_EPPAR_EPPA1_BOTH          (0x000C)
 568
 569 /* Bit definitions and macros for EPDDR */
 570 #define EPORT_EPDDR_EPDD1               (0x02)
 571 #define EPORT_EPDDR_EPDD2               (0x04)
 572 #define EPORT_EPDDR_EPDD3               (0x08)
 573 #define EPORT_EPDDR_EPDD4               (0x10)
 574 #define EPORT_EPDDR_EPDD5               (0x20)
 575 #define EPORT_EPDDR_EPDD6               (0x40)
 576 #define EPORT_EPDDR_EPDD7               (0x80)
 577
 578 /* Bit definitions and macros for EPIER */
 579 #define EPORT_EPIER_EPIE1               (0x02)
 580 #define EPORT_EPIER_EPIE2               (0x04)
 581 #define EPORT_EPIER_EPIE3               (0x08)
 582 #define EPORT_EPIER_EPIE4               (0x10)
 583 #define EPORT_EPIER_EPIE5               (0x20)
 584 #define EPORT_EPIER_EPIE6               (0x40)
 585 #define EPORT_EPIER_EPIE7               (0x80)
 586
 587 /* Bit definitions and macros for EPDR */
 588 #define EPORT_EPDR_EPD1                 (0x02)
 589 #define EPORT_EPDR_EPD2                 (0x04)
 590 #define EPORT_EPDR_EPD3                 (0x08)
 591 #define EPORT_EPDR_EPD4                 (0x10)
 592 #define EPORT_EPDR_EPD5                 (0x20)
 593 #define EPORT_EPDR_EPD6                 (0x40)
 594 #define EPORT_EPDR_EPD7                 (0x80)
 595
 596 /* Bit definitions and macros for EPPDR */
 597 #define EPORT_EPPDR_EPPD1               (0x02)
 598 #define EPORT_EPPDR_EPPD2               (0x04)
 599 #define EPORT_EPPDR_EPPD3               (0x08)
 600 #define EPORT_EPPDR_EPPD4               (0x10)
 601 #define EPORT_EPPDR_EPPD5               (0x20)
 602 #define EPORT_EPPDR_EPPD6               (0x40)
 603 #define EPORT_EPPDR_EPPD7               (0x80)
 604
 605 /* Bit definitions and macros for EPFR */
 606 #define EPORT_EPFR_EPF1                 (0x02)
 607 #define EPORT_EPFR_EPF2                 (0x04)
 608 #define EPORT_EPFR_EPF3                 (0x08)
 609 #define EPORT_EPFR_EPF4                 (0x10)
 610 #define EPORT_EPFR_EPF5                 (0x20)
 611 #define EPORT_EPFR_EPF6                 (0x40)
 612 #define EPORT_EPFR_EPF7                 (0x80)
 613
 614 /*********************************************************************
 615 * Watchdog Timer Modules (WTM)
 616 *********************************************************************/
 617
 618 /* Bit definitions and macros for WCR */
 619 #define WTM_WCR_EN                      (0x0001)
 620 #define WTM_WCR_HALTED                  (0x0002)
 621 #define WTM_WCR_DOZE                    (0x0004)
 622 #define WTM_WCR_WAIT                    (0x0008)
 623
 624 /*********************************************************************
 625 * Serial Boot Facility (SBF)
 626 *********************************************************************/
 627
 628 /* Bit definitions and macros for SBFCR */
 629 #define SBF_SBFCR_BLDIV(x)              (((x)&0x000F))  /* Boot loader clock divider */
 630 #define SBF_SBFCR_FR                    (0x0010)        /* Fast read */
 631
 632 /*********************************************************************
 633 * Reset Controller Module (RCM)
 634 *********************************************************************/
 635
 636 /* Bit definitions and macros for RCR */
 637 #define RCM_RCR_FRCRSTOUT               (0x40)
 638 #define RCM_RCR_SOFTRST                 (0x80)
 639
 640 /* Bit definitions and macros for RSR */
 641 #define RCM_RSR_LOL                     (0x01)
 642 #define RCM_RSR_WDR_CORE                (0x02)
 643 #define RCM_RSR_EXT                     (0x04)
 644 #define RCM_RSR_POR                     (0x08)
 645 #define RCM_RSR_SOFT                    (0x20)
 646
 647 /*********************************************************************
 648 * Chip Configuration Module (CCM)
 649 *********************************************************************/
 650
 651 /* Bit definitions and macros for CCR_360 */
 652 #define CCM_CCR_360_PLLMULT2(x)         (((x)&0x0003))  /* 2-Bit PLL clock mode */
 653 #define CCM_CCR_360_PCISLEW             (0x0004)        /* PCI pad slew rate mode */
 654 #define CCM_CCR_360_PCIMODE             (0x0008)        /* PCI host/agent mode */
 655 #define CCM_CCR_360_PLLMODE             (0x0010)        /* PLL Mode */
 656 #define CCM_CCR_360_FBCONFIG(x)         (((x)&0x0007)<<5)       /* Flexbus/PCI port size configuration */
 657 #define CCM_CCR_360_PLLMULT3(x)         (((x)&0x0007))  /* 3-Bit PLL Clock Mode */
 658 #define CCM_CCR_360_OSCMODE             (0x0008)        /* Oscillator Clock Mode */
 659 #define CCM_CCR_360_FBCONFIG_MASK       (0x00E0)
 660 #define CCM_CCR_360_PLLMULT2_MASK       (0x0003)
 661 #define CCM_CCR_360_PLLMULT3_MASK       (0x0007)
 662 #define CCM_CCR_360_FBCONFIG_NM_NP_32   (0x0000)
 663 #define CCM_CCR_360_FBCONFIG_NM_NP_8    (0x0020)
 664 #define CCM_CCR_360_FBCONFIG_NM_NP_16   (0x0040)
 665 #define CCM_CCR_360_FBCONFIG_M_P_16     (0x0060)
 666 #define CCM_CCR_360_FBCONFIG_M_NP_32    (0x0080)
 667 #define CCM_CCR_360_FBCONFIG_M_NP_8     (0x00A0)
 668 #define CCM_CCR_360_FBCONFIG_M_NP_16    (0x00C0)
 669 #define CCM_CCR_360_FBCONFIG_M_P_8      (0x00E0)
 670 #define CCM_CCR_360_PLLMULT2_12X        (0x0000)
 671 #define CCM_CCR_360_PLLMULT2_6X         (0x0001)
 672 #define CCM_CCR_360_PLLMULT2_16X        (0x0002)
 673 #define CCM_CCR_360_PLLMULT2_8X         (0x0003)
 674 #define CCM_CCR_360_PLLMULT3_20X        (0x0000)
 675 #define CCM_CCR_360_PLLMULT3_10X        (0x0001)
 676 #define CCM_CCR_360_PLLMULT3_24X        (0x0002)
 677 #define CCM_CCR_360_PLLMULT3_18X        (0x0003)
 678 #define CCM_CCR_360_PLLMULT3_12X        (0x0004)
 679 #define CCM_CCR_360_PLLMULT3_6X         (0x0005)
 680 #define CCM_CCR_360_PLLMULT3_16X        (0x0006)
 681 #define CCM_CCR_360_PLLMULT3_8X         (0x0007)
 682
 683 /* Bit definitions and macros for CCR_256 */
 684 #define CCM_CCR_256_PLLMULT3(x)         (((x)&0x0007))  /* 3-Bit PLL clock mode */
 685 #define CCM_CCR_256_OSCMODE             (0x0008)        /* Oscillator clock mode */
 686 #define CCM_CCR_256_PLLMODE             (0x0010)        /* PLL Mode */
 687 #define CCM_CCR_256_FBCONFIG(x)         (((x)&0x0007)<<5)       /* Flexbus/PCI port size configuration */
 688 #define CCM_CCR_256_FBCONFIG_MASK       (0x00E0)
 689 #define CCM_CCR_256_FBCONFIG_NM_32      (0x0000)
 690 #define CCM_CCR_256_FBCONFIG_NM_8       (0x0020)
 691 #define CCM_CCR_256_FBCONFIG_NM_16      (0x0040)
 692 #define CCM_CCR_256_FBCONFIG_M_32       (0x0080)
 693 #define CCM_CCR_256_FBCONFIG_M_8        (0x00A0)
 694 #define CCM_CCR_256_FBCONFIG_M_16       (0x00C0)
 695 #define CCM_CCR_256_PLLMULT3_MASK       (0x0007)
 696 #define CCM_CCR_256_PLLMULT3_20X        (0x0000)
 697 #define CCM_CCR_256_PLLMULT3_10X        (0x0001)
 698 #define CCM_CCR_256_PLLMULT3_24X        (0x0002)
 699 #define CCM_CCR_256_PLLMULT3_18X        (0x0003)
 700 #define CCM_CCR_256_PLLMULT3_12X        (0x0004)
 701 #define CCM_CCR_256_PLLMULT3_6X         (0x0005)
 702 #define CCM_CCR_256_PLLMULT3_16X        (0x0006)
 703 #define CCM_CCR_256_PLLMULT3_8X         (0x0007)
 704
 705 /* Bit definitions and macros for RCON_360 */
 706 #define CCM_RCON_360_PLLMULT(x)         (((x)&0x0003))  /* PLL clock mode */
 707 #define CCM_RCON_360_PCISLEW            (0x0004)        /* PCI pad slew rate mode */
 708 #define CCM_RCON_360_PCIMODE            (0x0008)        /* PCI host/agent mode */
 709 #define CCM_RCON_360_PLLMODE            (0x0010)        /* PLL Mode */
 710 #define CCM_RCON_360_FBCONFIG(x)        (((x)&0x0007)<<5)       /* Flexbus/PCI port size configuration */
 711
 712 /* Bit definitions and macros for RCON_256 */
 713 #define CCM_RCON_256_PLLMULT(x)         (((x)&0x0007))  /* PLL clock mode */
 714 #define CCM_RCON_256_OSCMODE            (0x0008)        /* Oscillator clock mode */
 715 #define CCM_RCON_256_PLLMODE            (0x0010)        /* PLL Mode */
 716 #define CCM_RCON_256_FBCONFIG(x)        (((x)&0x0007)<<5)       /* Flexbus/PCI port size configuration */
 717
 718 /* Bit definitions and macros for CIR */
 719 #define CCM_CIR_PRN(x)                  (((x)&0x003F))  /* Part revision number */
 720 #define CCM_CIR_PIN(x)                  (((x)&0x03FF)<<6)       /* Part identification number */
 721 #define CCM_CIR_PIN_MASK                (0xFFC0)
 722 #define CCM_CIR_PRN_MASK                (0x003F)
 723 #define CCM_CIR_PIN_MCF54450            (0x4F<<6)
 724 #define CCM_CIR_PIN_MCF54451            (0x4D<<6)
 725 #define CCM_CIR_PIN_MCF54452            (0x4B<<6)
 726 #define CCM_CIR_PIN_MCF54453            (0x49<<6)
 727 #define CCM_CIR_PIN_MCF54454            (0x4A<<6)
 728 #define CCM_CIR_PIN_MCF54455            (0x48<<6)
 729
 730 /* Bit definitions and macros for MISCCR */
 731 #define CCM_MISCCR_USBSRC               (0x0001)        /* USB clock source */
 732 #define CCM_MISCCR_USBOC                (0x0002)        /* USB VBUS over-current sense polarity */
 733 #define CCM_MISCCR_USBPUE               (0x0004)        /* USB transceiver pull-up enable */
 734 #define CCM_MISCCR_SSISRC               (0x0010)        /* SSI clock source */
 735 #define CCM_MISCCR_TIMDMA               (0x0020)        /* Timer DMA mux selection */
 736 #define CCM_MISCCR_SSIPUS               (0x0040)        /* SSI RXD/TXD pull select */
 737 #define CCM_MISCCR_SSIPUE               (0x0080)        /* SSI RXD/TXD pull enable */
 738 #define CCM_MISCCR_BMT(x)               (((x)&0x0007)<<8)       /* Bus monitor timing field */
 739 #define CCM_MISCCR_BME                  (0x0800)        /* Bus monitor external enable bit */
 740 #define CCM_MISCCR_LIMP                 (0x1000)        /* Limp mode enable */
 741 #define CCM_MISCCR_BMT_65536            (0)
 742 #define CCM_MISCCR_BMT_32768            (1)
 743 #define CCM_MISCCR_BMT_16384            (2)
 744 #define CCM_MISCCR_BMT_8192             (3)
 745 #define CCM_MISCCR_BMT_4096             (4)
 746 #define CCM_MISCCR_BMT_2048             (5)
 747 #define CCM_MISCCR_BMT_1024             (6)
 748 #define CCM_MISCCR_BMT_512              (7)
 749 #define CCM_MISCCR_SSIPUS_UP            (1)
 750 #define CCM_MISCCR_SSIPUS_DOWN          (0)
 751 #define CCM_MISCCR_TIMDMA_TIM           (1)
 752 #define CCM_MISCCR_TIMDMA_SSI           (0)
 753 #define CCM_MISCCR_SSISRC_CLKIN         (0)
 754 #define CCM_MISCCR_SSISRC_PLL           (1)
 755 #define CCM_MISCCR_USBOC_ACTHI          (0)
 756 #define CCM_MISCCR_USBOV_ACTLO          (1)
 757 #define CCM_MISCCR_USBSRC_CLKIN         (0)
 758 #define CCM_MISCCR_USBSRC_PLL           (1)
 759
 760 /* Bit definitions and macros for CDR */
 761 #define CCM_CDR_SSIDIV(x)               (((x)&0x00FF))  /* SSI oversampling clock divider */
 762 #define CCM_CDR_LPDIV(x)                (((x)&0x000F)<<8)       /* Low power clock divider */
 763
 764 /* Bit definitions and macros for UOCSR */
 765 #define CCM_UOCSR_XPDE                  (0x0001)        /* On-chip transceiver pull-down enable */
 766 #define CCM_UOCSR_UOMIE                 (0x0002)        /* USB OTG misc interrupt enable */
 767 #define CCM_UOCSR_WKUP                  (0x0004)        /* USB OTG controller wake-up event */
 768 #define CCM_UOCSR_PWRFLT                (0x0008)        /* VBUS power fault */
 769 #define CCM_UOCSR_SEND                  (0x0010)        /* Session end */
 770 #define CCM_UOCSR_VVLD                  (0x0020)        /* VBUS valid indicator */
 771 #define CCM_UOCSR_BVLD                  (0x0040)        /* B-peripheral valid indicator */
 772 #define CCM_UOCSR_AVLD                  (0x0080)        /* A-peripheral valid indicator */
 773 #define CCM_UOCSR_DPPU                  (0x0100)        /* D+ pull-up for FS enabled (read-only) */
 774 #define CCM_UOCSR_DCR_VBUS              (0x0200)        /* VBUS discharge resistor enabled (read-only) */
 775 #define CCM_UOCSR_CRG_VBUS              (0x0400)        /* VBUS charge resistor enabled (read-only) */
 776 #define CCM_UOCSR_DMPD                  (0x1000)        /* D- 15Kohm pull-down (read-only) */
 777 #define CCM_UOCSR_DPPD                  (0x2000)        /* D+ 15Kohm pull-down (read-only) */
 778
 779 /*********************************************************************
 780 * General Purpose I/O Module (GPIO)
 781 *********************************************************************/
 782
 783 /* Bit definitions and macros for PAR_FEC */
 784 #define GPIO_PAR_FEC_FEC0(x)            (((x)&0x07))
 785 #define GPIO_PAR_FEC_FEC1(x)            (((x)&0x07)<<4)
 786 #define GPIO_PAR_FEC_FEC1_MASK          (0x8F)
 787 #define GPIO_PAR_FEC_FEC1_MII           (0x70)
 788 #define GPIO_PAR_FEC_FEC1_RMII_GPIO     (0x30)
 789 #define GPIO_PAR_FEC_FEC1_RMII_ATA      (0x20)
 790 #define GPIO_PAR_FEC_FEC1_ATA           (0x10)
 791 #define GPIO_PAR_FEC_FEC1_GPIO          (0x00)
 792 #define GPIO_PAR_FEC_FEC0_MASK          (0xF8)
 793 #define GPIO_PAR_FEC_FEC0_MII           (0x07)
 794 #define GPIO_PAR_FEC_FEC0_RMII_GPIO     (0x03)
 795 #define GPIO_PAR_FEC_FEC0_RMII_ATA      (0x02)
 796 #define GPIO_PAR_FEC_FEC0_ATA           (0x01)
 797 #define GPIO_PAR_FEC_FEC0_GPIO          (0x00)
 798
 799 /* Bit definitions and macros for PAR_DMA */
 800 #define GPIO_PAR_DMA_DREQ0              (0x01)
 801 #define GPIO_PAR_DMA_DACK0(x)           (((x)&0x03)<<2)
 802 #define GPIO_PAR_DMA_DREQ1(x)           (((x)&0x03)<<4)
 803 #define GPIO_PAR_DMA_DACK1(x)           (((x)&0x03)<<6)
 804 #define GPIO_PAR_DMA_DACK1_MASK         (0x3F)
 805 #define GPIO_PAR_DMA_DACK1_DACK1        (0xC0)
 806 #define GPIO_PAR_DMA_DACK1_ULPI_DIR     (0x40)
 807 #define GPIO_PAR_DMA_DACK1_GPIO         (0x00)
 808 #define GPIO_PAR_DMA_DREQ1_MASK         (0xCF)
 809 #define GPIO_PAR_DMA_DREQ1_DREQ1        (0x30)
 810 #define GPIO_PAR_DMA_DREQ1_USB_CLKIN    (0x10)
 811 #define GPIO_PAR_DMA_DREQ1_GPIO         (0x00)
 812 #define GPIO_PAR_DMA_DACK0_MASK         (0xF3)
 813 #define GPIO_PAR_DMA_DACK0_DACK1        (0x0C)
 814 #define GPIO_PAR_DMA_DACK0_ULPI_DIR     (0x04)
 815 #define GPIO_PAR_DMA_DACK0_GPIO         (0x00)
 816 #define GPIO_PAR_DMA_DREQ0_DREQ0        (0x01)
 817 #define GPIO_PAR_DMA_DREQ0_GPIO         (0x00)
 818
 819 /* Bit definitions and macros for PAR_FBCTL */
 820 #define GPIO_PAR_FBCTL_TS(x)            (((x)&0x03)<<3)
 821 #define GPIO_PAR_FBCTL_RW               (0x20)
 822 #define GPIO_PAR_FBCTL_TA               (0x40)
 823 #define GPIO_PAR_FBCTL_OE               (0x80)
 824 #define GPIO_PAR_FBCTL_OE_OE            (0x80)
 825 #define GPIO_PAR_FBCTL_OE_GPIO          (0x00)
 826 #define GPIO_PAR_FBCTL_TA_TA            (0x40)
 827 #define GPIO_PAR_FBCTL_TA_GPIO          (0x00)
 828 #define GPIO_PAR_FBCTL_RW_RW            (0x20)
 829 #define GPIO_PAR_FBCTL_RW_GPIO          (0x00)
 830 #define GPIO_PAR_FBCTL_TS_MASK          (0xE7)
 831 #define GPIO_PAR_FBCTL_TS_TS            (0x18)
 832 #define GPIO_PAR_FBCTL_TS_ALE           (0x10)
 833 #define GPIO_PAR_FBCTL_TS_TBST          (0x08)
 834 #define GPIO_PAR_FBCTL_TS_GPIO          (0x80)
 835
 836 /* Bit definitions and macros for PAR_DSPI */
 837 #define GPIO_PAR_DSPI_SCK               (0x01)
 838 #define GPIO_PAR_DSPI_SOUT              (0x02)
 839 #define GPIO_PAR_DSPI_SIN               (0x04)
 840 #define GPIO_PAR_DSPI_PCS0              (0x08)
 841 #define GPIO_PAR_DSPI_PCS1              (0x10)
 842 #define GPIO_PAR_DSPI_PCS2              (0x20)
 843 #define GPIO_PAR_DSPI_PCS5              (0x40)
 844 #define GPIO_PAR_DSPI_PCS5_PCS5         (0x40)
 845 #define GPIO_PAR_DSPI_PCS5_GPIO         (0x00)
 846 #define GPIO_PAR_DSPI_PCS2_PCS2         (0x20)
 847 #define GPIO_PAR_DSPI_PCS2_GPIO         (0x00)
 848 #define GPIO_PAR_DSPI_PCS1_PCS1         (0x10)
 849 #define GPIO_PAR_DSPI_PCS1_GPIO         (0x00)
 850 #define GPIO_PAR_DSPI_PCS0_PCS0         (0x08)
 851 #define GPIO_PAR_DSPI_PCS0_GPIO         (0x00)
 852 #define GPIO_PAR_DSPI_SIN_SIN           (0x04)
 853 #define GPIO_PAR_DSPI_SIN_GPIO          (0x00)
 854 #define GPIO_PAR_DSPI_SOUT_SOUT         (0x02)
 855 #define GPIO_PAR_DSPI_SOUT_GPIO         (0x00)
 856 #define GPIO_PAR_DSPI_SCK_SCK           (0x01)
 857 #define GPIO_PAR_DSPI_SCK_GPIO          (0x00)
 858
 859 /* Bit definitions and macros for PAR_BE */
 860 #define GPIO_PAR_BE_BS0                 (0x01)
 861 #define GPIO_PAR_BE_BS1                 (0x04)
 862 #define GPIO_PAR_BE_BS2(x)              (((x)&0x03)<<4)
 863 #define GPIO_PAR_BE_BS3(x)              (((x)&0x03)<<6)
 864 #define GPIO_PAR_BE_BE3_MASK            (0x3F)
 865 #define GPIO_PAR_BE_BE3_BE3             (0xC0)
 866 #define GPIO_PAR_BE_BE3_TSIZ1           (0x80)
 867 #define GPIO_PAR_BE_BE3_GPIO            (0x00)
 868 #define GPIO_PAR_BE_BE2_MASK            (0xCF)
 869 #define GPIO_PAR_BE_BE2_BE2             (0x30)
 870 #define GPIO_PAR_BE_BE2_TSIZ0           (0x20)
 871 #define GPIO_PAR_BE_BE2_GPIO            (0x00)
 872 #define GPIO_PAR_BE_BE1_BE1             (0x04)
 873 #define GPIO_PAR_BE_BE1_GPIO            (0x00)
 874 #define GPIO_PAR_BE_BE0_BE0             (0x01)
 875 #define GPIO_PAR_BE_BE0_GPIO            (0x00)
 876
 877 /* Bit definitions and macros for PAR_CS */
 878 #define GPIO_PAR_CS_CS1                 (0x02)
 879 #define GPIO_PAR_CS_CS2                 (0x04)
 880 #define GPIO_PAR_CS_CS3                 (0x08)
 881 #define GPIO_PAR_CS_CS3_CS3             (0x08)
 882 #define GPIO_PAR_CS_CS3_GPIO            (0x00)
 883 #define GPIO_PAR_CS_CS2_CS2             (0x04)
 884 #define GPIO_PAR_CS_CS2_GPIO            (0x00)
 885 #define GPIO_PAR_CS_CS1_CS1             (0x02)
 886 #define GPIO_PAR_CS_CS1_GPIO            (0x00)
 887
 888 /* Bit definitions and macros for PAR_TIMER */
 889 #define GPIO_PAR_TIMER_T0IN(x)          (((x)&0x03))
 890 #define GPIO_PAR_TIMER_T1IN(x)          (((x)&0x03)<<2)
 891 #define GPIO_PAR_TIMER_T2IN(x)          (((x)&0x03)<<4)
 892 #define GPIO_PAR_TIMER_T3IN(x)          (((x)&0x03)<<6)
 893 #define GPIO_PAR_TIMER_T3IN_MASK        (0x3F)
 894 #define GPIO_PAR_TIMER_T3IN_T3IN        (0xC0)
 895 #define GPIO_PAR_TIMER_T3IN_T3OUT       (0x80)
 896 #define GPIO_PAR_TIMER_T3IN_U2RXD       (0x40)
 897 #define GPIO_PAR_TIMER_T3IN_GPIO        (0x00)
 898 #define GPIO_PAR_TIMER_T2IN_MASK        (0xCF)
 899 #define GPIO_PAR_TIMER_T2IN_T2IN        (0x30)
 900 #define GPIO_PAR_TIMER_T2IN_T2OUT       (0x20)
 901 #define GPIO_PAR_TIMER_T2IN_U2TXD       (0x10)
 902 #define GPIO_PAR_TIMER_T2IN_GPIO        (0x00)
 903 #define GPIO_PAR_TIMER_T1IN_MASK        (0xF3)
 904 #define GPIO_PAR_TIMER_T1IN_T1IN        (0x0C)
 905 #define GPIO_PAR_TIMER_T1IN_T1OUT       (0x08)
 906 #define GPIO_PAR_TIMER_T1IN_U2CTS       (0x04)
 907 #define GPIO_PAR_TIMER_T1IN_GPIO        (0x00)
 908 #define GPIO_PAR_TIMER_T0IN_MASK        (0xFC)
 909 #define GPIO_PAR_TIMER_T0IN_T0IN        (0x03)
 910 #define GPIO_PAR_TIMER_T0IN_T0OUT       (0x02)
 911 #define GPIO_PAR_TIMER_T0IN_U2RTS       (0x01)
 912 #define GPIO_PAR_TIMER_T0IN_GPIO        (0x00)
 913
 914 /* Bit definitions and macros for PAR_USB */
 915 #define GPIO_PAR_USB_VBUSOC(x)          (((x)&0x03))
 916 #define GPIO_PAR_USB_VBUSEN(x)          (((x)&0x03)<<2)
 917 #define GPIO_PAR_USB_VBUSEN_MASK        (0xF3)
 918 #define GPIO_PAR_USB_VBUSEN_VBUSEN      (0x0C)
 919 #define GPIO_PAR_USB_VBUSEN_USBPULLUP   (0x08)
 920 #define GPIO_PAR_USB_VBUSEN_ULPI_NXT    (0x04)
 921 #define GPIO_PAR_USB_VBUSEN_GPIO        (0x00)
 922 #define GPIO_PAR_USB_VBUSOC_MASK        (0xFC)
 923 #define GPIO_PAR_USB_VBUSOC_VBUSOC      (0x03)
 924 #define GPIO_PAR_USB_VBUSOC_ULPI_STP    (0x01)
 925 #define GPIO_PAR_USB_VBUSOC_GPIO        (0x00)
 926
 927 /* Bit definitions and macros for PAR_UART */
 928 #define GPIO_PAR_UART_U0TXD             (0x01)
 929 #define GPIO_PAR_UART_U0RXD             (0x02)
 930 #define GPIO_PAR_UART_U0RTS             (0x04)
 931 #define GPIO_PAR_UART_U0CTS             (0x08)
 932 #define GPIO_PAR_UART_U1TXD             (0x10)
 933 #define GPIO_PAR_UART_U1RXD             (0x20)
 934 #define GPIO_PAR_UART_U1RTS             (0x40)
 935 #define GPIO_PAR_UART_U1CTS             (0x80)
 936 #define GPIO_PAR_UART_U1CTS_U1CTS       (0x80)
 937 #define GPIO_PAR_UART_U1CTS_GPIO        (0x00)
 938 #define GPIO_PAR_UART_U1RTS_U1RTS       (0x40)
 939 #define GPIO_PAR_UART_U1RTS_GPIO        (0x00)
 940 #define GPIO_PAR_UART_U1RXD_U1RXD       (0x20)
 941 #define GPIO_PAR_UART_U1RXD_GPIO        (0x00)
 942 #define GPIO_PAR_UART_U1TXD_U1TXD       (0x10)
 943 #define GPIO_PAR_UART_U1TXD_GPIO        (0x00)
 944 #define GPIO_PAR_UART_U0CTS_U0CTS       (0x08)
 945 #define GPIO_PAR_UART_U0CTS_GPIO        (0x00)
 946 #define GPIO_PAR_UART_U0RTS_U0RTS       (0x04)
 947 #define GPIO_PAR_UART_U0RTS_GPIO        (0x00)
 948 #define GPIO_PAR_UART_U0RXD_U0RXD       (0x02)
 949 #define GPIO_PAR_UART_U0RXD_GPIO        (0x00)
 950 #define GPIO_PAR_UART_U0TXD_U0TXD       (0x01)
 951 #define GPIO_PAR_UART_U0TXD_GPIO        (0x00)
 952
 953 /* Bit definitions and macros for PAR_FECI2C */
 954 #define GPIO_PAR_FECI2C_SDA(x)          (((x)&0x0003))
 955 #define GPIO_PAR_FECI2C_SCL(x)          (((x)&0x0003)<<2)
 956 #define GPIO_PAR_FECI2C_MDIO0           (0x0010)
 957 #define GPIO_PAR_FECI2C_MDC0            (0x0040)
 958 #define GPIO_PAR_FECI2C_MDIO1(x)        (((x)&0x0003)<<8)
 959 #define GPIO_PAR_FECI2C_MDC1(x)         (((x)&0x0003)<<10)
 960 #define GPIO_PAR_FECI2C_MDC1_MASK       (0xF3FF)
 961 #define GPIO_PAR_FECI2C_MDC1_MDC1       (0x0C00)
 962 #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR   (0x0800)
 963 #define GPIO_PAR_FECI2C_MDC1_GPIO       (0x0000)
 964 #define GPIO_PAR_FECI2C_MDIO1_MASK      (0xFCFF)
 965 #define GPIO_PAR_FECI2C_MDIO1_MDIO1     (0x0300)
 966 #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW  (0x0200)
 967 #define GPIO_PAR_FECI2C_MDIO1_GPIO      (0x0000)
 968 #define GPIO_PAR_FECI2C_MDC0_MDC0       (0x0040)
 969 #define GPIO_PAR_FECI2C_MDC0_GPIO       (0x0000)
 970 #define GPIO_PAR_FECI2C_MDIO0_MDIO0     (0x0010)
 971 #define GPIO_PAR_FECI2C_MDIO0_GPIO      (0x0000)
 972 #define GPIO_PAR_FECI2C_SCL_MASK        (0xFFF3)
 973 #define GPIO_PAR_FECI2C_SCL_SCL         (0x000C)
 974 #define GPIO_PAR_FECI2C_SCL_U2TXD       (0x0004)
 975 #define GPIO_PAR_FECI2C_SCL_GPIO        (0x0000)
 976 #define GPIO_PAR_FECI2C_SDA_MASK        (0xFFFC)
 977 #define GPIO_PAR_FECI2C_SDA_SDA         (0x0003)
 978 #define GPIO_PAR_FECI2C_SDA_U2RXD       (0x0001)
 979 #define GPIO_PAR_FECI2C_SDA_GPIO        (0x0000)
 980
 981 /* Bit definitions and macros for PAR_SSI */
 982 #define GPIO_PAR_SSI_MCLK               (0x0001)
 983 #define GPIO_PAR_SSI_STXD(x)            (((x)&0x0003)<<2)
 984 #define GPIO_PAR_SSI_SRXD(x)            (((x)&0x0003)<<4)
 985 #define GPIO_PAR_SSI_FS(x)              (((x)&0x0003)<<6)
 986 #define GPIO_PAR_SSI_BCLK(x)            (((x)&0x0003)<<8)
 987 #define GPIO_PAR_SSI_BCLK_MASK          (0xFCFF)
 988 #define GPIO_PAR_SSI_BCLK_BCLK          (0x0300)
 989 #define GPIO_PAR_SSI_BCLK_U1CTS         (0x0200)
 990 #define GPIO_PAR_SSI_BCLK_GPIO          (0x0000)
 991 #define GPIO_PAR_SSI_FS_MASK            (0xFF3F)
 992 #define GPIO_PAR_SSI_FS_FS              (0x00C0)
 993 #define GPIO_PAR_SSI_FS_U1RTS           (0x0080)
 994 #define GPIO_PAR_SSI_FS_GPIO            (0x0000)
 995 #define GPIO_PAR_SSI_SRXD_MASK          (0xFFCF)
 996 #define GPIO_PAR_SSI_SRXD_SRXD          (0x0030)
 997 #define GPIO_PAR_SSI_SRXD_U1RXD         (0x0020)
 998 #define GPIO_PAR_SSI_SRXD_GPIO          (0x0000)
 999 #define GPIO_PAR_SSI_STXD_MASK          (0xFFF3)
1000 #define GPIO_PAR_SSI_STXD_STXD          (0x000C)
1001 #define GPIO_PAR_SSI_STXD_U1TXD         (0x0008)
1002 #define GPIO_PAR_SSI_STXD_GPIO          (0x0000)
1003 #define GPIO_PAR_SSI_MCLK_MCLK          (0x0001)
1004 #define GPIO_PAR_SSI_MCLK_GPIO          (0x0000)
1005
1006 /* Bit definitions and macros for PAR_ATA */
1007 #define GPIO_PAR_ATA_IORDY              (0x0001)
1008 #define GPIO_PAR_ATA_DMARQ              (0x0002)
1009 #define GPIO_PAR_ATA_RESET              (0x0004)
1010 #define GPIO_PAR_ATA_DA0                (0x0020)
1011 #define GPIO_PAR_ATA_DA1                (0x0040)
1012 #define GPIO_PAR_ATA_DA2                (0x0080)
1013 #define GPIO_PAR_ATA_CS0                (0x0100)
1014 #define GPIO_PAR_ATA_CS1                (0x0200)
1015 #define GPIO_PAR_ATA_BUFEN              (0x0400)
1016 #define GPIO_PAR_ATA_BUFEN_BUFEN        (0x0400)
1017 #define GPIO_PAR_ATA_BUFEN_GPIO         (0x0000)
1018 #define GPIO_PAR_ATA_CS1_CS1            (0x0200)
1019 #define GPIO_PAR_ATA_CS1_GPIO           (0x0000)
1020 #define GPIO_PAR_ATA_CS0_CS0            (0x0100)
1021 #define GPIO_PAR_ATA_CS0_GPIO           (0x0000)
1022 #define GPIO_PAR_ATA_DA2_DA2            (0x0080)
1023 #define GPIO_PAR_ATA_DA2_GPIO           (0x0000)
1024 #define GPIO_PAR_ATA_DA1_DA1            (0x0040)
1025 #define GPIO_PAR_ATA_DA1_GPIO           (0x0000)
1026 #define GPIO_PAR_ATA_DA0_DA0            (0x0020)
1027 #define GPIO_PAR_ATA_DA0_GPIO           (0x0000)
1028 #define GPIO_PAR_ATA_RESET_RESET        (0x0004)
1029 #define GPIO_PAR_ATA_RESET_GPIO         (0x0000)
1030 #define GPIO_PAR_ATA_DMARQ_DMARQ        (0x0002)
1031 #define GPIO_PAR_ATA_DMARQ_GPIO         (0x0000)
1032 #define GPIO_PAR_ATA_IORDY_IORDY        (0x0001)
1033 #define GPIO_PAR_ATA_IORDY_GPIO         (0x0000)
1034
1035 /* Bit definitions and macros for PAR_IRQ */
1036 #define GPIO_PAR_IRQ_IRQ1               (0x02)
1037 #define GPIO_PAR_IRQ_IRQ4               (0x10)
1038 #define GPIO_PAR_IRQ_IRQ4_IRQ4          (0x10)
1039 #define GPIO_PAR_IRQ_IRQ4_GPIO          (0x00)
1040 #define GPIO_PAR_IRQ_IRQ1_IRQ1          (0x02)
1041 #define GPIO_PAR_IRQ_IRQ1_GPIO          (0x00)
1042
1043 /* Bit definitions and macros for PAR_PCI */
1044 #define GPIO_PAR_PCI_REQ0               (0x0001)
1045 #define GPIO_PAR_PCI_REQ1               (0x0004)
1046 #define GPIO_PAR_PCI_REQ2               (0x0010)
1047 #define GPIO_PAR_PCI_REQ3(x)            (((x)&0x0003)<<6)
1048 #define GPIO_PAR_PCI_GNT0               (0x0100)
1049 #define GPIO_PAR_PCI_GNT1               (0x0400)
1050 #define GPIO_PAR_PCI_GNT2               (0x1000)
1051 #define GPIO_PAR_PCI_GNT3(x)            (((x)&0x0003)<<14)
1052 #define GPIO_PAR_PCI_GNT3_MASK          (0x3FFF)
1053 #define GPIO_PAR_PCI_GNT3_GNT3          (0xC000)
1054 #define GPIO_PAR_PCI_GNT3_ATA_DMACK     (0x8000)
1055 #define GPIO_PAR_PCI_GNT3_GPIO          (0x0000)
1056 #define GPIO_PAR_PCI_GNT2_GNT2          (0x1000)
1057 #define GPIO_PAR_PCI_GNT2_GPIO          (0x0000)
1058 #define GPIO_PAR_PCI_GNT1_GNT1          (0x0400)
1059 #define GPIO_PAR_PCI_GNT1_GPIO          (0x0000)
1060 #define GPIO_PAR_PCI_GNT0_GNT0          (0x0100)
1061 #define GPIO_PAR_PCI_GNT0_GPIO          (0x0000)
1062 #define GPIO_PAR_PCI_REQ3_MASK          (0xFF3F)
1063 #define GPIO_PAR_PCI_REQ3_REQ3          (0x00C0)
1064 #define GPIO_PAR_PCI_REQ3_ATA_INTRQ     (0x0080)
1065 #define GPIO_PAR_PCI_REQ3_GPIO          (0x0000)
1066 #define GPIO_PAR_PCI_REQ2_REQ2          (0x0010)
1067 #define GPIO_PAR_PCI_REQ2_GPIO          (0x0000)
1068 #define GPIO_PAR_PCI_REQ1_REQ1          (0x0040)
1069 #define GPIO_PAR_PCI_REQ1_GPIO          (0x0000)
1070 #define GPIO_PAR_PCI_REQ0_REQ0          (0x0001)
1071 #define GPIO_PAR_PCI_REQ0_GPIO          (0x0000)
1072
1073 /* Bit definitions and macros for MSCR_SDRAM */
1074 #define GPIO_MSCR_SDRAM_SDCTL(x)        (((x)&0x03))
1075 #define GPIO_MSCR_SDRAM_SDCLK(x)        (((x)&0x03)<<2)
1076 #define GPIO_MSCR_SDRAM_SDDQS(x)        (((x)&0x03)<<4)
1077 #define GPIO_MSCR_SDRAM_SDDATA(x)       (((x)&0x03)<<6)
1078 #define GPIO_MSCR_SDRAM_SDDATA_MASK     (0x3F)
1079 #define GPIO_MSCR_SDRAM_SDDATA_DDR1     (0xC0)
1080 #define GPIO_MSCR_SDRAM_SDDATA_DDR2     (0x80)
1081 #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
1082 #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
1083 #define GPIO_MSCR_SDRAM_SDDQS_MASK      (0xCF)
1084 #define GPIO_MSCR_SDRAM_SDDQS_DDR1      (0x30)
1085 #define GPIO_MSCR_SDRAM_SDDQS_DDR2      (0x20)
1086 #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR  (0x10)
1087 #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR  (0x00)
1088 #define GPIO_MSCR_SDRAM_SDCLK_MASK      (0xF3)
1089 #define GPIO_MSCR_SDRAM_SDCLK_DDR1      (0x0C)
1090 #define GPIO_MSCR_SDRAM_SDCLK_DDR2      (0x08)
1091 #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR  (0x04)
1092 #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR  (0x00)
1093 #define GPIO_MSCR_SDRAM_SDCTL_MASK      (0xFC)
1094 #define GPIO_MSCR_SDRAM_SDCTL_DDR1      (0x03)
1095 #define GPIO_MSCR_SDRAM_SDCTL_DDR2      (0x02)
1096 #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR  (0x01)
1097 #define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR  (0x00)
1098
1099 /* Bit definitions and macros for MSCR_PCI */
1100 #define GPIO_MSCR_PCI_PCI               (0x01)
1101 #define GPIO_MSCR_PCI_PCI_HI_66MHZ      (0x01)
1102 #define GPIO_MSCR_PCI_PCI_LO_33MHZ      (0x00)
1103
1104 /* Bit definitions and macros for DSCR_I2C */
1105 #define GPIO_DSCR_I2C_I2C(x)            (((x)&0x03))
1106 #define GPIO_DSCR_I2C_I2C_LOAD_50PF     (0x03)
1107 #define GPIO_DSCR_I2C_I2C_LOAD_30PF     (0x02)
1108 #define GPIO_DSCR_I2C_I2C_LOAD_20PF     (0x01)
1109 #define GPIO_DSCR_I2C_I2C_LOAD_10PF     (0x00)
1110
1111 /* Bit definitions and macros for DSCR_FLEXBUS */
1112 #define GPIO_DSCR_FLEXBUS_FBADL(x)              (((x)&0x03))
1113 #define GPIO_DSCR_FLEXBUS_FBADH(x)              (((x)&0x03)<<2)
1114 #define GPIO_DSCR_FLEXBUS_FBCTL(x)              (((x)&0x03)<<4)
1115 #define GPIO_DSCR_FLEXBUS_FBCLK(x)              (((x)&0x03)<<6)
1116 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF       (0xC0)
1117 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF       (0x80)
1118 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF       (0x40)
1119 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF       (0x00)
1120 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF       (0x30)
1121 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF       (0x20)
1122 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF       (0x10)
1123 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF       (0x00)
1124 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF       (0x0C)
1125 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF       (0x08)
1126 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF       (0x04)
1127 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF       (0x00)
1128 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF       (0x03)
1129 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF       (0x02)
1130 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF       (0x01)
1131 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF       (0x00)
1132
1133 /* Bit definitions and macros for DSCR_FEC */
1134 #define GPIO_DSCR_FEC_FEC0(x)           (((x)&0x03))
1135 #define GPIO_DSCR_FEC_FEC1(x)           (((x)&0x03)<<2)
1136 #define GPIO_DSCR_FEC_FEC1_LOAD_50PF    (0x0C)
1137 #define GPIO_DSCR_FEC_FEC1_LOAD_30PF    (0x08)
1138 #define GPIO_DSCR_FEC_FEC1_LOAD_20PF    (0x04)
1139 #define GPIO_DSCR_FEC_FEC1_LOAD_10PF    (0x00)
1140 #define GPIO_DSCR_FEC_FEC0_LOAD_50PF    (0x03)
1141 #define GPIO_DSCR_FEC_FEC0_LOAD_30PF    (0x02)
1142 #define GPIO_DSCR_FEC_FEC0_LOAD_20PF    (0x01)
1143 #define GPIO_DSCR_FEC_FEC0_LOAD_10PF    (0x00)
1144
1145 /* Bit definitions and macros for DSCR_UART */
1146 #define GPIO_DSCR_UART_UART0(x)         (((x)&0x03))
1147 #define GPIO_DSCR_UART_UART1(x)         (((x)&0x03)<<2)
1148 #define GPIO_DSCR_UART_UART1_LOAD_50PF  (0x0C)
1149 #define GPIO_DSCR_UART_UART1_LOAD_30PF  (0x08)
1150 #define GPIO_DSCR_UART_UART1_LOAD_20PF  (0x04)
1151 #define GPIO_DSCR_UART_UART1_LOAD_10PF  (0x00)
1152 #define GPIO_DSCR_UART_UART0_LOAD_50PF  (0x03)
1153 #define GPIO_DSCR_UART_UART0_LOAD_30PF  (0x02)
1154 #define GPIO_DSCR_UART_UART0_LOAD_20PF  (0x01)
1155 #define GPIO_DSCR_UART_UART0_LOAD_10PF  (0x00)
1156
1157 /* Bit definitions and macros for DSCR_DSPI */
1158 #define GPIO_DSCR_DSPI_DSPI(x)          (((x)&0x03))
1159 #define GPIO_DSCR_DSPI_DSPI_LOAD_50PF   (0x03)
1160 #define GPIO_DSCR_DSPI_DSPI_LOAD_30PF   (0x02)
1161 #define GPIO_DSCR_DSPI_DSPI_LOAD_20PF   (0x01)
1162 #define GPIO_DSCR_DSPI_DSPI_LOAD_10PF   (0x00)
1163
1164 /* Bit definitions and macros for DSCR_TIMER */
1165 #define GPIO_DSCR_TIMER_TIMER(x)        (((x)&0x03))
1166 #define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
1167 #define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
1168 #define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
1169 #define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
1170
1171 /* Bit definitions and macros for DSCR_SSI */
1172 #define GPIO_DSCR_SSI_SSI(x)            (((x)&0x03))
1173 #define GPIO_DSCR_SSI_SSI_LOAD_50PF     (0x03)
1174 #define GPIO_DSCR_SSI_SSI_LOAD_30PF     (0x02)
1175 #define GPIO_DSCR_SSI_SSI_LOAD_20PF     (0x01)
1176 #define GPIO_DSCR_SSI_SSI_LOAD_10PF     (0x00)
1177
1178 /* Bit definitions and macros for DSCR_DMA */
1179 #define GPIO_DSCR_DMA_DMA(x)            (((x)&0x03))
1180 #define GPIO_DSCR_DMA_DMA_LOAD_50PF     (0x03)
1181 #define GPIO_DSCR_DMA_DMA_LOAD_30PF     (0x02)
1182 #define GPIO_DSCR_DMA_DMA_LOAD_20PF     (0x01)
1183 #define GPIO_DSCR_DMA_DMA_LOAD_10PF     (0x00)
1184
1185 /* Bit definitions and macros for DSCR_DEBUG */
1186 #define GPIO_DSCR_DEBUG_DEBUG(x)        (((x)&0x03))
1187 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
1188 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
1189 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
1190 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
1191
1192 /* Bit definitions and macros for DSCR_RESET */
1193 #define GPIO_DSCR_RESET_RESET(x)        (((x)&0x03))
1194 #define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
1195 #define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
1196 #define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
1197 #define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
1198
1199 /* Bit definitions and macros for DSCR_IRQ */
1200 #define GPIO_DSCR_IRQ_IRQ(x)            (((x)&0x03))
1201 #define GPIO_DSCR_IRQ_IRQ_LOAD_50PF     (0x03)
1202 #define GPIO_DSCR_IRQ_IRQ_LOAD_30PF     (0x02)
1203 #define GPIO_DSCR_IRQ_IRQ_LOAD_20PF     (0x01)
1204 #define GPIO_DSCR_IRQ_IRQ_LOAD_10PF     (0x00)
1205
1206 /* Bit definitions and macros for DSCR_USB */
1207 #define GPIO_DSCR_USB_USB(x)            (((x)&0x03))
1208 #define GPIO_DSCR_USB_USB_LOAD_50PF     (0x03)
1209 #define GPIO_DSCR_USB_USB_LOAD_30PF     (0x02)
1210 #define GPIO_DSCR_USB_USB_LOAD_20PF     (0x01)
1211 #define GPIO_DSCR_USB_USB_LOAD_10PF     (0x00)
1212
1213 /* Bit definitions and macros for DSCR_ATA */
1214 #define GPIO_DSCR_ATA_ATA(x)            (((x)&0x03))
1215 #define GPIO_DSCR_ATA_ATA_LOAD_50PF     (0x03)
1216 #define GPIO_DSCR_ATA_ATA_LOAD_30PF     (0x02)
1217 #define GPIO_DSCR_ATA_ATA_LOAD_20PF     (0x01)
1218 #define GPIO_DSCR_ATA_ATA_LOAD_10PF     (0x00)
1219
1220 /*********************************************************************
1221 * Random Number Generator (RNG)
1222 *********************************************************************/
1223
1224 /* Bit definitions and macros for RNGCR */
1225 #define RNG_RNGCR_GO                    (0x00000001)
1226 #define RNG_RNGCR_HA                    (0x00000002)
1227 #define RNG_RNGCR_IM                    (0x00000004)
1228 #define RNG_RNGCR_CI                    (0x00000008)
1229
1230 /* Bit definitions and macros for RNGSR */
1231 #define RNG_RNGSR_SV                    (0x00000001)
1232 #define RNG_RNGSR_LRS                   (0x00000002)
1233 #define RNG_RNGSR_FUF                   (0x00000004)
1234 #define RNG_RNGSR_EI                    (0x00000008)
1235 #define RNG_RNGSR_OFL(x)                (((x)&0x000000FF)<<8)
1236 #define RNG_RNGSR_OFS(x)                (((x)&0x000000FF)<<16)
1237
1238 /*********************************************************************
1239 * SDRAM Controller (SDRAMC)
1240 *********************************************************************/
1241
1242 /* Bit definitions and macros for SDMR */
1243 #define SDRAMC_SDMR_DDR2_AD(x)          (((x)&0x00003FFF))      /* Address for DDR2 */
1244 #define SDRAMC_SDMR_CMD                 (0x00010000)    /* Command */
1245 #define SDRAMC_SDMR_AD(x)               (((x)&0x00000FFF)<<18)  /* Address */
1246 #define SDRAMC_SDMR_BK(x)               (((x)&0x00000003)<<30)  /* Bank Address */
1247 #define SDRAMC_SDMR_BK_LMR              (0x00000000)
1248 #define SDRAMC_SDMR_BK_LEMR             (0x40000000)
1249
1250 /* Bit definitions and macros for SDCR */
1251 #define SDRAMC_SDCR_DPD                 (0x00000001)    /* Deep Power-Down Mode */
1252 #define SDRAMC_SDCR_IPALL               (0x00000002)    /* Initiate Precharge All */
1253 #define SDRAMC_SDCR_IREF                (0x00000004)    /* Initiate Refresh */
1254 #define SDRAMC_SDCR_DQS_OE(x)           (((x)&0x00000003)<<10)  /* DQS Output Enable */
1255 #define SDRAMC_SDCR_MEM_PS              (0x00002000)    /* Data Port Size */
1256 #define SDRAMC_SDCR_REF_CNT(x)          (((x)&0x0000003F)<<16)  /* Periodic Refresh Counter */
1257 #define SDRAMC_SDCR_OE_RULE             (0x00400000)    /* Drive Rule Selection */
1258 #define SDRAMC_SDCR_ADDR_MUX(x)         (((x)&0x00000003)<<24)  /* Internal Address Mux Select */
1259 #define SDRAMC_SDCR_DDR2_MODE           (0x08000000)    /* DDR2 Mode Select */
1260 #define SDRAMC_SDCR_REF_EN              (0x10000000)    /* Refresh Enable */
1261 #define SDRAMC_SDCR_DDR_MODE            (0x20000000)    /* DDR Mode Select */
1262 #define SDRAMC_SDCR_CKE                 (0x40000000)    /* Clock Enable */
1263 #define SDRAMC_SDCR_MODE_EN             (0x80000000)    /* SDRAM Mode Register Programming Enable */
1264 #define SDRAMC_SDCR_DQS_OE_BOTH         (0x00000C000)
1265
1266 /* Bit definitions and macros for SDCFG1 */
1267 #define SDRAMC_SDCFG1_WT_LAT(x)         (((x)&0x00000007)<<4)   /* Write Latency */
1268 #define SDRAMC_SDCFG1_REF2ACT(x)        (((x)&0x0000000F)<<8)   /* Refresh to active delay */
1269 #define SDRAMC_SDCFG1_PRE2ACT(x)        (((x)&0x00000007)<<12)  /* Precharge to active delay */
1270 #define SDRAMC_SDCFG1_ACT2RW(x)         (((x)&0x00000007)<<16)  /* Active to read/write delay */
1271 #define SDRAMC_SDCFG1_RD_LAT(x)         (((x)&0x0000000F)<<20)  /* Read CAS Latency */
1272 #define SDRAMC_SDCFG1_SWT2RWP(x)        (((x)&0x00000007)<<24)  /* Single write to read/write/precharge delay */
1273 #define SDRAMC_SDCFG1_SRD2RWP(x)        (((x)&0x0000000F)<<28)  /* Single read to read/write/precharge delay */
1274
1275 /* Bit definitions and macros for SDCFG2 */
1276 #define SDRAMC_SDCFG2_BL(x)             (((x)&0x0000000F)<<16)  /* Burst Length */
1277 #define SDRAMC_SDCFG2_BRD2W(x)          (((x)&0x0000000F)<<20)  /* Burst read to write delay */
1278 #define SDRAMC_SDCFG2_BWT2RWP(x)        (((x)&0x0000000F)<<24)  /* Burst write to read/write/precharge delay */
1279 #define SDRAMC_SDCFG2_BRD2RP(x)         (((x)&0x0000000F)<<28)  /* Burst read to read/precharge delay */
1280
1281 /* Bit definitions and macros for SDCS group */
1282 #define SDRAMC_SDCS_CSSZ(x)             (((x)&0x0000001F))      /* Chip-Select Size */
1283 #define SDRAMC_SDCS_CSBA(x)             (((x)&0x00000FFF)<<20)  /* Chip-Select Base Address */
1284 #define SDRAMC_SDCS_BA(x)               ((x)&0xFFF00000)
1285 #define SDRAMC_SDCS_CSSZ_DISABLE        (0x00000000)
1286 #define SDRAMC_SDCS_CSSZ_1MBYTE         (0x00000013)
1287 #define SDRAMC_SDCS_CSSZ_2MBYTE         (0x00000014)
1288 #define SDRAMC_SDCS_CSSZ_4MBYTE         (0x00000015)
1289 #define SDRAMC_SDCS_CSSZ_8MBYTE         (0x00000016)
1290 #define SDRAMC_SDCS_CSSZ_16MBYTE        (0x00000017)
1291 #define SDRAMC_SDCS_CSSZ_32MBYTE        (0x00000018)
1292 #define SDRAMC_SDCS_CSSZ_64MBYTE        (0x00000019)
1293 #define SDRAMC_SDCS_CSSZ_128MBYTE       (0x0000001A)
1294 #define SDRAMC_SDCS_CSSZ_256MBYTE       (0x0000001B)
1295 #define SDRAMC_SDCS_CSSZ_512MBYTE       (0x0000001C)
1296 #define SDRAMC_SDCS_CSSZ_1GBYTE         (0x0000001D)
1297 #define SDRAMC_SDCS_CSSZ_2GBYTE         (0x0000001E)
1298 #define SDRAMC_SDCS_CSSZ_4GBYTE         (0x0000001F)
1299
1300 /*********************************************************************
1301 * Synchronous Serial Interface (SSI)
1302 *********************************************************************/
1303
1304 /* Bit definitions and macros for CR */
1305 #define SSI_CR_SSI_EN                   (0x00000001)
1306 #define SSI_CR_TE                       (0x00000002)
1307 #define SSI_CR_RE                       (0x00000004)
1308 #define SSI_CR_NET                      (0x00000008)
1309 #define SSI_CR_SYN                      (0x00000010)
1310 #define SSI_CR_I2S(x)                   (((x)&0x00000003)<<5)
1311 #define SSI_CR_MCE                      (0x00000080)
1312 #define SSI_CR_TCH                      (0x00000100)
1313 #define SSI_CR_CIS                      (0x00000200)
1314 #define SSI_CR_I2S_NORMAL               (0x00000000)
1315 #define SSI_CR_I2S_MASTER               (0x00000020)
1316 #define SSI_CR_I2S_SLAVE                (0x00000040)
1317
1318 /* Bit definitions and macros for ISR */
1319 #define SSI_ISR_TFE0                    (0x00000001)
1320 #define SSI_ISR_TFE1                    (0x00000002)
1321 #define SSI_ISR_RFF0                    (0x00000004)
1322 #define SSI_ISR_RFF1                    (0x00000008)
1323 #define SSI_ISR_RLS                     (0x00000010)
1324 #define SSI_ISR_TLS                     (0x00000020)
1325 #define SSI_ISR_RFS                     (0x00000040)
1326 #define SSI_ISR_TFS                     (0x00000080)
1327 #define SSI_ISR_TUE0                    (0x00000100)
1328 #define SSI_ISR_TUE1                    (0x00000200)
1329 #define SSI_ISR_ROE0                    (0x00000400)
1330 #define SSI_ISR_ROE1                    (0x00000800)
1331 #define SSI_ISR_TDE0                    (0x00001000)
1332 #define SSI_ISR_TDE1                    (0x00002000)
1333 #define SSI_ISR_RDR0                    (0x00004000)
1334 #define SSI_ISR_RDR1                    (0x00008000)
1335 #define SSI_ISR_RXT                     (0x00010000)
1336 #define SSI_ISR_CMDDU                   (0x00020000)
1337 #define SSI_ISR_CMDAU                   (0x00040000)
1338
1339 /* Bit definitions and macros for IER */
1340 #define SSI_IER_TFE0                    (0x00000001)
1341 #define SSI_IER_TFE1                    (0x00000002)
1342 #define SSI_IER_RFF0                    (0x00000004)
1343 #define SSI_IER_RFF1                    (0x00000008)
1344 #define SSI_IER_RLS                     (0x00000010)
1345 #define SSI_IER_TLS                     (0x00000020)
1346 #define SSI_IER_RFS                     (0x00000040)
1347 #define SSI_IER_TFS                     (0x00000080)
1348 #define SSI_IER_TUE0                    (0x00000100)
1349 #define SSI_IER_TUE1                    (0x00000200)
1350 #define SSI_IER_ROE0                    (0x00000400)
1351 #define SSI_IER_ROE1                    (0x00000800)
1352 #define SSI_IER_TDE0                    (0x00001000)
1353 #define SSI_IER_TDE1                    (0x00002000)
1354 #define SSI_IER_RDR0                    (0x00004000)
1355 #define SSI_IER_RDR1                    (0x00008000)
1356 #define SSI_IER_RXT                     (0x00010000)
1357 #define SSI_IER_CMDU                    (0x00020000)
1358 #define SSI_IER_CMDAU                   (0x00040000)
1359 #define SSI_IER_TIE                     (0x00080000)
1360 #define SSI_IER_TDMAE                   (0x00100000)
1361 #define SSI_IER_RIE                     (0x00200000)
1362 #define SSI_IER_RDMAE                   (0x00400000)
1363
1364 /* Bit definitions and macros for TCR */
1365 #define SSI_TCR_TEFS                    (0x00000001)
1366 #define SSI_TCR_TFSL                    (0x00000002)
1367 #define SSI_TCR_TFSI                    (0x00000004)
1368 #define SSI_TCR_TSCKP                   (0x00000008)
1369 #define SSI_TCR_TSHFD                   (0x00000010)
1370 #define SSI_TCR_TXDIR                   (0x00000020)
1371 #define SSI_TCR_TFDIR                   (0x00000040)
1372 #define SSI_TCR_TFEN0                   (0x00000080)
1373 #define SSI_TCR_TFEN1                   (0x00000100)
1374 #define SSI_TCR_TXBIT0                  (0x00000200)
1375
1376 /* Bit definitions and macros for RCR */
1377 #define SSI_RCR_REFS                    (0x00000001)
1378 #define SSI_RCR_RFSL                    (0x00000002)
1379 #define SSI_RCR_RFSI                    (0x00000004)
1380 #define SSI_RCR_RSCKP                   (0x00000008)
1381 #define SSI_RCR_RSHFD                   (0x00000010)
1382 #define SSI_RCR_RFEN0                   (0x00000080)
1383 #define SSI_RCR_RFEN1                   (0x00000100)
1384 #define SSI_RCR_RXBIT0                  (0x00000200)
1385 #define SSI_RCR_RXEXT                   (0x00000400)
1386
1387 /* Bit definitions and macros for CCR */
1388 #define SSI_CCR_PM(x)                   (((x)&0x000000FF))
1389 #define SSI_CCR_DC(x)                   (((x)&0x0000001F)<<8)
1390 #define SSI_CCR_WL(x)                   (((x)&0x0000000F)<<13)
1391 #define SSI_CCR_PSR                     (0x00020000)
1392 #define SSI_CCR_DIV2                    (0x00040000)
1393
1394 /* Bit definitions and macros for FCSR */
1395 #define SSI_FCSR_TFWM0(x)               (((x)&0x0000000F))
1396 #define SSI_FCSR_RFWM0(x)               (((x)&0x0000000F)<<4)
1397 #define SSI_FCSR_TFCNT0(x)              (((x)&0x0000000F)<<8)
1398 #define SSI_FCSR_RFCNT0(x)              (((x)&0x0000000F)<<12)
1399 #define SSI_FCSR_TFWM1(x)               (((x)&0x0000000F)<<16)
1400 #define SSI_FCSR_RFWM1(x)               (((x)&0x0000000F)<<20)
1401 #define SSI_FCSR_TFCNT1(x)              (((x)&0x0000000F)<<24)
1402 #define SSI_FCSR_RFCNT1(x)              (((x)&0x0000000F)<<28)
1403
1404 /* Bit definitions and macros for ACR */
1405 #define SSI_ACR_AC97EN                  (0x00000001)
1406 #define SSI_ACR_FV                      (0x00000002)
1407 #define SSI_ACR_TIF                     (0x00000004)
1408 #define SSI_ACR_RD                      (0x00000008)
1409 #define SSI_ACR_WR                      (0x00000010)
1410 #define SSI_ACR_FRDIV(x)                (((x)&0x0000003F)<<5)
1411
1412 /* Bit definitions and macros for ACADD */
1413 #define SSI_ACADD_SSI_ACADD(x)          (((x)&0x0007FFFF))
1414
1415 /* Bit definitions and macros for ACDAT */
1416 #define SSI_ACDAT_SSI_ACDAT(x)          (((x)&0x0007FFFF))
1417
1418 /* Bit definitions and macros for ATAG */
1419 #define SSI_ATAG_DDI_ATAG(x)            (((x)&0x0000FFFF))
1420
1421 /*********************************************************************
1422 * Phase Locked Loop (PLL)
1423 *********************************************************************/
1424
1425 /* Bit definitions and macros for PCR */
1426 #define PLL_PCR_OUTDIV1(x)              (((x)&0x0000000F))      /* Output divider for CPU clock frequency */
1427 #define PLL_PCR_OUTDIV2(x)              (((x)&0x0000000F)<<4)   /* Output divider for internal bus clock frequency */
1428 #define PLL_PCR_OUTDIV3(x)              (((x)&0x0000000F)<<8)   /* Output divider for Flexbus clock frequency */
1429 #define PLL_PCR_OUTDIV4(x)              (((x)&0x0000000F)<<12)  /* Output divider for PCI clock frequency */
1430 #define PLL_PCR_OUTDIV5(x)              (((x)&0x0000000F)<<16)  /* Output divider for USB clock frequency */
1431 #define PLL_PCR_PFDR(x)                 (((x)&0x000000FF)<<24)  /* Feedback divider for VCO frequency */
1432 #define PLL_PCR_PFDR_MASK               (0x000F0000)
1433 #define PLL_PCR_OUTDIV5_MASK            (0x000F0000)
1434 #define PLL_PCR_OUTDIV4_MASK            (0x0000F000)
1435 #define PLL_PCR_OUTDIV3_MASK            (0x00000F00)
1436 #define PLL_PCR_OUTDIV2_MASK            (0x000000F0)
1437 #define PLL_PCR_OUTDIV1_MASK            (0x0000000F)
1438
1439 /* Bit definitions and macros for PSR */
1440 #define PLL_PSR_LOCKS                   (0x00000001)    /* PLL lost lock - sticky */
1441 #define PLL_PSR_LOCK                    (0x00000002)    /* PLL lock status */
1442 #define PLL_PSR_LOLIRQ                  (0x00000004)    /* PLL loss-of-lock interrupt enable */
1443 #define PLL_PSR_LOLRE                   (0x00000008)    /* PLL loss-of-lock reset enable */
1444
1445 /*********************************************************************
1446 * PCI
1447 *********************************************************************/
1448
1449 /* Bit definitions and macros for SCR */
1450 #define PCI_SCR_PE                      (0x80000000)    /* Parity Error detected */
1451 #define PCI_SCR_SE                      (0x40000000)    /* System error signalled */
1452 #define PCI_SCR_MA                      (0x20000000)    /* Master aboart received */
1453 #define PCI_SCR_TR                      (0x10000000)    /* Target abort received */
1454 #define PCI_SCR_TS                      (0x08000000)    /* Target abort signalled */
1455 #define PCI_SCR_DT                      (0x06000000)    /* PCI_DEVSEL timing */
1456 #define PCI_SCR_DP                      (0x01000000)    /* Master data parity err */
1457 #define PCI_SCR_FC                      (0x00800000)    /* Fast back-to-back */
1458 #define PCI_SCR_R                       (0x00400000)    /* Reserved */
1459 #define PCI_SCR_66M                     (0x00200000)    /* 66Mhz */
1460 #define PCI_SCR_C                       (0x00100000)    /* Capabilities list */
1461 #define PCI_SCR_F                       (0x00000200)    /* Fast back-to-back enable */
1462 #define PCI_SCR_S                       (0x00000100)    /* SERR enable */
1463 #define PCI_SCR_ST                      (0x00000080)    /* Addr and Data stepping */
1464 #define PCI_SCR_PER                     (0x00000040)    /* Parity error response */
1465 #define PCI_SCR_V                       (0x00000020)    /* VGA palette snoop enable */
1466 #define PCI_SCR_MW                      (0x00000010)    /* Memory write and invalidate enable */
1467 #define PCI_SCR_SP                      (0x00000008)    /* Special cycle monitor or ignore */
1468 #define PCI_SCR_B                       (0x00000004)    /* Bus master enable */
1469 #define PCI_SCR_M                       (0x00000002)    /* Memory access control */
1470 #define PCI_SCR_IO                      (0x00000001)    /* I/O access control */
1471
1472 #define PCI_CR1_BIST(x)                 ((x & 0xFF) << 24)      /* Built in self test */
1473 #define PCI_CR1_HDR(x)                  ((x & 0xFF) << 16)      /* Header type */
1474 #define PCI_CR1_LTMR(x)                 ((x & 0xF8) << 8)       /* Latency timer */
1475 #define PCI_CR1_CLS(x)                  (x & 0x0F)      /* Cache line size */
1476
1477 #define PCI_BAR_BAR0(x)                 (x & 0xFFFC0000)
1478 #define PCI_BAR_BAR1(x)                 (x & 0xFFF00000)
1479 #define PCI_BAR_BAR2(x)                 (x & 0xFFC00000)
1480 #define PCI_BAR_BAR3(x)                 (x & 0xFF000000)
1481 #define PCI_BAR_BAR4(x)                 (x & 0xF8000000)
1482 #define PCI_BAR_BAR5(x)                 (x & 0xE0000000)
1483 #define PCI_BAR_PREF                    (0x00000004)    /* Prefetchable access */
1484 #define PCI_BAR_RANGE                   (0x00000002)    /* Fixed to 00 */
1485 #define PCI_BAR_IO_M                    (0x00000001)    /* IO / memory space */
1486
1487 #define PCI_CR2_MAXLAT(x)               ((x & 0xFF) << 24)      /* Maximum latency */
1488 #define PCI_CR2_MINGNT(x)               ((x & 0xFF) << 16)      /* Minimum grant */
1489 #define PCI_CR2_INTPIN(x)               ((x & 0xFF) << 8)       /* Interrupt Pin */
1490 #define PCI_CR2_INTLIN(x)               (x & 0xFF)      /* Interrupt Line */
1491
1492 #define PCI_GSCR_DRD                    (0x80000000)    /* Delayed read discarded */
1493 #define PCI_GSCR_PE                     (0x20000000)    /* PCI_PERR detected */
1494 #define PCI_GSCR_SE                     (0x10000000)    /* SERR detected */
1495 #define PCI_GSCR_ER                     (0x08000000)    /* Error response detected */
1496 #define PCI_GSCR_DRDE                   (0x00008000)    /* Delayed read discarded enable */
1497 #define PCI_GSCR_PEE                    (0x00002000)    /* PERR detected interrupt enable */
1498 #define PCI_GSCR_SEE                    (0x00001000)    /* SERR detected interrupt enable */
1499 #define PCI_GSCR_PR                     (0x00000001)    /* PCI reset */
1500
1501 #define PCI_TCR1_LD                     (0x01000000)    /* Latency rule disable */
1502 #define PCI_TCR1_PID                    (0x00020000)    /* Prefetch invalidate and disable */
1503 #define PCI_TCR1_P                      (0x00010000)    /* Prefetch reads */
1504 #define PCI_TCR1_WCD                    (0x00000100)    /* Write combine disable */
1505
1506 #define PCI_TCR1_B5E                    (0x00002000)    /*  */
1507 #define PCI_TCR1_B4E                    (0x00001000)    /*  */
1508 #define PCI_TCR1_B3E                    (0x00000800)    /*  */
1509 #define PCI_TCR1_B2E                    (0x00000400)    /*  */
1510 #define PCI_TCR1_B1E                    (0x00000200)    /*  */
1511 #define PCI_TCR1_B0E                    (0x00000100)    /*  */
1512 #define PCI_TCR1_CR                     (0x00000001)    /*  */
1513
1514 #define PCI_TBATR_BAT(x)                ((x & 0xFFF) << 20)
1515 #define PCI_TBATR_EN                    (0x00000001)    /* Enable */
1516
1517 #define PCI_IWCR_W0C_IO                 (0x08000000)    /* Windows Maps to PCI I/O */
1518 #define PCI_IWCR_W0C_PRC_RDMUL          (0x04000000)    /* PCI Memory Read multiple */
1519 #define PCI_IWCR_W0C_PRC_RDLN           (0x02000000)    /* PCI Memory Read line */
1520 #define PCI_IWCR_W0C_PRC_RD             (0x00000000)    /* PCI Memory Read */
1521 #define PCI_IWCR_W0C_EN                 (0x01000000)    /* Enable - Register initialize */
1522 #define PCI_IWCR_W1C_IO                 (0x00080000)    /* Windows Maps to PCI I/O */
1523 #define PCI_IWCR_W1C_PRC_RDMUL          (0x00040000)    /* PCI Memory Read multiple */
1524 #define PCI_IWCR_W1C_PRC_RDLN           (0x00020000)    /* PCI Memory Read line */
1525 #define PCI_IWCR_W1C_PRC_RD             (0x00000000)    /* PCI Memory Read */
1526 #define PCI_IWCR_W1C_EN                 (0x00010000)    /* Enable - Register initialize */
1527 #define PCI_IWCR_W2C_IO                 (0x00000800)    /* Windows Maps to PCI I/O */
1528 #define PCI_IWCR_W2C_PRC_RDMUL          (0x00000400)    /* PCI Memory Read multiple */
1529 #define PCI_IWCR_W2C_PRC_RDLN           (0x00000200)    /* PCI Memory Read line */
1530 #define PCI_IWCR_W2C_PRC_RD             (0x00000000)    /* PCI Memory Read */
1531 #define PCI_IWCR_W2C_EN                 (0x00000100)    /* Enable - Register initialize */
1532
1533 #define PCI_ICR_REE                     (0x04000000)    /* Retry error enable */
1534 #define PCI_ICR_IAE                     (0x02000000)    /* Initiator abort enable */
1535 #define PCI_ICR_TAE                     (0x01000000)    /* Target abort enable */
1536
1537 #define PCI_IDR_DEVID                   (
1538
1539 /********************************************************************/
1540
1541 #endif                          /* __MCF5445X__ */