include/asm-mips/vr4181/irq.h

   1 /*
   2  * Macros for vr4181 IRQ numbers.
   3  *
   4  * Copyright (C) 2001 MontaVista Software Inc.
   5  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  */
  13
  14 /*
  15  * Strategy:
  16  *
  17  * Vr4181 has conceptually three levels of interrupt controllers:
  18  *  1. the CPU itself with 8 intr level.
  19  *  2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs
  20  *  3. GPIO interrupts : forwarding external interrupts to sys intr controller
  21  */
  22
  23 /* decide the irq block assignment */
  24 #define VR4181_NUM_CPU_IRQ      8
  25 #define VR4181_NUM_SYS_IRQ      32
  26 #define VR4181_NUM_GPIO_IRQ     16
  27
  28 #define VR4181_IRQ_BASE         0
  29
  30 #define VR4181_CPU_IRQ_BASE     VR4181_IRQ_BASE
  31 #define VR4181_SYS_IRQ_BASE     (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ)
  32 #define VR4181_GPIO_IRQ_BASE    (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ)
  33
  34 /* CPU interrupts */
  35
  36 /*
  37    IP0 - Software interrupt
  38    IP1 - Software interrupt
  39    IP2 - All but battery, high speed modem, and real time clock
  40    IP3 - RTC Long1 (system timer)
  41    IP4 - RTC Long2
  42    IP5 - High Speed Modem (unused on VR4181)
  43    IP6 - Unused
  44    IP7 - Timer interrupt from CPO_COMPARE
  45 */
  46
  47 #define VR4181_IRQ_SW1       (VR4181_CPU_IRQ_BASE + 0)
  48 #define VR4181_IRQ_SW2       (VR4181_CPU_IRQ_BASE + 1)
  49 #define VR4181_IRQ_INT0      (VR4181_CPU_IRQ_BASE + 2)
  50 #define VR4181_IRQ_INT1      (VR4181_CPU_IRQ_BASE + 3)
  51 #define VR4181_IRQ_INT2      (VR4181_CPU_IRQ_BASE + 4)
  52 #define VR4181_IRQ_INT3      (VR4181_CPU_IRQ_BASE + 5)
  53 #define VR4181_IRQ_INT4      (VR4181_CPU_IRQ_BASE + 6)
  54 #define VR4181_IRQ_TIMER     (VR4181_CPU_IRQ_BASE + 7)
  55
  56
  57 /* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */
  58
  59 /*
  60    IP2 - same as VR4181_IRQ_INT1
  61    IP8 - This is a cascade to GPIO IRQ's. Do not use.
  62    IP16 - same as VR4181_IRQ_INT2
  63    IP18 - CompactFlash
  64 */
  65
  66 #define VR4181_IRQ_BATTERY   (VR4181_SYS_IRQ_BASE + 0)
  67 #define VR4181_IRQ_POWER     (VR4181_SYS_IRQ_BASE + 1)
  68 #define VR4181_IRQ_RTCL1     (VR4181_SYS_IRQ_BASE + 2)
  69 #define VR4181_IRQ_ETIMER    (VR4181_SYS_IRQ_BASE + 3)
  70 #define VR4181_IRQ_RFU12     (VR4181_SYS_IRQ_BASE + 4)
  71 #define VR4181_IRQ_PIU       (VR4181_SYS_IRQ_BASE + 5)
  72 #define VR4181_IRQ_AIU       (VR4181_SYS_IRQ_BASE + 6)
  73 #define VR4181_IRQ_KIU       (VR4181_SYS_IRQ_BASE + 7)
  74 #define VR4181_IRQ_GIU       (VR4181_SYS_IRQ_BASE + 8)
  75 #define VR4181_IRQ_SIU       (VR4181_SYS_IRQ_BASE + 9)
  76 #define VR4181_IRQ_RFU18     (VR4181_SYS_IRQ_BASE + 10)
  77 #define VR4181_IRQ_SOFT      (VR4181_SYS_IRQ_BASE + 11)
  78 #define VR4181_IRQ_RFU20     (VR4181_SYS_IRQ_BASE + 12)
  79 #define VR4181_IRQ_DOZEPIU   (VR4181_SYS_IRQ_BASE + 13)
  80 #define VR4181_IRQ_RFU22     (VR4181_SYS_IRQ_BASE + 14)
  81 #define VR4181_IRQ_RFU23     (VR4181_SYS_IRQ_BASE + 15)
  82 #define VR4181_IRQ_RTCL2     (VR4181_SYS_IRQ_BASE + 16)
  83 #define VR4181_IRQ_LED       (VR4181_SYS_IRQ_BASE + 17)
  84 #define VR4181_IRQ_ECU       (VR4181_SYS_IRQ_BASE + 18)
  85 #define VR4181_IRQ_CSU       (VR4181_SYS_IRQ_BASE + 19)
  86 #define VR4181_IRQ_USB       (VR4181_SYS_IRQ_BASE + 20)
  87 #define VR4181_IRQ_DMA       (VR4181_SYS_IRQ_BASE + 21)
  88 #define VR4181_IRQ_LCD       (VR4181_SYS_IRQ_BASE + 22)
  89 #define VR4181_IRQ_RFU31     (VR4181_SYS_IRQ_BASE + 23)
  90 #define VR4181_IRQ_RFU32     (VR4181_SYS_IRQ_BASE + 24)
  91 #define VR4181_IRQ_RFU33     (VR4181_SYS_IRQ_BASE + 25)
  92 #define VR4181_IRQ_RFU34     (VR4181_SYS_IRQ_BASE + 26)
  93 #define VR4181_IRQ_RFU35     (VR4181_SYS_IRQ_BASE + 27)
  94 #define VR4181_IRQ_RFU36     (VR4181_SYS_IRQ_BASE + 28)
  95 #define VR4181_IRQ_RFU37     (VR4181_SYS_IRQ_BASE + 29)
  96 #define VR4181_IRQ_RFU38     (VR4181_SYS_IRQ_BASE + 30)
  97 #define VR4181_IRQ_RFU39     (VR4181_SYS_IRQ_BASE + 31)
  98
  99 /* Cascaded from VR4181_IRQ_GIU */
 100 #define VR4181_IRQ_GPIO0     (VR4181_GPIO_IRQ_BASE + 0)
 101 #define VR4181_IRQ_GPIO1     (VR4181_GPIO_IRQ_BASE + 1)
 102 #define VR4181_IRQ_GPIO2     (VR4181_GPIO_IRQ_BASE + 2)
 103 #define VR4181_IRQ_GPIO3     (VR4181_GPIO_IRQ_BASE + 3)
 104 #define VR4181_IRQ_GPIO4     (VR4181_GPIO_IRQ_BASE + 4)
 105 #define VR4181_IRQ_GPIO5     (VR4181_GPIO_IRQ_BASE + 5)
 106 #define VR4181_IRQ_GPIO6     (VR4181_GPIO_IRQ_BASE + 6)
 107 #define VR4181_IRQ_GPIO7     (VR4181_GPIO_IRQ_BASE + 7)
 108 #define VR4181_IRQ_GPIO8     (VR4181_GPIO_IRQ_BASE + 8)
 109 #define VR4181_IRQ_GPIO9     (VR4181_GPIO_IRQ_BASE + 9)
 110 #define VR4181_IRQ_GPIO10    (VR4181_GPIO_IRQ_BASE + 10)
 111 #define VR4181_IRQ_GPIO11    (VR4181_GPIO_IRQ_BASE + 11)
 112 #define VR4181_IRQ_GPIO12    (VR4181_GPIO_IRQ_BASE + 12)
 113 #define VR4181_IRQ_GPIO13    (VR4181_GPIO_IRQ_BASE + 13)
 114 #define VR4181_IRQ_GPIO14    (VR4181_GPIO_IRQ_BASE + 14)
 115 #define VR4181_IRQ_GPIO15    (VR4181_GPIO_IRQ_BASE + 15)
 116
 117
 118 // Alternative to above GPIO IRQ defines
 119 #define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
 120
 121 #define VR4181_IRQ_MAX       (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
 122                               VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)