include/asm-ppc/4xx_pcie.h

   1 /*
   2  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
   3  * Roland Dreier <rolandd@cisco.com>
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of  the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <ppc4xx.h>
  12 #ifndef __4XX_PCIE_H
  13 #define __4XX_PCIE_H
  14
  15 #define DCRN_SDR0_CFGADDR       0x00e
  16 #define DCRN_SDR0_CFGDATA       0x00f
  17
  18 #if defined(CONFIG_440SPE)
  19 #define CFG_PCIE_NR_PORTS       3
  20
  21 #define CFG_PCIE_ADDR_HIGH      0x0000000d
  22
  23 #define DCRN_PCIE0_BASE         0x100
  24 #define DCRN_PCIE1_BASE         0x120
  25 #define DCRN_PCIE2_BASE         0x140
  26
  27 #define PCIE0_SDR               0x300
  28 #define PCIE1_SDR               0x340
  29 #define PCIE2_SDR               0x370
  30 #endif
  31
  32 #if defined(CONFIG_405EX)
  33 #define CFG_PCIE_NR_PORTS       2
  34
  35 #define CFG_PCIE_ADDR_HIGH      0x00000000
  36
  37 #define DCRN_PCIE0_BASE         0x040
  38 #define DCRN_PCIE1_BASE         0x060
  39
  40 #define PCIE0_SDR               0x400
  41 #define PCIE1_SDR               0x440
  42 #endif
  43
  44 #define PCIE0                   DCRN_PCIE0_BASE
  45 #define PCIE1                   DCRN_PCIE1_BASE
  46 #define PCIE2                   DCRN_PCIE2_BASE
  47
  48 #define DCRN_PEGPL_CFGBAH(base)         (base + 0x00)
  49 #define DCRN_PEGPL_CFGBAL(base)         (base + 0x01)
  50 #define DCRN_PEGPL_CFGMSK(base)         (base + 0x02)
  51 #define DCRN_PEGPL_MSGBAH(base)         (base + 0x03)
  52 #define DCRN_PEGPL_MSGBAL(base)         (base + 0x04)
  53 #define DCRN_PEGPL_MSGMSK(base)         (base + 0x05)
  54 #define DCRN_PEGPL_OMR1BAH(base)        (base + 0x06)
  55 #define DCRN_PEGPL_OMR1BAL(base)        (base + 0x07)
  56 #define DCRN_PEGPL_OMR1MSKH(base)       (base + 0x08)
  57 #define DCRN_PEGPL_OMR1MSKL(base)       (base + 0x09)
  58 #define DCRN_PEGPL_REGBAH(base)         (base + 0x12)
  59 #define DCRN_PEGPL_REGBAL(base)         (base + 0x13)
  60 #define DCRN_PEGPL_REGMSK(base)         (base + 0x14)
  61 #define DCRN_PEGPL_SPECIAL(base)        (base + 0x15)
  62 #define DCRN_PEGPL_CFG(base)            (base + 0x16)
  63
  64 /*
  65  * System DCRs (SDRs)
  66  */
  67 #define PESDR0_PLLLCT1          0x03a0
  68 #define PESDR0_PLLLCT2          0x03a1
  69 #define PESDR0_PLLLCT3          0x03a2
  70
  71 /* common regs, at least for 405EX and 440SPe */
  72 #define SDRN_PESDR_UTLSET1(n)           (sdr_base(n) + 0x00)
  73 #define SDRN_PESDR_UTLSET2(n)           (sdr_base(n) + 0x01)
  74 #define SDRN_PESDR_DLPSET(n)            (sdr_base(n) + 0x02)
  75 #define SDRN_PESDR_LOOP(n)              (sdr_base(n) + 0x03)
  76 #define SDRN_PESDR_RCSSET(n)            (sdr_base(n) + 0x04)
  77 #define SDRN_PESDR_RCSSTS(n)            (sdr_base(n) + 0x05)
  78
  79 #if defined(CONFIG_440SPE)
  80 #define SDRN_PESDR_HSSL0SET1(n)         (sdr_base(n) + 0x06)
  81 #define SDRN_PESDR_HSSL0SET2(n)         (sdr_base(n) + 0x07)
  82 #define SDRN_PESDR_HSSL0STS(n)          (sdr_base(n) + 0x08)
  83 #define SDRN_PESDR_HSSL1SET1(n)         (sdr_base(n) + 0x09)
  84 #define SDRN_PESDR_HSSL1SET2(n)         (sdr_base(n) + 0x0a)
  85 #define SDRN_PESDR_HSSL1STS(n)          (sdr_base(n) + 0x0b)
  86 #define SDRN_PESDR_HSSL2SET1(n)         (sdr_base(n) + 0x0c)
  87 #define SDRN_PESDR_HSSL2SET2(n)         (sdr_base(n) + 0x0d)
  88 #define SDRN_PESDR_HSSL2STS(n)          (sdr_base(n) + 0x0e)
  89 #define SDRN_PESDR_HSSL3SET1(n)         (sdr_base(n) + 0x0f)
  90 #define SDRN_PESDR_HSSL3SET2(n)         (sdr_base(n) + 0x10)
  91 #define SDRN_PESDR_HSSL3STS(n)          (sdr_base(n) + 0x11)
  92
  93 #define PESDR0_UTLSET1          0x0300
  94 #define PESDR0_UTLSET2          0x0301
  95 #define PESDR0_DLPSET           0x0302
  96 #define PESDR0_LOOP             0x0303
  97 #define PESDR0_RCSSET           0x0304
  98 #define PESDR0_RCSSTS           0x0305
  99 #define PESDR0_HSSL0SET1        0x0306
 100 #define PESDR0_HSSL0SET2        0x0307
 101 #define PESDR0_HSSL0STS         0x0308
 102 #define PESDR0_HSSL1SET1        0x0309
 103 #define PESDR0_HSSL1SET2        0x030a
 104 #define PESDR0_HSSL1STS         0x030b
 105 #define PESDR0_HSSL2SET1        0x030c
 106 #define PESDR0_HSSL2SET2        0x030d
 107 #define PESDR0_HSSL2STS         0x030e
 108 #define PESDR0_HSSL3SET1        0x030f
 109 #define PESDR0_HSSL3SET2        0x0310
 110 #define PESDR0_HSSL3STS         0x0311
 111 #define PESDR0_HSSL4SET1        0x0312
 112 #define PESDR0_HSSL4SET2        0x0313
 113 #define PESDR0_HSSL4STS         0x0314
 114 #define PESDR0_HSSL5SET1        0x0315
 115 #define PESDR0_HSSL5SET2        0x0316
 116 #define PESDR0_HSSL5STS         0x0317
 117 #define PESDR0_HSSL6SET1        0x0318
 118 #define PESDR0_HSSL6SET2        0x0319
 119 #define PESDR0_HSSL6STS         0x031a
 120 #define PESDR0_HSSL7SET1        0x031b
 121 #define PESDR0_HSSL7SET2        0x031c
 122 #define PESDR0_HSSL7STS         0x031d
 123 #define PESDR0_HSSCTLSET        0x031e
 124 #define PESDR0_LANE_ABCD        0x031f
 125 #define PESDR0_LANE_EFGH        0x0320
 126
 127 #define PESDR1_UTLSET1          0x0340
 128 #define PESDR1_UTLSET2          0x0341
 129 #define PESDR1_DLPSET           0x0342
 130 #define PESDR1_LOOP             0x0343
 131 #define PESDR1_RCSSET           0x0344
 132 #define PESDR1_RCSSTS           0x0345
 133 #define PESDR1_HSSL0SET1        0x0346
 134 #define PESDR1_HSSL0SET2        0x0347
 135 #define PESDR1_HSSL0STS         0x0348
 136 #define PESDR1_HSSL1SET1        0x0349
 137 #define PESDR1_HSSL1SET2        0x034a
 138 #define PESDR1_HSSL1STS         0x034b
 139 #define PESDR1_HSSL2SET1        0x034c
 140 #define PESDR1_HSSL2SET2        0x034d
 141 #define PESDR1_HSSL2STS         0x034e
 142 #define PESDR1_HSSL3SET1        0x034f
 143 #define PESDR1_HSSL3SET2        0x0350
 144 #define PESDR1_HSSL3STS         0x0351
 145 #define PESDR1_HSSCTLSET        0x0352
 146 #define PESDR1_LANE_ABCD        0x0353
 147
 148 #define PESDR2_UTLSET1          0x0370
 149 #define PESDR2_UTLSET2          0x0371
 150 #define PESDR2_DLPSET           0x0372
 151 #define PESDR2_LOOP             0x0373
 152 #define PESDR2_RCSSET           0x0374
 153 #define PESDR2_RCSSTS           0x0375
 154 #define PESDR2_HSSL0SET1        0x0376
 155 #define PESDR2_HSSL0SET2        0x0377
 156 #define PESDR2_HSSL0STS         0x0378
 157 #define PESDR2_HSSL1SET1        0x0379
 158 #define PESDR2_HSSL1SET2        0x037a
 159 #define PESDR2_HSSL1STS         0x037b
 160 #define PESDR2_HSSL2SET1        0x037c
 161 #define PESDR2_HSSL2SET2        0x037d
 162 #define PESDR2_HSSL2STS         0x037e
 163 #define PESDR2_HSSL3SET1        0x037f
 164 #define PESDR2_HSSL3SET2        0x0380
 165 #define PESDR2_HSSL3STS         0x0381
 166 #define PESDR2_HSSCTLSET        0x0382
 167 #define PESDR2_LANE_ABCD        0x0383
 168
 169 #elif defined(CONFIG_405EX)
 170
 171 #define SDRN_PESDR_PHYSET1(n)           (sdr_base(n) + 0x06)
 172 #define SDRN_PESDR_PHYSET2(n)           (sdr_base(n) + 0x07)
 173 #define SDRN_PESDR_BIST(n)              (sdr_base(n) + 0x08)
 174 #define SDRN_PESDR_LPB(n)               (sdr_base(n) + 0x0b)
 175 #define SDRN_PESDR_PHYSTA(n)            (sdr_base(n) + 0x0c)
 176
 177 #define PESDR0_UTLSET1          0x0400
 178 #define PESDR0_UTLSET2          0x0401
 179 #define PESDR0_DLPSET           0x0402
 180 #define PESDR0_LOOP             0x0403
 181 #define PESDR0_RCSSET           0x0404
 182 #define PESDR0_RCSSTS           0x0405
 183 #define PESDR0_PHYSET1          0x0406
 184 #define PESDR0_PHYSET2          0x0407
 185 #define PESDR0_BIST             0x0408
 186 #define PESDR0_LPB              0x040B
 187 #define PESDR0_PHYSTA           0x040C
 188
 189 #define PESDR1_UTLSET1          0x0440
 190 #define PESDR1_UTLSET2          0x0441
 191 #define PESDR1_DLPSET           0x0442
 192 #define PESDR1_LOOP             0x0443
 193 #define PESDR1_RCSSET           0x0444
 194 #define PESDR1_RCSSTS           0x0445
 195 #define PESDR1_PHYSET1          0x0446
 196 #define PESDR1_PHYSET2          0x0447
 197 #define PESDR1_BIST             0x0448
 198 #define PESDR1_LPB              0x044B
 199 #define PESDR1_PHYSTA           0x044C
 200
 201 #endif
 202
 203 /*
 204  * UTL register offsets
 205  */
 206 #define PEUTL_PBCTL             0x00
 207 #define PEUTL_PBBSZ             0x20
 208 #define PEUTL_OPDBSZ            0x68
 209 #define PEUTL_IPHBSZ            0x70
 210 #define PEUTL_IPDBSZ            0x78
 211 #define PEUTL_OUTTR             0x90
 212 #define PEUTL_INTR              0x98
 213 #define PEUTL_PCTL              0xa0
 214 #define PEUTL_RCSTA             0xb0
 215 #define PEUTL_RCIRQEN           0xb8
 216
 217 /*
 218  * Config space register offsets
 219  */
 220 #define PECFG_BAR0LMPA          0x210
 221 #define PECFG_BAR0HMPA          0x214
 222 #define PECFG_BAR1MPA           0x218
 223 #define PECFG_BAR2LMPA          0x220
 224 #define PECFG_BAR2HMPA          0x224
 225
 226 #define PECFG_PIMEN             0x33c
 227 #define PECFG_PIM0LAL           0x340
 228 #define PECFG_PIM0LAH           0x344
 229 #define PECFG_PIM1LAL           0x348
 230 #define PECFG_PIM1LAH           0x34c
 231 #define PECFG_PIM01SAL          0x350
 232 #define PECFG_PIM01SAH          0x354
 233
 234 #define PECFG_POM0LAL           0x380
 235 #define PECFG_POM0LAH           0x384
 236
 237 #define SDR_READ(offset) ({\
 238         mtdcr(DCRN_SDR0_CFGADDR, offset); \
 239         mfdcr(DCRN_SDR0_CFGDATA);})
 240
 241 #define SDR_WRITE(offset, data) ({\
 242         mtdcr(DCRN_SDR0_CFGADDR, offset); \
 243         mtdcr(DCRN_SDR0_CFGDATA,data);})
 244
 245 #define GPL_DMER_MASK_DISA      0x02000000
 246
 247 #define U64_TO_U32_LOW(val)     ((u32)((val) & 0x00000000ffffffffULL))
 248 #define U64_TO_U32_HIGH(val)    ((u32)((val) >> 32))
 249
 250 /*
 251  * Prototypes
 252  */
 253 int ppc4xx_init_pcie(void);
 254 int ppc4xx_init_pcie_rootport(int port);
 255 int ppc4xx_init_pcie_endport(int port);
 256 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
 257 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
 258 int pcie_hose_scan(struct pci_controller *hose, int bus);
 259
 260 /*
 261  * Function to determine root port or endport from env variable.
 262  */
 263 static inline int is_end_point(int port)
 264 {
 265         char s[10], *tk;
 266         char *pcie_mode = getenv("pcie_mode");
 267
 268         if (pcie_mode == NULL)
 269                 return 0;
 270
 271         strcpy(s, pcie_mode);
 272         tk = strtok(s, ":");
 273
 274         switch (port) {
 275         case 0:
 276                 if (tk != NULL) {
 277                         if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
 278                                 return 1;
 279                         else
 280                                 return 0;
 281                 }
 282                 else
 283                         return 0;
 284
 285         case 1:
 286                 tk = strtok(NULL, ":");
 287                 if (tk != NULL) {
 288                         if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
 289                                 return 1;
 290                         else
 291                                 return 0;
 292                 }
 293                 else
 294                         return 0;
 295
 296         case 2:
 297                 tk = strtok(NULL, ":");
 298                 if (tk != NULL)
 299                         tk = strtok(NULL, ":");
 300                 if (tk != NULL) {
 301                         if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
 302                                 return 1;
 303                         else
 304                                 return 0;
 305                 }
 306                 else
 307                         return 0;
 308         }
 309
 310         return 0;
 311 }
 312
 313 static inline void mdelay(int n)
 314 {
 315         u32 ms = n;
 316
 317         while (ms--)
 318                 udelay(1000);
 319 }
 320
 321 static inline u32 sdr_base(int port)
 322 {
 323         switch (port) {
 324         default:        /* to satisfy compiler */
 325         case 0:
 326                 return PCIE0_SDR;
 327         case 1:
 328                 return PCIE1_SDR;
 329 #if CFG_PCIE_NR_PORTS > 2
 330         case 2:
 331                 return PCIE2_SDR;
 332 #endif
 333         }
 334 }
 335
 336 #endif /* __4XX_PCIE_H */