include/asm-ppc/cpm_8260.h

   1
   2 /*
   3  * MPC8260 Communication Processor Module.
   4  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
   5  *
   6  * This file contains structures and information for the communication
   7  * processor channels found in the dual port RAM or parameter RAM.
   8  * All CPM control and status is available through the MPC8260 internal
   9  * memory map.  See immap.h for details.
  10  */
  11 #ifndef __CPM_82XX__
  12 #define __CPM_82XX__
  13
  14 #include <asm/immap_8260.h>
  15
  16 /* CPM Command register.
  17 */
  18 #define CPM_CR_RST      ((uint)0x80000000)
  19 #define CPM_CR_PAGE     ((uint)0x7c000000)
  20 #define CPM_CR_SBLOCK   ((uint)0x03e00000)
  21 #define CPM_CR_FLG      ((uint)0x00010000)
  22 #define CPM_CR_MCN      ((uint)0x00003fc0)
  23 #define CPM_CR_OPCODE   ((uint)0x0000000f)
  24
  25 /* Device sub-block and page codes.
  26 */
  27 #define CPM_CR_SCC1_SBLOCK      (0x04)
  28 #define CPM_CR_SCC2_SBLOCK      (0x05)
  29 #define CPM_CR_SCC3_SBLOCK      (0x06)
  30 #define CPM_CR_SCC4_SBLOCK      (0x07)
  31 #define CPM_CR_SMC1_SBLOCK      (0x08)
  32 #define CPM_CR_SMC2_SBLOCK      (0x09)
  33 #define CPM_CR_SPI_SBLOCK       (0x0a)
  34 #define CPM_CR_I2C_SBLOCK       (0x0b)
  35 #define CPM_CR_TIMER_SBLOCK     (0x0f)
  36 #define CPM_CR_RAND_SBLOCK      (0x0e)
  37 #define CPM_CR_FCC1_SBLOCK      (0x10)
  38 #define CPM_CR_FCC2_SBLOCK      (0x11)
  39 #define CPM_CR_FCC3_SBLOCK      (0x12)
  40 #define CPM_CR_IDMA1_SBLOCK     (0x14)
  41 #define CPM_CR_IDMA2_SBLOCK     (0x15)
  42 #define CPM_CR_IDMA3_SBLOCK     (0x16)
  43 #define CPM_CR_IDMA4_SBLOCK     (0x17)
  44 #define CPM_CR_MCC1_SBLOCK      (0x1c)
  45
  46 #define CPM_CR_SCC1_PAGE        (0x00)
  47 #define CPM_CR_SCC2_PAGE        (0x01)
  48 #define CPM_CR_SCC3_PAGE        (0x02)
  49 #define CPM_CR_SCC4_PAGE        (0x03)
  50 #define CPM_CR_SMC1_PAGE        (0x07)
  51 #define CPM_CR_SMC2_PAGE        (0x08)
  52 #define CPM_CR_SPI_PAGE         (0x09)
  53 #define CPM_CR_I2C_PAGE         (0x0a)
  54 #define CPM_CR_TIMER_PAGE       (0x0a)
  55 #define CPM_CR_RAND_PAGE        (0x0a)
  56 #define CPM_CR_FCC1_PAGE        (0x04)
  57 #define CPM_CR_FCC2_PAGE        (0x05)
  58 #define CPM_CR_FCC3_PAGE        (0x06)
  59 #define CPM_CR_IDMA1_PAGE       (0x07)
  60 #define CPM_CR_IDMA2_PAGE       (0x08)
  61 #define CPM_CR_IDMA3_PAGE       (0x09)
  62 #define CPM_CR_IDMA4_PAGE       (0x0a)
  63 #define CPM_CR_MCC1_PAGE        (0x07)
  64 #define CPM_CR_MCC2_PAGE        (0x08)
  65
  66 /* Some opcodes (there are more...later)
  67 */
  68 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
  69 #define CPM_CR_INIT_RX          ((ushort)0x0001)
  70 #define CPM_CR_INIT_TX          ((ushort)0x0002)
  71 #define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  72 #define CPM_CR_STOP_TX          ((ushort)0x0004)
  73 #define CPM_CR_RESTART_TX       ((ushort)0x0006)
  74 #define CPM_CR_SET_GADDR        ((ushort)0x0008)
  75
  76 #define mk_cr_cmd(PG, SBC, MCN, OP) \
  77         ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
  78
  79 /* Dual Port RAM addresses.  The first 16K is available for almost
  80  * any CPM use, so we put the BDs there.  The first 128 bytes are
  81  * used for SMC1 and SMC2 parameter RAM, so we start allocating
  82  * BDs above that.  All of this must change when we start
  83  * downloading RAM microcode.
  84  */
  85 #define CPM_DATAONLY_BASE       ((uint)128)
  86 #define CPM_DATAONLY_SIZE       ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
  87 #define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  88 #define CPM_FCC_SPECIAL_BASE    ((uint)0x0000b000)
  89
  90 /* The number of pages of host memory we allocate for CPM.  This is
  91  * done early in kernel initialization to get physically contiguous
  92  * pages.
  93  */
  94 #define NUM_CPM_HOST_PAGES      2
  95
  96
  97 /* Export the base address of the communication processor registers
  98  * and dual port ram.
  99  */
 100 extern  cpm8260_t       *cpmp;          /* Pointer to comm processor */
 101 uint            m8260_cpm_dpalloc(uint size, uint align);
 102 uint            m8260_cpm_hostalloc(uint size, uint align);
 103 void            m8260_cpm_setbrg(uint brg, uint rate);
 104 void            m8260_cpm_fastbrg(uint brg, uint rate, int div16);
 105 void            m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
 106
 107 /* Buffer descriptors used by many of the CPM protocols.
 108 */
 109 typedef struct cpm_buf_desc {
 110         ushort  cbd_sc;         /* Status and Control */
 111         ushort  cbd_datlen;     /* Data length in buffer */
 112         uint    cbd_bufaddr;    /* Buffer address in host memory */
 113 } cbd_t;
 114
 115 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Recieve is empty */
 116 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
 117 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
 118 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
 119 #define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
 120 #define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
 121 #define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
 122 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
 123 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
 124 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
 125 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
 126 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
 127 #define BD_SC_CD        ((ushort)0x0001)        /* ?? */
 128
 129 /* Function code bits, usually generic to devices.
 130 */
 131 #define CPMFCR_GBL      ((u_char)0x20)  /* Set memory snooping */
 132 #define CPMFCR_EB       ((u_char)0x10)  /* Set big endian byte order */
 133 #define CPMFCR_TC2      ((u_char)0x04)  /* Transfer code 2 value */
 134 #define CPMFCR_DTB      ((u_char)0x02)  /* Use local bus for data when set */
 135 #define CPMFCR_BDB      ((u_char)0x01)  /* Use local bus for BD when set */
 136
 137 /* Parameter RAM offsets from the base.
 138 */
 139 #ifndef CFG_CPM_POST_WORD_ADDR
 140 #define CPM_POST_WORD_ADDR      0x80FC  /* steal a long at the end of SCC1 */
 141 #else
 142 #define CPM_POST_WORD_ADDR      CFG_CPM_POST_WORD_ADDR
 143 #endif
 144
 145 #ifndef CFG_CPM_BOOTCOUNT_ADDR
 146 #define CPM_BOOTCOUNT_ADDR      (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
 147 #else
 148 #define CPM_BOOTCOUNT_ADDR      CFG_CPM_BOOTCOUNT_ADDR
 149 #endif
 150
 151 #define PROFF_SCC1              ((uint)0x8000)
 152 #define PROFF_SCC2              ((uint)0x8100)
 153 #define PROFF_SCC3              ((uint)0x8200)
 154 #define PROFF_SCC4              ((uint)0x8300)
 155 #define PROFF_FCC1              ((uint)0x8400)
 156 #define PROFF_FCC2              ((uint)0x8500)
 157 #define PROFF_FCC3              ((uint)0x8600)
 158 #define PROFF_MCC1              ((uint)0x8700)
 159 #define PROFF_SMC1_BASE         ((uint)0x87fc)
 160 #define PROFF_IDMA1_BASE        ((uint)0x87fe)
 161 #define PROFF_MCC2              ((uint)0x8800)
 162 #define PROFF_SMC2_BASE         ((uint)0x88fc)
 163 #define PROFF_IDMA2_BASE        ((uint)0x88fe)
 164 #define PROFF_SPI_BASE          ((uint)0x89fc)
 165 #define PROFF_IDMA3_BASE        ((uint)0x89fe)
 166 #define PROFF_TIMERS            ((uint)0x8ae0)
 167 #define PROFF_REVNUM            ((uint)0x8af0)
 168 #define PROFF_RAND              ((uint)0x8af8)
 169 #define PROFF_I2C_BASE          ((uint)0x8afc)
 170 #define PROFF_IDMA4_BASE        ((uint)0x8afe)
 171
 172 /* The SMCs are relocated to any of the first eight DPRAM pages.
 173  * We will fix these at the first locations of DPRAM, until we
 174  * get some microcode patches :-).
 175  * The parameter ram space for the SMCs is fifty-some bytes, and
 176  * they are required to start on a 64 byte boundary.
 177  */
 178 #define PROFF_SMC1      (0)
 179 #define PROFF_SMC2      (64)
 180 #define PROFF_SPI       ((16*1024) - 128)
 181
 182 /* Define enough so I can at least use the serial port as a UART.
 183  */
 184 typedef struct smc_uart {
 185         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 186         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 187         u_char  smc_rfcr;       /* Rx function code */
 188         u_char  smc_tfcr;       /* Tx function code */
 189         ushort  smc_mrblr;      /* Max receive buffer length */
 190         uint    smc_rstate;     /* Internal */
 191         uint    smc_idp;        /* Internal */
 192         ushort  smc_rbptr;      /* Internal */
 193         ushort  smc_ibc;        /* Internal */
 194         uint    smc_rxtmp;      /* Internal */
 195         uint    smc_tstate;     /* Internal */
 196         uint    smc_tdp;        /* Internal */
 197         ushort  smc_tbptr;      /* Internal */
 198         ushort  smc_tbc;        /* Internal */
 199         uint    smc_txtmp;      /* Internal */
 200         ushort  smc_maxidl;     /* Maximum idle characters */
 201         ushort  smc_tmpidl;     /* Temporary idle counter */
 202         ushort  smc_brklen;     /* Last received break length */
 203         ushort  smc_brkec;      /* rcv'd break condition counter */
 204         ushort  smc_brkcr;      /* xmt break count register */
 205         ushort  smc_rmask;      /* Temporary bit mask */
 206         uint    smc_stmp;       /* SDMA Temp */
 207 } smc_uart_t;
 208
 209 /* SMC uart mode register (Internal memory map).
 210 */
 211 #define SMCMR_REN       ((ushort)0x0001)
 212 #define SMCMR_TEN       ((ushort)0x0002)
 213 #define SMCMR_DM        ((ushort)0x000c)
 214 #define SMCMR_SM_GCI    ((ushort)0x0000)
 215 #define SMCMR_SM_UART   ((ushort)0x0020)
 216 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 217 #define SMCMR_SM_MASK   ((ushort)0x0030)
 218 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 219 #define SMCMR_REVD      SMCMR_PM_EVEN
 220 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 221 #define SMCMR_BS        SMCMR_PEN
 222 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 223 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 224 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 225
 226 /* SMC Event and Mask register.
 227 */
 228 #define SMCM_TXE        ((unsigned char)0x10)
 229 #define SMCM_BSY        ((unsigned char)0x04)
 230 #define SMCM_TX         ((unsigned char)0x02)
 231 #define SMCM_RX         ((unsigned char)0x01)
 232
 233 /* Baud rate generators.
 234 */
 235 #define CPM_BRG_RST             ((uint)0x00020000)
 236 #define CPM_BRG_EN              ((uint)0x00010000)
 237 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 238 #define CPM_BRG_EXTC_CLK3_9     ((uint)0x00004000)
 239 #define CPM_BRG_EXTC_CLK5_15    ((uint)0x00008000)
 240 #define CPM_BRG_ATB             ((uint)0x00002000)
 241 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 242 #define CPM_BRG_DIV16           ((uint)0x00000001)
 243
 244 /* SCCs.
 245 */
 246 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 247 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 248 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 249 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 250 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 251 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 252 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 253 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 254 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 255 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 256 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 257 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 258 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 259 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 260 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 261 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 262 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 263 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 264 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 265 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 266
 267 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 268 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 269 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 270 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 271 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 272 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 273 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 274 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 275 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 276 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 277 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 278 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 279 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 280 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 281 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 282 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 283 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 284 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 285 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 286 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 287 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 288 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 289 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 290 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 291 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 292 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 293 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 294 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 295 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 296 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 297 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 298 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 299 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 300 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 301 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 302 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 303 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 304 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 305 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 306 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 307 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 308 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 309 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 310 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 311 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 312 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 313 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 314 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 315 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 316 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 317 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 318 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 319 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 320 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 321 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 322 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 323 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 324 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 325
 326 #define SCC_TODR_TOD            ((ushort)0x8000)
 327
 328 /* SCC Event and Mask register.
 329 */
 330 #define SCCM_TXE        ((unsigned char)0x10)
 331 #define SCCM_BSY        ((unsigned char)0x04)
 332 #define SCCM_TX         ((unsigned char)0x02)
 333 #define SCCM_RX         ((unsigned char)0x01)
 334
 335 typedef struct scc_param {
 336         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 337         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 338         u_char  scc_rfcr;       /* Rx function code */
 339         u_char  scc_tfcr;       /* Tx function code */
 340         ushort  scc_mrblr;      /* Max receive buffer length */
 341         uint    scc_rstate;     /* Internal */
 342         uint    scc_idp;        /* Internal */
 343         ushort  scc_rbptr;      /* Internal */
 344         ushort  scc_ibc;        /* Internal */
 345         uint    scc_rxtmp;      /* Internal */
 346         uint    scc_tstate;     /* Internal */
 347         uint    scc_tdp;        /* Internal */
 348         ushort  scc_tbptr;      /* Internal */
 349         ushort  scc_tbc;        /* Internal */
 350         uint    scc_txtmp;      /* Internal */
 351         uint    scc_rcrc;       /* Internal */
 352         uint    scc_tcrc;       /* Internal */
 353 } sccp_t;
 354
 355 /* CPM Ethernet through SCC1.
 356  */
 357 typedef struct scc_enet {
 358         sccp_t  sen_genscc;
 359         uint    sen_cpres;      /* Preset CRC */
 360         uint    sen_cmask;      /* Constant mask for CRC */
 361         uint    sen_crcec;      /* CRC Error counter */
 362         uint    sen_alec;       /* alignment error counter */
 363         uint    sen_disfc;      /* discard frame counter */
 364         ushort  sen_pads;       /* Tx short frame pad character */
 365         ushort  sen_retlim;     /* Retry limit threshold */
 366         ushort  sen_retcnt;     /* Retry limit counter */
 367         ushort  sen_maxflr;     /* maximum frame length register */
 368         ushort  sen_minflr;     /* minimum frame length register */
 369         ushort  sen_maxd1;      /* maximum DMA1 length */
 370         ushort  sen_maxd2;      /* maximum DMA2 length */
 371         ushort  sen_maxd;       /* Rx max DMA */
 372         ushort  sen_dmacnt;     /* Rx DMA counter */
 373         ushort  sen_maxb;       /* Max BD byte count */
 374         ushort  sen_gaddr1;     /* Group address filter */
 375         ushort  sen_gaddr2;
 376         ushort  sen_gaddr3;
 377         ushort  sen_gaddr4;
 378         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 379         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 380         uint    sen_tbuf0rba;   /* Internal */
 381         uint    sen_tbuf0crc;   /* Internal */
 382         ushort  sen_tbuf0bcnt;  /* Internal */
 383         ushort  sen_paddrh;     /* physical address (MSB) */
 384         ushort  sen_paddrm;
 385         ushort  sen_paddrl;     /* physical address (LSB) */
 386         ushort  sen_pper;       /* persistence */
 387         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 388         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 389         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 390         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 391         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 392         uint    sen_tbuf1rba;   /* Internal */
 393         uint    sen_tbuf1crc;   /* Internal */
 394         ushort  sen_tbuf1bcnt;  /* Internal */
 395         ushort  sen_txlen;      /* Tx Frame length counter */
 396         ushort  sen_iaddr1;     /* Individual address filter */
 397         ushort  sen_iaddr2;
 398         ushort  sen_iaddr3;
 399         ushort  sen_iaddr4;
 400         ushort  sen_boffcnt;    /* Backoff counter */
 401
 402         /* NOTE: Some versions of the manual have the following items
 403          * incorrectly documented.  Below is the proper order.
 404          */
 405         ushort  sen_taddrh;     /* temp address (MSB) */
 406         ushort  sen_taddrm;
 407         ushort  sen_taddrl;     /* temp address (LSB) */
 408 } scc_enet_t;
 409
 410
 411 /* SCC Event register as used by Ethernet.
 412 */
 413 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 414 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 415 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 416 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 417 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 418 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 419
 420 /* SCC Mode Register (PSMR) as used by Ethernet.
 421 */
 422 #define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 423 #define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
 424 #define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
 425 #define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
 426 #define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 427 #define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 428 #define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 429 #define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 430 #define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 431 #define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 432 #define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
 433 #define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
 434 #define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 435
 436 /* Buffer descriptor control/status used by Ethernet receive.
 437  * Common to SCC and FCC.
 438  */
 439 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
 440 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
 441 #define BD_ENET_RX_INTR         ((ushort)0x1000)
 442 #define BD_ENET_RX_LAST         ((ushort)0x0800)
 443 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
 444 #define BD_ENET_RX_MISS         ((ushort)0x0100)
 445 #define BD_ENET_RX_BC           ((ushort)0x0080)        /* FCC Only */
 446 #define BD_ENET_RX_MC           ((ushort)0x0040)        /* FCC Only */
 447 #define BD_ENET_RX_LG           ((ushort)0x0020)
 448 #define BD_ENET_RX_NO           ((ushort)0x0010)
 449 #define BD_ENET_RX_SH           ((ushort)0x0008)
 450 #define BD_ENET_RX_CR           ((ushort)0x0004)
 451 #define BD_ENET_RX_OV           ((ushort)0x0002)
 452 #define BD_ENET_RX_CL           ((ushort)0x0001)
 453 #define BD_ENET_RX_STATS        ((ushort)0x01ff)        /* All status bits */
 454
 455 /* Buffer descriptor control/status used by Ethernet transmit.
 456  * Common to SCC and FCC.
 457  */
 458 #define BD_ENET_TX_READY        ((ushort)0x8000)
 459 #define BD_ENET_TX_PAD          ((ushort)0x4000)
 460 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
 461 #define BD_ENET_TX_INTR         ((ushort)0x1000)
 462 #define BD_ENET_TX_LAST         ((ushort)0x0800)
 463 #define BD_ENET_TX_TC           ((ushort)0x0400)
 464 #define BD_ENET_TX_DEF          ((ushort)0x0200)
 465 #define BD_ENET_TX_HB           ((ushort)0x0100)
 466 #define BD_ENET_TX_LC           ((ushort)0x0080)
 467 #define BD_ENET_TX_RL           ((ushort)0x0040)
 468 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
 469 #define BD_ENET_TX_UN           ((ushort)0x0002)
 470 #define BD_ENET_TX_CSL          ((ushort)0x0001)
 471 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
 472
 473 /* SCC as UART
 474 */
 475 typedef struct scc_uart {
 476         sccp_t  scc_genscc;
 477         uint    scc_res1;       /* Reserved */
 478         uint    scc_res2;       /* Reserved */
 479         ushort  scc_maxidl;     /* Maximum idle chars */
 480         ushort  scc_idlc;       /* temp idle counter */
 481         ushort  scc_brkcr;      /* Break count register */
 482         ushort  scc_parec;      /* receive parity error counter */
 483         ushort  scc_frmec;      /* receive framing error counter */
 484         ushort  scc_nosec;      /* receive noise counter */
 485         ushort  scc_brkec;      /* receive break condition counter */
 486         ushort  scc_brkln;      /* last received break length */
 487         ushort  scc_uaddr1;     /* UART address character 1 */
 488         ushort  scc_uaddr2;     /* UART address character 2 */
 489         ushort  scc_rtemp;      /* Temp storage */
 490         ushort  scc_toseq;      /* Transmit out of sequence char */
 491         ushort  scc_char1;      /* control character 1 */
 492         ushort  scc_char2;      /* control character 2 */
 493         ushort  scc_char3;      /* control character 3 */
 494         ushort  scc_char4;      /* control character 4 */
 495         ushort  scc_char5;      /* control character 5 */
 496         ushort  scc_char6;      /* control character 6 */
 497         ushort  scc_char7;      /* control character 7 */
 498         ushort  scc_char8;      /* control character 8 */
 499         ushort  scc_rccm;       /* receive control character mask */
 500         ushort  scc_rccr;       /* receive control character register */
 501         ushort  scc_rlbc;       /* receive last break character */
 502 } scc_uart_t;
 503
 504 /* SCC Event and Mask registers when it is used as a UART.
 505 */
 506 #define UART_SCCM_GLR           ((ushort)0x1000)
 507 #define UART_SCCM_GLT           ((ushort)0x0800)
 508 #define UART_SCCM_AB            ((ushort)0x0200)
 509 #define UART_SCCM_IDL           ((ushort)0x0100)
 510 #define UART_SCCM_GRA           ((ushort)0x0080)
 511 #define UART_SCCM_BRKE          ((ushort)0x0040)
 512 #define UART_SCCM_BRKS          ((ushort)0x0020)
 513 #define UART_SCCM_CCR           ((ushort)0x0008)
 514 #define UART_SCCM_BSY           ((ushort)0x0004)
 515 #define UART_SCCM_TX            ((ushort)0x0002)
 516 #define UART_SCCM_RX            ((ushort)0x0001)
 517
 518 /* The SCC PSMR when used as a UART.
 519 */
 520 #define SCU_PSMR_FLC            ((ushort)0x8000)
 521 #define SCU_PSMR_SL             ((ushort)0x4000)
 522 #define SCU_PSMR_CL             ((ushort)0x3000)
 523 #define SCU_PSMR_UM             ((ushort)0x0c00)
 524 #define SCU_PSMR_FRZ            ((ushort)0x0200)
 525 #define SCU_PSMR_RZS            ((ushort)0x0100)
 526 #define SCU_PSMR_SYN            ((ushort)0x0080)
 527 #define SCU_PSMR_DRT            ((ushort)0x0040)
 528 #define SCU_PSMR_PEN            ((ushort)0x0010)
 529 #define SCU_PSMR_RPM            ((ushort)0x000c)
 530 #define SCU_PSMR_REVP           ((ushort)0x0008)
 531 #define SCU_PSMR_TPM            ((ushort)0x0003)
 532 #define SCU_PSMR_TEVP           ((ushort)0x0003)
 533
 534 /* CPM Transparent mode SCC.
 535  */
 536 typedef struct scc_trans {
 537         sccp_t  st_genscc;
 538         uint    st_cpres;       /* Preset CRC */
 539         uint    st_cmask;       /* Constant mask for CRC */
 540 } scc_trans_t;
 541
 542 #define BD_SCC_TX_LAST          ((ushort)0x0800)
 543
 544 /* How about some FCCs.....
 545 */
 546 #define FCC_GFMR_DIAG_NORM      ((uint)0x00000000)
 547 #define FCC_GFMR_DIAG_LE        ((uint)0x40000000)
 548 #define FCC_GFMR_DIAG_AE        ((uint)0x80000000)
 549 #define FCC_GFMR_DIAG_ALE       ((uint)0xc0000000)
 550 #define FCC_GFMR_TCI            ((uint)0x20000000)
 551 #define FCC_GFMR_TRX            ((uint)0x10000000)
 552 #define FCC_GFMR_TTX            ((uint)0x08000000)
 553 #define FCC_GFMR_TTX            ((uint)0x08000000)
 554 #define FCC_GFMR_CDP            ((uint)0x04000000)
 555 #define FCC_GFMR_CTSP           ((uint)0x02000000)
 556 #define FCC_GFMR_CDS            ((uint)0x01000000)
 557 #define FCC_GFMR_CTSS           ((uint)0x00800000)
 558 #define FCC_GFMR_SYNL_NONE      ((uint)0x00000000)
 559 #define FCC_GFMR_SYNL_AUTO      ((uint)0x00004000)
 560 #define FCC_GFMR_SYNL_8         ((uint)0x00008000)
 561 #define FCC_GFMR_SYNL_16        ((uint)0x0000c000)
 562 #define FCC_GFMR_RTSM           ((uint)0x00002000)
 563 #define FCC_GFMR_RENC_NRZ       ((uint)0x00000000)
 564 #define FCC_GFMR_RENC_NRZI      ((uint)0x00000800)
 565 #define FCC_GFMR_REVD           ((uint)0x00000400)
 566 #define FCC_GFMR_TENC_NRZ       ((uint)0x00000000)
 567 #define FCC_GFMR_TENC_NRZI      ((uint)0x00000100)
 568 #define FCC_GFMR_TCRC_16        ((uint)0x00000000)
 569 #define FCC_GFMR_TCRC_32        ((uint)0x00000080)
 570 #define FCC_GFMR_ENR            ((uint)0x00000020)
 571 #define FCC_GFMR_ENT            ((uint)0x00000010)
 572 #define FCC_GFMR_MODE_ENET      ((uint)0x0000000c)
 573 #define FCC_GFMR_MODE_ATM       ((uint)0x0000000a)
 574 #define FCC_GFMR_MODE_HDLC      ((uint)0x00000000)
 575
 576 /* Generic FCC parameter ram.
 577 */
 578 typedef struct fcc_param {
 579         ushort  fcc_riptr;      /* Rx Internal temp pointer */
 580         ushort  fcc_tiptr;      /* Tx Internal temp pointer */
 581         ushort  fcc_res1;
 582         ushort  fcc_mrblr;      /* Max receive buffer length, mod 32 bytes */
 583         uint    fcc_rstate;     /* Upper byte is Func code, must be set */
 584         uint    fcc_rbase;      /* Receive BD base */
 585         ushort  fcc_rbdstat;    /* RxBD status */
 586         ushort  fcc_rbdlen;     /* RxBD down counter */
 587         uint    fcc_rdptr;      /* RxBD internal data pointer */
 588         uint    fcc_tstate;     /* Upper byte is Func code, must be set */
 589         uint    fcc_tbase;      /* Transmit BD base */
 590         ushort  fcc_tbdstat;    /* TxBD status */
 591         ushort  fcc_tbdlen;     /* TxBD down counter */
 592         uint    fcc_tdptr;      /* TxBD internal data pointer */
 593         uint    fcc_rbptr;      /* Rx BD Internal buf pointer */
 594         uint    fcc_tbptr;      /* Tx BD Internal buf pointer */
 595         uint    fcc_rcrc;       /* Rx temp CRC */
 596         uint    fcc_res2;
 597         uint    fcc_tcrc;       /* Tx temp CRC */
 598 } fccp_t;
 599
 600
 601 /* Ethernet controller through FCC.
 602 */
 603 typedef struct fcc_enet {
 604         fccp_t  fen_genfcc;
 605         uint    fen_statbuf;    /* Internal status buffer */
 606         uint    fen_camptr;     /* CAM address */
 607         uint    fen_cmask;      /* Constant mask for CRC */
 608         uint    fen_cpres;      /* Preset CRC */
 609         uint    fen_crcec;      /* CRC Error counter */
 610         uint    fen_alec;       /* alignment error counter */
 611         uint    fen_disfc;      /* discard frame counter */
 612         ushort  fen_retlim;     /* Retry limit */
 613         ushort  fen_retcnt;     /* Retry counter */
 614         ushort  fen_pper;       /* Persistence */
 615         ushort  fen_boffcnt;    /* backoff counter */
 616         uint    fen_gaddrh;     /* Group address filter, high 32-bits */
 617         uint    fen_gaddrl;     /* Group address filter, low 32-bits */
 618         ushort  fen_tfcstat;    /* out of sequence TxBD */
 619         ushort  fen_tfclen;
 620         uint    fen_tfcptr;
 621         ushort  fen_mflr;       /* Maximum frame length (1518) */
 622         ushort  fen_paddrh;     /* MAC address */
 623         ushort  fen_paddrm;
 624         ushort  fen_paddrl;
 625         ushort  fen_ibdcount;   /* Internal BD counter */
 626         ushort  fen_idbstart;   /* Internal BD start pointer */
 627         ushort  fen_ibdend;     /* Internal BD end pointer */
 628         ushort  fen_txlen;      /* Internal Tx frame length counter */
 629         uint    fen_ibdbase[8]; /* Internal use */
 630         uint    fen_iaddrh;     /* Individual address filter */
 631         uint    fen_iaddrl;
 632         ushort  fen_minflr;     /* Minimum frame length (64) */
 633         ushort  fen_taddrh;     /* Filter transfer MAC address */
 634         ushort  fen_taddrm;
 635         ushort  fen_taddrl;
 636         ushort  fen_padptr;     /* Pointer to pad byte buffer */
 637         ushort  fen_cftype;     /* control frame type */
 638         ushort  fen_cfrange;    /* control frame range */
 639         ushort  fen_maxb;       /* maximum BD count */
 640         ushort  fen_maxd1;      /* Max DMA1 length (1520) */
 641         ushort  fen_maxd2;      /* Max DMA2 length (1520) */
 642         ushort  fen_maxd;       /* internal max DMA count */
 643         ushort  fen_dmacnt;     /* internal DMA counter */
 644         uint    fen_octc;       /* Total octect counter */
 645         uint    fen_colc;       /* Total collision counter */
 646         uint    fen_broc;       /* Total broadcast packet counter */
 647         uint    fen_mulc;       /* Total multicast packet count */
 648         uint    fen_uspc;       /* Total packets < 64 bytes */
 649         uint    fen_frgc;       /* Total packets < 64 bytes with errors */
 650         uint    fen_ospc;       /* Total packets > 1518 */
 651         uint    fen_jbrc;       /* Total packets > 1518 with errors */
 652         uint    fen_p64c;       /* Total packets == 64 bytes */
 653         uint    fen_p65c;       /* Total packets 64 < bytes <= 127 */
 654         uint    fen_p128c;      /* Total packets 127 < bytes <= 255 */
 655         uint    fen_p256c;      /* Total packets 256 < bytes <= 511 */
 656         uint    fen_p512c;      /* Total packets 512 < bytes <= 1023 */
 657         uint    fen_p1024c;     /* Total packets 1024 < bytes <= 1518 */
 658         uint    fen_cambuf;     /* Internal CAM buffer poiner */
 659         ushort  fen_rfthr;      /* Received frames threshold */
 660         ushort  fen_rfcnt;      /* Received frames count */
 661 } fcc_enet_t;
 662
 663 /* FCC Event/Mask register as used by Ethernet.
 664 */
 665 #define FCC_ENET_GRA    ((ushort)0x0080)        /* Graceful stop complete */
 666 #define FCC_ENET_RXC    ((ushort)0x0040)        /* Control Frame Received */
 667 #define FCC_ENET_TXC    ((ushort)0x0020)        /* Out of seq. Tx sent */
 668 #define FCC_ENET_TXE    ((ushort)0x0010)        /* Transmit Error */
 669 #define FCC_ENET_RXF    ((ushort)0x0008)        /* Full frame received */
 670 #define FCC_ENET_BSY    ((ushort)0x0004)        /* Busy.  Rx Frame dropped */
 671 #define FCC_ENET_TXB    ((ushort)0x0002)        /* A buffer was transmitted */
 672 #define FCC_ENET_RXB    ((ushort)0x0001)        /* A buffer was received */
 673
 674 /* FCC Mode Register (FPSMR) as used by Ethernet.
 675 */
 676 #define FCC_PSMR_HBC    ((uint)0x80000000)      /* Enable heartbeat */
 677 #define FCC_PSMR_FC     ((uint)0x40000000)      /* Force Collision */
 678 #define FCC_PSMR_SBT    ((uint)0x20000000)      /* Stop backoff timer */
 679 #define FCC_PSMR_LPB    ((uint)0x10000000)      /* Local protect. 1 = FDX */
 680 #define FCC_PSMR_LCW    ((uint)0x08000000)      /* Late collision select */
 681 #define FCC_PSMR_FDE    ((uint)0x04000000)      /* Full Duplex Enable */
 682 #define FCC_PSMR_MON    ((uint)0x02000000)      /* RMON Enable */
 683 #define FCC_PSMR_PRO    ((uint)0x00400000)      /* Promiscuous Enable */
 684 #define FCC_PSMR_FCE    ((uint)0x00200000)      /* Flow Control Enable */
 685 #define FCC_PSMR_RSH    ((uint)0x00100000)      /* Receive Short Frames */
 686 #define FCC_PSMR_RMII   ((uint)0x00020000)      /* Use RMII interface */
 687 #define FCC_PSMR_CAM    ((uint)0x00000400)      /* CAM enable */
 688 #define FCC_PSMR_BRO    ((uint)0x00000200)      /* Broadcast pkt discard */
 689 #define FCC_PSMR_ENCRC  ((uint)0x00000080)      /* Use 32-bit CRC */
 690
 691 /* IIC parameter RAM.
 692 */
 693 typedef struct iic {
 694         ushort  iic_rbase;      /* Rx Buffer descriptor base address */
 695         ushort  iic_tbase;      /* Tx Buffer descriptor base address */
 696         u_char  iic_rfcr;       /* Rx function code */
 697         u_char  iic_tfcr;       /* Tx function code */
 698         ushort  iic_mrblr;      /* Max receive buffer length */
 699         uint    iic_rstate;     /* Internal */
 700         uint    iic_rdp;        /* Internal */
 701         ushort  iic_rbptr;      /* Internal */
 702         ushort  iic_rbc;        /* Internal */
 703         uint    iic_rxtmp;      /* Internal */
 704         uint    iic_tstate;     /* Internal */
 705         uint    iic_tdp;        /* Internal */
 706         ushort  iic_tbptr;      /* Internal */
 707         ushort  iic_tbc;        /* Internal */
 708         uint    iic_txtmp;      /* Internal */
 709 } iic_t;
 710
 711 /* SPI parameter RAM.
 712 */
 713 typedef struct spi {
 714         ushort  spi_rbase;      /* Rx Buffer descriptor base address */
 715         ushort  spi_tbase;      /* Tx Buffer descriptor base address */
 716         u_char  spi_rfcr;       /* Rx function code */
 717         u_char  spi_tfcr;       /* Tx function code */
 718         ushort  spi_mrblr;      /* Max receive buffer length */
 719         uint    spi_rstate;     /* Internal */
 720         uint    spi_rdp;        /* Internal */
 721         ushort  spi_rbptr;      /* Internal */
 722         ushort  spi_rbc;        /* Internal */
 723         uint    spi_rxtmp;      /* Internal */
 724         uint    spi_tstate;     /* Internal */
 725         uint    spi_tdp;        /* Internal */
 726         ushort  spi_tbptr;      /* Internal */
 727         ushort  spi_tbc;        /* Internal */
 728         uint    spi_txtmp;      /* Internal */
 729         uint    spi_res;        /* Tx temp. */
 730         uint    spi_res1[4];    /* SDMA temp. */
 731 } spi_t;
 732
 733 /* SPI Mode register.
 734 */
 735 #define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
 736 #define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
 737 #define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
 738 #define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
 739 #define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
 740 #define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
 741 #define SPMODE_EN       ((ushort)0x0100)        /* Enable */
 742 #define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
 743 #define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
 744
 745 #define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
 746 #define SPMODE_PM(x)    ((x) &0xF)
 747
 748 /* SPI Event/Mask register.
 749 */
 750 #define SPI_EMASK               0x37    /* Event Mask                           */
 751 #define SPI_MME                 0x20    /* Multi-Master Error                   */
 752 #define SPI_TXE                 0x10    /* Transmit Error                       */
 753 #define SPI_BSY                 0x04    /* Busy                                 */
 754 #define SPI_TXB                 0x02    /* Tx Buffer Empty                      */
 755 #define SPI_RXB                 0x01    /* RX Buffer full/closed                */
 756
 757 #define SPI_STR                 0x80    /* SPCOM: Start transmit                */
 758
 759 #define SPI_EB          ((u_char)0x10)          /* big endian byte order */
 760
 761 #define BD_IIC_START            ((ushort)0x0400)
 762
 763 #endif /* __CPM_82XX__ */