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1 /*
2 * (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
3 *
4 * MPC83xx Internal Memory Map
5 *
6 * History :
7 * 20060601: Daveliu (daveliu@freescale.com)
8 * TanyaJiang (tanya.jiang@freescale.com)
9 * Unified variable names for mpc83xx
10 * 2005 : Mandy Lavi (mandy.lavi@freescale.com)
11 * support for mpc8360e
12 * 2004 : Eran Liberty (liberty@freescale.com)
13 * Initialized for mpc8349
14 * based on:
15 * MPC8260 Internal Memory Map
16 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
17 * MPC85xx Internal Memory Map
18 * Copyright(c) 2002,2003 Motorola Inc.
19 * Xianghua Xiao (x.xiao@motorola.com)
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * MA 02111-1307 USA
35 *
36 */
37 #ifndef __IMMAP_83xx__
38 #define __IMMAP_83xx__
39
40 #include <config.h>
41 #include <asm/types.h>
42 #include <asm/fsl_i2c.h>
43
44 /*
45 * Local Access Window.
46 */
47 typedef struct law83xx {
48 u32 bar; /* LBIU local access window base address register */
49 /* Identifies the 20 most-significant address bits of the base of local
50 * access window n. The specified base address should be aligned to the
51 * window size, as defined by LBLAWARn[SIZE].
52 */
53 #define LAWBAR_BAR 0xFFFFF000
54 #define LAWBAR_RES ~(LAWBAR_BAR)
55 u32 ar; /* LBIU local access window attribute register */
56 } law83xx_t;
57
58 /*
59 * System configuration registers.
60 */
61 typedef struct sysconf83xx {
62 u32 immrbar; /* Internal memory map base address register */
63 u8 res0[0x04];
64 u32 altcbar; /* Alternate configuration base address register */
65 /* Identifies the12 most significant address bits of an alternate base
66 * address used for boot sequencer configuration accesses.
67 */
68 #define ALTCBAR_BASE_ADDR 0xFFF00000
69 #define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
70 u8 res1[0x14];
71 law83xx_t lblaw[4]; /* LBIU local access window */
72 u8 res2[0x20];
73 law83xx_t pcilaw[2]; /* PCI local access window */
74 u8 res3[0x30];
75 law83xx_t ddrlaw[2]; /* DDR local access window */
76 u8 res4[0x50];
77 u32 sgprl; /* System General Purpose Register Low */
78 u32 sgprh; /* System General Purpose Register High */
79 u32 spridr; /* System Part and Revision ID Register */
80 #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */
81 #define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */
82 u8 res5[0x04];
83 u32 spcr; /* System Priority Configuration Register */
84 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */
85 #define SPCR_PCIHPE_SHIFT (31-3)
86 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */
87 #define SPCR_PCIPR_SHIFT (31-7)
88 #define SPCR_OPT 0x00800000 /* Optimize */
89 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */
90 #define SPCR_TBEN_SHIFT (31-9)
91 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */
92 #define SPCR_COREPR_SHIFT (31-11)
93 #if defined (CONFIG_MPC8349)
94 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */
95 #define SPCR_TSEC1DP_SHIFT (31-19)
96 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
97 #define SPCR_TSEC1BDP_SHIFT (31-21)
98 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */
99 #define SPCR_TSEC1EP_SHIFT (31-23)
100 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */
101 #define SPCR_TSEC2DP_SHIFT (31-27)
102 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
103 #define SPCR_TSEC2BDP_SHIFT (31-29)
104 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */
105 #define SPCR_TSEC2EP_SHIFT (31-31)
106 #define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
107 | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
108 | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
109 #elif defined (CONFIG_MPC8360)
110 #define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR)
111 #endif
112 u32 sicrl; /* System General Purpose Register Low */
113 #if defined (CONFIG_MPC8349)
114 #define SICRL_LDP_A 0x80000000
115 #define SICRL_USB1 0x40000000
116 #define SICRL_USB0 0x20000000
117 #define SICRL_UART 0x0C000000
118 #define SICRL_GPIO1_A 0x02000000
119 #define SICRL_GPIO1_B 0x01000000
120 #define SICRL_GPIO1_C 0x00800000
121 #define SICRL_GPIO1_D 0x00400000
122 #define SICRL_GPIO1_E 0x00200000
123 #define SICRL_GPIO1_F 0x00180000
124 #define SICRL_GPIO1_G 0x00040000
125 #define SICRL_GPIO1_H 0x00020000
126 #define SICRL_GPIO1_I 0x00010000
127 #define SICRL_GPIO1_J 0x00008000
128 #define SICRL_GPIO1_K 0x00004000
129 #define SICRL_GPIO1_L 0x00003000
130 #define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
131 | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
132 | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
133 | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
134 | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
135 #elif defined (CONFIG_MPC8360)
136 #define SICRL_LDP_A 0xC0000000
137 #define SICRL_LCLK_1 0x10000000
138 #define SICRL_LCLK_2 0x08000000
139 #define SICRL_SRCID_A 0x03000000
140 #define SICRL_IRQ_CKSTP_A 0x00C00000
141 #define SICRL_RES ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \
142 SICRL_SRCID_A | SICRL_IRQ_CKSTP_A)
143 #endif
144 u32 sicrh; /* System General Purpose Register High */
145 #define SICRH_DDR 0x80000000
146 #if defined (CONFIG_MPC8349)
147 #define SICRH_TSEC1_A 0x10000000
148 #define SICRH_TSEC1_B 0x08000000
149 #define SICRH_TSEC1_C 0x04000000
150 #define SICRH_TSEC1_D 0x02000000
151 #define SICRH_TSEC1_E 0x01000000
152 #define SICRH_TSEC1_F 0x00800000
153 #define SICRH_TSEC2_A 0x00400000
154 #define SICRH_TSEC2_B 0x00200000
155 #define SICRH_TSEC2_C 0x00100000
156 #define SICRH_TSEC2_D 0x00080000
157 #define SICRH_TSEC2_E 0x00040000
158 #define SICRH_TSEC2_F 0x00020000
159 #define SICRH_TSEC2_G 0x00010000
160 #define SICRH_TSEC2_H 0x00008000
161 #define SICRH_GPIO2_A 0x00004000
162 #define SICRH_GPIO2_B 0x00002000
163 #define SICRH_GPIO2_C 0x00001000
164 #define SICRH_GPIO2_D 0x00000800
165 #define SICRH_GPIO2_E 0x00000400
166 #define SICRH_GPIO2_F 0x00000200
167 #define SICRH_GPIO2_G 0x00000180
168 #define SICRH_GPIO2_H 0x00000060
169 #define SICRH_TSOBI1 0x00000002
170 #define SICRH_TSOBI2 0x00000001
171 #define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
172 | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
173 | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
174 | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
175 | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
176 | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
177 | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
178 | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
179 | SICRH_TSOBI2)
180 #elif defined (CONFIG_MPC8360)
181 #define SICRH_SECONDARY_DDR 0x40000000
182 #define SICRH_SDDROE 0x02000000 /* SDDRIOE bit from reset configuration word high. */
183 #define SICRH_UC1EOBI 0x00000004 /* UCC1 Ethernet Output Buffer Impedance. */
184 #define SICRH_UC2E1OBI 0x00000002 /* UCC2 Ethernet pin option 1 Output Buffer Impedance. */
185 #define SICRH_UC2E2OBI 0x00000001 /* UCC2 Ethernet pin option 2 Output Buffer Impedance. */
186 #define SICRH_RES ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \
187 SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI)
188 #endif
189 u8 res6[0xE4];
190 } sysconf83xx_t;
191
192 /*
193 * Watch Dog Timer (WDT) Registers
194 */
195 typedef struct wdt83xx {
196 u8 res0[4];
197 u32 swcrr; /* System watchdog control register */
198 u32 swcnr; /* System watchdog count register */
199 #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
200 #define SWCNR_RES ~(SWCNR_SWCN)
201 u8 res1[2];
202 u16 swsrr; /* System watchdog service register */
203 #define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field. */
204 u8 res2[0xF0];
205 } wdt83xx_t;
206
207 /*
208 * RTC/PIT Module Registers
209 */
210 typedef struct rtclk83xx {
211 u32 cnr; /* control register */
212 #define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */
213 #define CNR_CLIN 0x00000040 /* Input Clock Control Bit */
214 #define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */
215 #define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */
216 #define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
217 u32 ldr; /* load register */
218 #define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be
219 * loaded in a 32-bit RTC counter.*/
220 u32 psr; /* prescale register */
221 #define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits. */
222 u32 ctr; /* Counter value field register */
223 #define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field. */
224 u32 evr; /* event register */
225 #define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */
226 #define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */
227 #define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF)
228 #define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit. */
229 #define PTEVR_RES ~(PTEVR_PIF)
230 u32 alr; /* alarm register */
231 u8 res0[0xE8];
232 } rtclk83xx_t;
233
234 /*
235 * Global timper module
236 */
237
238 typedef struct gtm83xx {
239 u8 cfr1; /* Timer1/2 Configuration */
240 #define CFR1_PCAS 0x80 /* Pair Cascade mode */
241 #define CFR1_BCM 0x40 /* Backward compatible mode */
242 #define CFR1_STP2 0x20 /* Stop timer */
243 #define CFR1_RST2 0x10 /* Reset timer */
244 #define CFR1_GM2 0x08 /* Gate mode for pin 2 */
245 #define CFR1_GM1 0x04 /* Gate mode for pin 1 */
246 #define CFR1_STP1 0x02 /* Stop timer */
247 #define CFR1_RST1 0x01 /* Reset timer */
248 #define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
249 CFR1_GM1 | CFR1_STP1 | CFR1_RST1)
250 u8 res0[3];
251 u8 cfr2; /* Timer3/4 Configuration */
252 #define CFR2_PCAS 0x80 /* Pair Cascade mode */
253 #define CFR2_SCAS 0x40 /* Super Cascade mode */
254 #define CFR2_STP4 0x20 /* Stop timer */
255 #define CFR2_RST4 0x10 /* Reset timer */
256 #define CFR2_GM4 0x08 /* Gate mode for pin 4 */
257 #define CFR2_GM3 0x04 /* Gate mode for pin 3 */
258 #define CFR2_STP3 0x02 /* Stop timer */
259 #define CFR2_RST3 0x01 /* Reset timer */
260 u8 res1[10];
261 u16 mdr1; /* Timer1 Mode Register */
262 #define MDR_SPS 0xff00 /* Secondary Prescaler value */
263 #define MDR_CE 0x00c0 /* Capture edge and enable interrupt */
264 #define MDR_OM 0x0020 /* Output mode */
265 #define MDR_ORI 0x0010 /* Output reference interrupt enable */
266 #define MDR_FRR 0x0008 /* Free run/restart */
267 #define MDR_ICLK 0x0006 /* Input clock source for the timer */
268 #define MDR_GE 0x0001 /* Gate enable */
269 u16 mdr2; /* Timer2 Mode Register */
270 u16 rfr1; /* Timer1 Reference Register */
271 u16 rfr2; /* Timer2 Reference Register */
272 u16 cpr1; /* Timer1 Capture Register */
273 u16 cpr2; /* Timer2 Capture Register */
274 u16 cnr1; /* Timer1 Counter Register */
275 u16 cnr2; /* Timer2 Counter Register */
276 u16 mdr3; /* Timer3 Mode Register */
277 u16 mdr4; /* Timer4 Mode Register */
278 u16 rfr3; /* Timer3 Reference Register */
279 u16 rfr4; /* Timer4 Reference Register */
280 u16 cpr3; /* Timer3 Capture Register */
281 u16 cpr4; /* Timer4 Capture Register */
282 u16 cnr3; /* Timer3 Counter Register */
283 u16 cnr4; /* Timer4 Counter Register */
284 u16 evr1; /* Timer1 Event Register */
285 u16 evr2; /* Timer2 Event Register */
286 u16 evr3; /* Timer3 Event Register */
287 u16 evr4; /* Timer4 Event Register */
288 #define GTEVR_REF 0x0002 /* Output reference event */
289 #define GTEVR_CAP 0x0001 /* Counter Capture event */
290 #define GTEVR_RES ~(EVR_CAP|EVR_REF)
291 u16 psr1; /* Timer1 Prescaler Register */
292 u16 psr2; /* Timer2 Prescaler Register */
293 u16 psr3; /* Timer3 Prescaler Register */
294 u16 psr4; /* Timer4 Prescaler Register */
295 #define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */
296 #define GTPSR_RES ~(GTPSR_PPS)
297 u8 res[0xC0];
298 } gtm83xx_t;
299
300 /*
301 * Integrated Programmable Interrupt Controller
302 */
303 typedef struct ipic83xx {
304 u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */
305 #define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */
306 #define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */
307 #define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */
308 #define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */
309 #define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */
310 #define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */
311 #define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
312 u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */
313 #define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */
314 #define SICVR_IVEC 0x0000007f /* Interrupt vector */
315 #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
316 u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */
317 #if defined (CONFIG_MPC8349)
318 #define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */
319 #define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */
320 #define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */
321 #define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */
322 #define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */
323 #define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */
324 #define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */
325 #define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */
326 #endif
327 #if defined (CONFIG_MPC8360)
328 #define SIIH_H_QE_H 0x80000000 /* QE high interrupt */
329 #define SIIH_H_QE_L 0x40000000 /* QE low interrupt */
330 #endif
331 #define SIIH_UART1 0x00000080 /* UART1 interrupt */
332 #define SIIH_UART2 0x00000040 /* UART2 interrupt */
333 #define SIIH_SEC 0x00000020 /* SEC interrupt */
334 #define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
335 #define SIIH_I2C2 0x00000002 /* I2C2 interrupt */
336 #if defined (CONFIG_MPC8349)
337 #define SIIH_SPI 0x00000001 /* SPI interrupt */
338 #define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
339 | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
340 | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
341 | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
342 | SIIH_I2C2 | SIIH_SPI)
343 #endif
344 #if defined (CONFIG_MPC8360)
345 #define SIIH_RES ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \
346 SIIH_H_UART2| SIIH_H_SEC | SIIH_H_I2C1 |SIIH_H_I2C2)
347 #endif
348 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */
349 #define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */
350 #define SIIL_PIT 0x40000000 /* PIT interrupt */
351 #define SIIL_PCI1 0x20000000 /* PCI1 interrupt */
352 #if defined (CONFIG_MPC8349)
353 #define SIIL_PCI2 0x10000000 /* PCI2 interrupt */
354 #endif
355 #define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */
356 #define SIIL_MU 0x04000000 /* Message Unit interrupt */
357 #define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */
358 #define SIIL_DMA 0x01000000 /* DMA interrupt */
359 #define SIIL_GTM4 0x00800000 /* GTM4 interrupt */
360 #define SIIL_GTM8 0x00400000 /* GTM8 interrupt */
361 #if defined (CONFIG_MPC8349)
362 #define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */
363 #define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */
364 #endif
365 #if defined (CONFIG_MPC8360)
366 #define SIIL_QEP 0x00200000 /* QE ports interrupt */
367 #define SIIL_SDDR 0x00100000 /* SDDR interrupt */
368 #endif
369 #define SIIL_DDR 0x00080000 /* DDR interrupt */
370 #define SIIL_LBC 0x00040000 /* LBC interrupt */
371 #define SIIL_GTM2 0x00020000 /* GTM2 interrupt */
372 #define SIIL_GTM6 0x00010000 /* GTM6 interrupt */
373 #define SIIL_PMC 0x00008000 /* PMC interrupt */
374 #define SIIL_GTM3 0x00000800 /* GTM3 interrupt */
375 #define SIIL_GTM7 0x00000400 /* GTM7 interrupt */
376 #define SIIL_GTM1 0x00000020 /* GTM1 interrupt */
377 #define SIIL_GTM5 0x00000010 /* GTM5 interrupt */
378 #define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */
379 #if defined (CONFIG_MPC8349)
380 #define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
381 | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
382 | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
383 | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
384 | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
385 | SIIL_GTM5 |SIIL_DPTC )
386 #endif
387 #if defined (CONFIG_MPC8360)
388 #define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \
389 |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \
390 |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \
391 |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \
392 |SIIL_GTM5 )
393 #endif
394 u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */
395 u8 res0[8];
396 u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */
397 u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */
398 u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */
399 u8 res1[4];
400 u32 sepnr; /* System External Interrupt Pending Register (SEI) */
401 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */
402 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */
403 #define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
404 #define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
405 #define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
406 #define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
407 #define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
408 #define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
409 #define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
410 #define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
411 #define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
412 u32 semsr; /* System External Interrupt Mask Register (SEI) */
413 #define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */
414 #define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */
415 #define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */
416 #define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */
417 #define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */
418 #define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */
419 #define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */
420 #define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */
421 #define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */
422 #define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
423 | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
424 | SEI_SIRQ0)
425 u32 secnr; /* System External Interrupt Control Register (SECNR) */
426 #define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */
427 #define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */
428 #define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */
429 #define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */
430 #define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */
431 #define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */
432 #define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */
433 #define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */
434 #define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */
435 #define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */
436 #define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */
437 #define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */
438 #define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
439 | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
440 | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
441 | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
442 u32 sersr; /* System Error Status Register (SERR) */
443 u32 sermr; /* System Error Mask Register (SERR) */
444 #define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */
445 #define SERR_WDT 0x40000000 /* WDT MCP request */
446 #define SERR_SBA 0x20000000 /* SBA MCP request */
447 #if defined (CONFIG_MPC8349)
448 #define SERR_DDR 0x10000000 /* DDR MCP request */
449 #define SERR_LBC 0x08000000 /* LBC MCP request */
450 #define SERR_PCI1 0x04000000 /* PCI1 MCP request */
451 #define SERR_PCI2 0x02000000 /* PCI2 MCP request */
452 #endif
453 #if defined (CONFIG_MPC8360)
454 #define SERR_CIEE 0x10000000 /* CIEE MCP request */
455 #define SERR_CMEE 0x08000000 /* CMEEMCP request */
456 #define SERR_PCI 0x04000000 /* PCI MCP request */
457 #endif
458 #define SERR_MU 0x01000000 /* MU MCP request */
459 #define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */
460 #if defined (CONFIG_MPC8349)
461 #define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
462 |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
463 |SERR_RNC )
464 #elif defined (CONFIG_MPC8360)
465 #define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\
466 |SERR_CMEE|SERR_PCI|SERR_MU)
467 #endif
468 u32 sercr; /* System Error Control Register (SERCR) */
469 #define SERCR_MCPR 0x00000001 /* MCP Route */
470 #define SERCR_RES ~(SERCR_MCPR)
471 u8 res2[4];
472 u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */
473 u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */
474 u32 sefcr; /* System External Interrupt Force Register (SEI) */
475 u32 serfr; /* System Error Force Register (SERR) */
476 u32 scvcr; /* System Critical Interrupt Vector Register */
477 #define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible
478 critical interrupt vector. */
479 #define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */
480 #define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC)
481 u32 smvcr; /* System Management Interrupt Vector Register */
482 #define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible
483 critical interrupt vector. */
484 #define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */
485 #define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC)
486 u8 res3[0x98];
487 } ipic83xx_t;
488
489 /*
490 * System Arbiter Registers
491 */
492 typedef struct arbiter83xx {
493 u32 acr; /* Arbiter Configuration Register */
494 #define ACR_COREDIS 0x10000000 /* Core disable. */
495 #define ACR_COREDIS_SHIFT (31-7)
496 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
497 #define ACR_PIPE_DEP_SHIFT (31-15)
498 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
499 #define ACR_PCI_RPTCNT_SHIFT (31-19)
500 #define ACR_RPTCNT 0x00000700 /* Repeat count. */
501 #define ACR_RPTCNT_SHIFT (31-23)
502 #define ACR_APARK 0x00000030 /* Address parking. */
503 #define ACR_APARK_SHIFT (31-27)
504 #define ACR_PARKM 0x0000000F /* Parking master. */
505 #define ACR_PARKM_SHIFT (31-31)
506 #define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
507 u32 atr; /* Arbiter Timers Register */
508 #define ATR_DTO 0x00FF0000 /* Data time out. */
509 #define ATR_ATO 0x000000FF /* Address time out. */
510 #define ATR_RES ~(ATR_DTO|ATR_ATO)
511 u8 res[4];
512 u32 aer; /* Arbiter Event Register (AE) */
513 u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
514 u32 amr; /* Arbiter Mask Register (AE) */
515 u32 aeatr; /* Arbiter Event Attributes Register */
516 #define AEATR_EVENT 0x07000000 /* Event type. */
517 #define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
518 #define AEATR_TBST 0x00000800 /* Transfer burst. */
519 #define AEATR_TSIZE 0x00000700 /* Transfer Size. */
520 #define AEATR_TTYPE 0x0000001F /* Transfer Type. */
521 #define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
522 u32 aeadr; /* Arbiter Event Address Register */
523 u32 aerr; /* Arbiter Event Response Register (AE) */
524 #define AE_ETEA 0x00000020 /* Transfer error. */
525 #define AE_RES_ 0x00000010 /* Reserved transfer type. */
526 #define AE_ECW 0x00000008 /* External control word transfer type. */
527 #define AE_AO 0x00000004 /* Address Only transfer type. */
528 #define AE_DTO 0x00000002 /* Data time out. */
529 #define AE_ATO 0x00000001 /* Address time out. */
530 #define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
531 u8 res1[0xDC];
532 } arbiter83xx_t;
533
534 /*
535 * Reset Module
536 */
537 typedef struct reset83xx {
538 u32 rcwl; /* RCWL Register */
539 #define RCWL_LBIUCM 0x80000000 /* LBIUCM */
540 #define RCWL_LBIUCM_SHIFT 31
541 #define RCWL_DDRCM 0x40000000 /* DDRCM */
542 #define RCWL_DDRCM_SHIFT 30
543 #if defined (CONFIG_MPC8349)
544 #define RCWL_SVCOD 0x30000000 /* SVCOD */
545 #endif
546 #define RCWL_SPMF 0x0f000000 /* SPMF */
547 #define RCWL_SPMF_SHIFT 24
548 #define RCWL_COREPLL 0x007F0000 /* COREPLL */
549 #define RCWL_COREPLL_SHIFT 16
550 #define RCWL_CEVCOD 0x000000C0 /* CEVCOD */
551 #define RCWL_CEPDF 0x00000020 /* CEPDF */
552 #define RCWL_CEPDF_SHIFT 5
553 #define RCWL_CEPMF 0x0000001F /* CEPMF */
554 #define RCWL_CEPMF_SHIFT 0
555 #if defined (CONFIG_MPC8349)
556 #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
557 #elif defined (CONFIG_MPC8360)
558 #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF)
559 #endif
560 u32 rcwh; /* RCHL Register */
561 #define RCWH_PCIHOST 0x80000000 /* PCIHOST */
562 #define RCWH_PCIHOST_SHIFT 31
563 #if defined (CONFIG_MPC8349)
564 #define RCWH_PCI64 0x40000000 /* PCI64 */
565 #define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */
566 #define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */
567 #elif defined (CONFIG_MPC8360)
568 #define RCWH_PCIARB 0x20000000 /* PCI internal arbiter mode. */
569 #define RCWH_PCICKDRV 0x10000000 /* PCI clock output drive. */
570 #endif
571 #define RCWH_COREDIS 0x08000000 /* COREDIS */
572 #define RCWH_BMS 0x04000000 /* BMS */
573 #define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */
574 #define RCWH_SWEN 0x00800000 /* SWEN */
575 #define RCWH_ROMLOC 0x00700000 /* ROMLOC */
576 #if defined (CONFIG_MPC8349)
577 #define RCWH_TSEC1M 0x0000c000 /* TSEC1M */
578 #define RCWH_TSEC2M 0x00003000 /* TSEC2M */
579 #define RCWH_TPR 0x00000100 /* TPR */
580 #elif defined (CONFIG_MPC8360)
581 #define RCWH_SDDRIOE 0x00000010 /* Secondary DDR IO Enable. */
582 #endif
583 #define RCWH_TLE 0x00000008 /* TLE */
584 #define RCWH_LALE 0x00000004 /* LALE */
585 #if defined (CONFIG_MPC8349)
586 #define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
587 | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
588 | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
589 | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
590 | RCWH_TLE | RCWH_LALE)
591 #elif defined (CONFIG_MPC8360)
592 #define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \
593 |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \
594 |RCWH_SDDRIOE |RCWH_TLE)
595 #endif
596 u8 res0[8];
597 u32 rsr; /* Reset status Register */
598 #define RSR_RSTSRC 0xE0000000 /* Reset source */
599 #define RSR_RSTSRC_SHIFT 29
600 #define RSR_BSF 0x00010000 /* Boot seq. fail */
601 #define RSR_BSF_SHIFT 16
602 #define RSR_SWSR 0x00002000 /* software soft reset */
603 #define RSR_SWSR_SHIFT 13
604 #define RSR_SWHR 0x00001000 /* software hard reset */
605 #define RSR_SWHR_SHIFT 12
606 #define RSR_JHRS 0x00000200 /* jtag hreset */
607 #define RSR_JHRS_SHIFT 9
608 #define RSR_JSRS 0x00000100 /* jtag sreset status */
609 #define RSR_JSRS_SHIFT 8
610 #define RSR_CSHR 0x00000010 /* checkstop reset status */
611 #define RSR_CSHR_SHIFT 4
612 #define RSR_SWRS 0x00000008 /* software watchdog reset status */
613 #define RSR_SWRS_SHIFT 3
614 #define RSR_BMRS 0x00000004 /* bus monitop reset status */
615 #define RSR_BMRS_SHIFT 2
616 #define RSR_SRS 0x00000002 /* soft reset status */
617 #define RSR_SRS_SHIFT 1
618 #define RSR_HRS 0x00000001 /* hard reset status */
619 #define RSR_HRS_SHIFT 0
620 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
621 u32 rmr; /* Reset mode Register */
622 #define RMR_CSRE 0x00000001 /* checkstop reset enable */
623 #define RMR_CSRE_SHIFT 0
624 #define RMR_RES ~(RMR_CSRE)
625 u32 rpr; /* Reset protection Register */
626 u32 rcr; /* Reset Control Register */
627 #define RCR_SWHR 0x00000002 /* software hard reset */
628 #define RCR_SWSR 0x00000001 /* software soft reset */
629 #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
630 u32 rcer; /* Reset Control Enable Register */
631 #define RCER_CRE 0x00000001 /* software hard reset */
632 #define RCER_RES ~(RCER_CRE)
633 u8 res1[0xDC];
634 } reset83xx_t;
635
636 typedef struct clk83xx {
637 u32 spmr; /* system PLL mode Register */
638 #define SPMR_LBIUCM 0x80000000 /* LBIUCM */
639 #define SPMR_DDRCM 0x40000000 /* DDRCM */
640 #if defined (CONFIG_MPC8349)
641 #define SPMR_SVCOD 0x30000000 /* SVCOD */
642 #endif
643 #define SPMR_SPMF 0x0F000000 /* SPMF */
644 #define SPMR_CKID 0x00800000 /* CKID */
645 #define SPMR_CKID_SHIFT 23
646 #define SPMR_COREPLL 0x007F0000 /* COREPLL */
647 #define SPMR_CEVCOD 0x000000C0 /* CEVCOD */
648 #define SPMR_CEPDF 0x00000020 /* CEPDF */
649 #define SPMR_CEPMF 0x0000001F /* CEPMF */
650 #if defined (CONFIG_MPC8349)
651 #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
652 | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
653 | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
654 #elif defined (CONFIG_MPC8360)
655 #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \
656 | SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \
657 | SPMR_CEPDF | SPMR_CEPMF)
658 #endif
659 u32 occr; /* output clock control Register */
660 #define OCCR_PCICOE0 0x80000000 /* PCICOE0 */
661 #define OCCR_PCICOE1 0x40000000 /* PCICOE1 */
662 #define OCCR_PCICOE2 0x20000000 /* PCICOE2 */
663 #if defined (CONFIG_MPC8349)
664 #define OCCR_PCICOE3 0x10000000 /* PCICOE3 */
665 #define OCCR_PCICOE4 0x08000000 /* PCICOE4 */
666 #define OCCR_PCICOE5 0x04000000 /* PCICOE5 */
667 #define OCCR_PCICOE6 0x02000000 /* PCICOE6 */
668 #define OCCR_PCICOE7 0x01000000 /* PCICOE7 */
669 #endif
670 #define OCCR_PCICD0 0x00800000 /* PCICD0 */
671 #define OCCR_PCICD1 0x00400000 /* PCICD1 */
672 #define OCCR_PCICD2 0x00200000 /* PCICD2 */
673 #if defined (CONFIG_MPC8349)
674 #define OCCR_PCICD3 0x00100000 /* PCICD3 */
675 #define OCCR_PCICD4 0x00080000 /* PCICD4 */
676 #define OCCR_PCICD5 0x00040000 /* PCICD5 */
677 #define OCCR_PCICD6 0x00020000 /* PCICD6 */
678 #define OCCR_PCICD7 0x00010000 /* PCICD7 */
679 #define OCCR_PCI1CR 0x00000002 /* PCI1CR */
680 #define OCCR_PCI2CR 0x00000001 /* PCI2CR */
681 #define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
682 | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
683 | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
684 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \
685 | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \
686 | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR )
687 #endif
688 #if defined (CONFIG_MPC8360)
689 #define OCCR_PCICR 0x00000002 /* PCI clock rate */
690 #define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \
691 |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR )
692 #endif
693 u32 sccr; /* system clock control Register */
694 #if defined (CONFIG_MPC8349)
695 #define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */
696 #define SCCR_TSEC1CM_SHIFT 30
697 #define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */
698 #define SCCR_TSEC2CM_SHIFT 28
699 #endif
700 #define SCCR_ENCCM 0x03000000 /* ENCCM */
701 #define SCCR_ENCCM_SHIFT 24
702 #if defined (CONFIG_MPC8349)
703 #define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */
704 #define SCCR_USBMPHCM_SHIFT 22
705 #define SCCR_USBDRCM 0x00300000 /* USBDRCM */
706 #define SCCR_USBDRCM_SHIFT 20
707 #endif
708 #define SCCR_PCICM 0x00010000 /* PCICM */
709 #if defined (CONFIG_MPC8349)
710 #define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
711 | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
712 #endif
713 #if defined (CONFIG_MPC8360)
714 #define SCCR_RES ~(SCCR_ENCCM | SCCR_PCICM)
715 #endif
716 u8 res0[0xF4];
717 } clk83xx_t;
718
719 /*
720 * Power Management Control Module
721 */
722 typedef struct pmc83xx {
723 u32 pmccr; /* PMC Configuration Register */
724 #define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
725 #define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
726 #if defined (CONFIG_MPC8360)
727 #define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */
728 #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN)
729 #elif defined (CONFIG_MPC8349)
730 #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
731 #endif
732 u32 pmcer; /* PMC Event Register */
733 #define PMCER_PMCI 0x00000001 /* PMC Interrupt */
734 #define PMCER_RES ~(PMCER_PMCI)
735 u32 pmcmr; /* PMC Mask Register */
736 #define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */
737 #define PMCMR_RES ~(PMCMR_PMCIE)
738 u8 res0[0xF4];
739 } pmc83xx_t;
740
741 #if defined (CONFIG_MPC8349)
742 /*
743 * general purpose I/O module
744 */
745 typedef struct gpio83xx {
746 u32 dir; /* direction register */
747 u32 odr; /* open drain register */
748 u32 dat; /* data register */
749 u32 ier; /* interrupt event register */
750 u32 imr; /* interrupt mask register */
751 u32 icr; /* external interrupt control register */
752 u8 res0[0xE8];
753 } gpio83xx_t;
754 #endif
755
756 #if defined (CONFIG_MPC8360)
757 /*
758 * QE Ports Interrupts Registers
759 */
760 typedef struct qepi83xx {
761 u8 res0[0xC];
762 u32 qepier; /* QE Ports Interrupt Event Register */
763 #define QEPIER_PA15 0x80000000
764 #define QEPIER_PA16 0x40000000
765 #define QEPIER_PA29 0x20000000
766 #define QEPIER_PA30 0x10000000
767 #define QEPIER_PB3 0x08000000
768 #define QEPIER_PB5 0x04000000
769 #define QEPIER_PB12 0x02000000
770 #define QEPIER_PB13 0x01000000
771 #define QEPIER_PB26 0x00800000
772 #define QEPIER_PB27 0x00400000
773 #define QEPIER_PC27 0x00200000
774 #define QEPIER_PC28 0x00100000
775 #define QEPIER_PC29 0x00080000
776 #define QEPIER_PD12 0x00040000
777 #define QEPIER_PD13 0x00020000
778 #define QEPIER_PD16 0x00010000
779 #define QEPIER_PD17 0x00008000
780 #define QEPIER_PD26 0x00004000
781 #define QEPIER_PD27 0x00002000
782 #define QEPIER_PE12 0x00001000
783 #define QEPIER_PE13 0x00000800
784 #define QEPIER_PE24 0x00000400
785 #define QEPIER_PE25 0x00000200
786 #define QEPIER_PE26 0x00000100
787 #define QEPIER_PE27 0x00000080
788 #define QEPIER_PE31 0x00000040
789 #define QEPIER_PF20 0x00000020
790 #define QEPIER_PG31 0x00000010
791 #define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \
792 |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \
793 |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \
794 |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \
795 |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \
796 |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31)
797 u32 qepimr; /* QE Ports Interrupt Mask Register */
798 #define QEPIMR_PA15 0x80000000
799 #define QEPIMR_PA16 0x40000000
800 #define QEPIMR_PA29 0x20000000
801 #define QEPIMR_PA30 0x10000000
802 #define QEPIMR_PB3 0x08000000
803 #define QEPIMR_PB5 0x04000000
804 #define QEPIMR_PB12 0x02000000
805 #define QEPIMR_PB13 0x01000000
806 #define QEPIMR_PB26 0x00800000
807 #define QEPIMR_PB27 0x00400000
808 #define QEPIMR_PC27 0x00200000
809 #define QEPIMR_PC28 0x00100000
810 #define QEPIMR_PC29 0x00080000
811 #define QEPIMR_PD12 0x00040000
812 #define QEPIMR_PD13 0x00020000
813 #define QEPIMR_PD16 0x00010000
814 #define QEPIMR_PD17 0x00008000
815 #define QEPIMR_PD26 0x00004000
816 #define QEPIMR_PD27 0x00002000
817 #define QEPIMR_PE12 0x00001000
818 #define QEPIMR_PE13 0x00000800
819 #define QEPIMR_PE24 0x00000400
820 #define QEPIMR_PE25 0x00000200
821 #define QEPIMR_PE26 0x00000100
822 #define QEPIMR_PE27 0x00000080
823 #define QEPIMR_PE31 0x00000040
824 #define QEPIMR_PF20 0x00000020
825 #define QEPIMR_PG31 0x00000010
826 #define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \
827 |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \
828 |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \
829 |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \
830 |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \
831 |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31)
832 u32 qepicr; /* QE Ports Interrupt Control Register */
833 #define QEPICR_PA15 0x80000000
834 #define QEPICR_PA16 0x40000000
835 #define QEPICR_PA29 0x20000000
836 #define QEPICR_PA30 0x10000000
837 #define QEPICR_PB3 0x08000000
838 #define QEPICR_PB5 0x04000000
839 #define QEPICR_PB12 0x02000000
840 #define QEPICR_PB13 0x01000000
841 #define QEPICR_PB26 0x00800000
842 #define QEPICR_PB27 0x00400000
843 #define QEPICR_PC27 0x00200000
844 #define QEPICR_PC28 0x00100000
845 #define QEPICR_PC29 0x00080000
846 #define QEPICR_PD12 0x00040000
847 #define QEPICR_PD13 0x00020000
848 #define QEPICR_PD16 0x00010000
849 #define QEPICR_PD17 0x00008000
850 #define QEPICR_PD26 0x00004000
851 #define QEPICR_PD27 0x00002000
852 #define QEPICR_PE12 0x00001000
853 #define QEPICR_PE13 0x00000800
854 #define QEPICR_PE24 0x00000400
855 #define QEPICR_PE25 0x00000200
856 #define QEPICR_PE26 0x00000100
857 #define QEPICR_PE27 0x00000080
858 #define QEPICR_PE31 0x00000040
859 #define QEPICR_PF20 0x00000020
860 #define QEPICR_PG31 0x00000010
861 #define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \
862 |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \
863 |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \
864 |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \
865 |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \
866 |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31)
867 u8 res1[0xE8];
868 } qepi83xx_t;
869
870 /*
871 * general purpose I/O module
872 */
873 typedef struct gpio_n {
874 u32 podr; /* Open Drain Register */
875 u32 pdat; /* Data Register */
876 u32 dir1; /* direction register 1 */
877 u32 dir2; /* direction register 2 */
878 u32 ppar1; /* Pin Assignment Register 1 */
879 u32 ppar2; /* Pin Assignment Register 2 */
880 } gpio_n_t;
881
882 typedef struct gpio83xx {
883 gpio_n_t ioport[0x7];
884 u8 res0[0x358];
885 } gpio83xx_t;
886
887 /*
888 * QE Secondary Bus Access Windows
889 */
890
891 typedef struct qesba83xx {
892 u32 lbmcsar; /* Local bus memory controller start address */
893 #define LBMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */
894 #define LBMCSAR_RES ~(LBMCSAR_SA)
895 u32 sdmcsar; /* Secondary DDR memory controller start address */
896 #define SDMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */
897 #define SDMCSAR_RES ~(SDMCSAR_SA)
898 u8 res0[0x38];
899 u32 lbmcear; /* Local bus memory controller end address */
900 #define LBMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */
901 #define LBMCEAR_RES ~(LBMCEAR_EA)
902 u32 sdmcear; /* Secondary DDR memory controller end address */
903 #define SDMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */
904 #define SDMCEAR_RES ~(SDMCEAR_EA)
905 u8 res1[0x38];
906 u32 lbmcar; /* Local bus memory controller attributes */
907 #define LBMCAR_WEN 0x00000001 /* Forward transactions to the QE local bus */
908 #define LBMCAR_RES ~(LBMCAR_WEN)
909 u32 sdmcar; /* Secondary DDR memory controller attributes */
910 #define SDMCAR_WEN 0x00000001 /* Forward transactions to the second DDR bus */
911 #define SDMCAR_RES ~(SDMCAR_WEN)
912 u8 res2[0x778];
913 } qesba83xx_t;
914 #endif
915
916 /*
917 * DDR Memory Controller Memory Map
918 */
919 typedef struct ddr_cs_bnds {
920 u32 csbnds;
921 #define CSBNDS_SA 0x00FF0000
922 #define CSBNDS_SA_SHIFT 8
923 #define CSBNDS_EA 0x000000FF
924 #define CSBNDS_EA_SHIFT 24
925 u8 res0[4];
926 } ddr_cs_bnds_t;
927
928 typedef struct ddr83xx {
929 ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */
930 u8 res0[0x60];
931 u32 cs_config[4]; /**< Chip Select x Configuration */
932 #define CSCONFIG_EN 0x80000000
933 #define CSCONFIG_AP 0x00800000
934 #define CSCONFIG_ROW_BIT 0x00000700
935 #define CSCONFIG_ROW_BIT_12 0x00000000
936 #define CSCONFIG_ROW_BIT_13 0x00000100
937 #define CSCONFIG_ROW_BIT_14 0x00000200
938 #define CSCONFIG_COL_BIT 0x00000007
939 #define CSCONFIG_COL_BIT_8 0x00000000
940 #define CSCONFIG_COL_BIT_9 0x00000001
941 #define CSCONFIG_COL_BIT_10 0x00000002
942 #define CSCONFIG_COL_BIT_11 0x00000003
943 u8 res1[0x78];
944 u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */
945 #define TIMING_CFG1_PRETOACT 0x70000000
946 #define TIMING_CFG1_PRETOACT_SHIFT 28
947 #define TIMING_CFG1_ACTTOPRE 0x0F000000
948 #define TIMING_CFG1_ACTTOPRE_SHIFT 24
949 #define TIMING_CFG1_ACTTORW 0x00700000
950 #define TIMING_CFG1_ACTTORW_SHIFT 20
951 #define TIMING_CFG1_CASLAT 0x00070000
952 #define TIMING_CFG1_CASLAT_SHIFT 16
953 #define TIMING_CFG1_REFREC 0x0000F000
954 #define TIMING_CFG1_REFREC_SHIFT 12
955 #define TIMING_CFG1_WRREC 0x00000700
956 #define TIMING_CFG1_WRREC_SHIFT 8
957 #define TIMING_CFG1_ACTTOACT 0x00000070
958 #define TIMING_CFG1_ACTTOACT_SHIFT 4
959 #define TIMING_CFG1_WRTORD 0x00000007
960 #define TIMING_CFG1_WRTORD_SHIFT 0
961 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
962 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
963
964 u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
965 #define TIMING_CFG2_CPO 0x0F000000
966 #define TIMING_CFG2_CPO_SHIFT 24
967 #define TIMING_CFG2_ACSM 0x00080000
968 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
969 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
970 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
971
972 u32 sdram_cfg; /**< SDRAM Control Configuration */
973 #define SDRAM_CFG_MEM_EN 0x80000000
974 #define SDRAM_CFG_SREN 0x40000000
975 #define SDRAM_CFG_ECC_EN 0x20000000
976 #define SDRAM_CFG_RD_EN 0x10000000
977 #define SDRAM_CFG_SDRAM_TYPE 0x03000000
978 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
979 #define SDRAM_CFG_DYN_PWR 0x00200000
980 #define SDRAM_CFG_32_BE 0x00080000
981 #define SDRAM_CFG_8_BE 0x00040000
982 #define SDRAM_CFG_NCAP 0x00020000
983 #define SDRAM_CFG_2T_EN 0x00008000
984 #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
985
986 u8 res2[4];
987 u32 sdram_mode; /**< SDRAM Mode Configuration */
988 #define SDRAM_MODE_ESD 0xFFFF0000
989 #define SDRAM_MODE_ESD_SHIFT 16
990 #define SDRAM_MODE_SD 0x0000FFFF
991 #define SDRAM_MODE_SD_SHIFT 0
992 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
993 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
994 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
995 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
996 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
997 #define DDR_MODE_WEAK 0x0002 /* weak drivers */
998 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
999 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
1000 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
1001 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
1002 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
1003 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
1004 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
1005 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
1006 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
1007 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
1008 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */
1009 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
1010 #define DDR_MODE_MODEREG 0x0000 /* select mode register */
1011
1012 u8 res3[8];
1013 u32 sdram_interval; /**< SDRAM Interval Configuration */
1014 #define SDRAM_INTERVAL_REFINT 0x3FFF0000
1015 #define SDRAM_INTERVAL_REFINT_SHIFT 16
1016 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
1017 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
1018 u8 res9[8];
1019 u32 sdram_clk_cntl;
1020 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
1021 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
1022 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
1023 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
1024 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
1025
1026 u8 res4[0xCCC];
1027 u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
1028 u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
1029 u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */
1030 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
1031 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
1032 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
1033 #define ECC_ERR_INJECT_EEIM_SHIFT 0
1034 u8 res5[0x14];
1035 u32 capture_data_hi; /**< Memory Data Path Read Capture High */
1036 u32 capture_data_lo; /**< Memory Data Path Read Capture Low */
1037 u32 capture_ecc; /**< Memory Data Path Read Capture ECC */
1038 #define CAPTURE_ECC_ECE (0xff000000>>24)
1039 #define CAPTURE_ECC_ECE_SHIFT 0
1040 u8 res6[0x14];
1041 u32 err_detect; /**< Memory Error Detect */
1042 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
1043 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
1044 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
1045 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
1046 u32 err_disable; /**< Memory Error Disable */
1047 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
1048 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
1049 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
1050 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
1051 u32 err_int_en; /**< Memory Error Interrupt Enable */
1052 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
1053 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
1054 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
1055 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
1056 u32 capture_attributes; /**< Memory Error Attributes Capture */
1057 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
1058 #define ECC_CAPT_ATTR_BNUM_SHIFT 28
1059 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
1060 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
1061 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
1062 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
1063 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
1064 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24
1065 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
1066 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
1067 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1068 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
1069 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
1070 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
1071 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
1072 #define ECC_CAPT_ATTR_TSRC_I2C 0x9
1073 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA
1074 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD
1075 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE
1076 #define ECC_CAPT_ATTR_TSRC_DMA 0xF
1077 #define ECC_CAPT_ATTR_TSRC_SHIFT 16
1078 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
1079 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1
1080 #define ECC_CAPT_ATTR_TTYP_READ 0x2
1081 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
1082 #define ECC_CAPT_ATTR_TTYP_SHIFT 12
1083 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
1084 u32 capture_address; /**< Memory Error Address Capture */
1085 u32 capture_ext_address;/**< Memory Error Extended Address Capture */
1086 u32 err_sbe; /**< Memory Single-Bit ECC Error Management */
1087 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
1088 #define ECC_ERROR_MAN_SBET_SHIFT 16
1089 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
1090 #define ECC_ERROR_MAN_SBEC_SHIFT 0
1091 u8 res7[0xA4];
1092 u32 debug_reg;
1093 u8 res8[0xFC];
1094 } ddr83xx_t;
1095
1096 /*
1097 * I2C1 Controller
1098 */
1099
1100 /*
1101 * DUART
1102 */
1103 typedef struct duart83xx {
1104 u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
1105 u8 uier_udmb; /**< combined register for UIER and UDMB */
1106 u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
1107 u8 ulcr; /**< line control register */
1108 u8 umcr; /**< MODEM control register */
1109 u8 ulsr; /**< line status register */
1110 u8 umsr; /**< MODEM status register */
1111 u8 uscr; /**< scratch register */
1112 u8 res0[8];
1113 u8 udsr; /**< DMA status register */
1114 u8 res1[3];
1115 u8 res2[0xEC];
1116 } duart83xx_t;
1117
1118 /*
1119 * Local Bus Controller Registers
1120 */
1121 typedef struct lbus_bank {
1122 u32 br; /**< Base Register */
1123 u32 or; /**< Base Register */
1124 } lbus_bank_t;
1125
1126 typedef struct lbus83xx {
1127 lbus_bank_t bank[8];
1128 u8 res0[0x28];
1129 u32 mar; /**< UPM Address Register */
1130 u8 res1[0x4];
1131 u32 mamr; /**< UPMA Mode Register */
1132 u32 mbmr; /**< UPMB Mode Register */
1133 u32 mcmr; /**< UPMC Mode Register */
1134 u8 res2[0x8];
1135 u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
1136 u32 mdr; /**< UPM Data Register */
1137 u8 res3[0x8];
1138 u32 lsdmr; /**< SDRAM Mode Register */
1139 u8 res4[0x8];
1140 u32 lurt; /**< UPM Refresh Timer */
1141 u32 lsrt; /**< SDRAM Refresh Timer */
1142 u8 res5[0x8];
1143 u32 ltesr; /**< Transfer Error Status Register */
1144 u32 ltedr; /**< Transfer Error Disable Register */
1145 u32 lteir; /**< Transfer Error Interrupt Register */
1146 u32 lteatr; /**< Transfer Error Attributes Register */
1147 u32 ltear; /**< Transfer Error Address Register */
1148 u8 res6[0xC];
1149 u32 lbcr; /**< Configuration Register */
1150 #define LBCR_LDIS 0x80000000
1151 #define LBCR_LDIS_SHIFT 31
1152 #define LBCR_BCTLC 0x00C00000
1153 #define LBCR_BCTLC_SHIFT 22
1154 #define LBCR_LPBSE 0x00020000
1155 #define LBCR_LPBSE_SHIFT 17
1156 #define LBCR_EPAR 0x00010000
1157 #define LBCR_EPAR_SHIFT 16
1158 #define LBCR_BMT 0x0000FF00
1159 #define LBCR_BMT_SHIFT 8
1160 u32 lcrr; /**< Clock Ratio Register */
1161 #define LCRR_DBYP 0x80000000
1162 #define LCRR_DBYP_SHIFT 31
1163 #define LCRR_BUFCMDC 0x30000000
1164 #define LCRR_BUFCMDC_SHIFT 28
1165 #define LCRR_ECL 0x03000000
1166 #define LCRR_ECL_SHIFT 24
1167 #define LCRR_EADC 0x00030000
1168 #define LCRR_EADC_SHIFT 16
1169 #define LCRR_CLKDIV 0x0000000F
1170 #define LCRR_CLKDIV_SHIFT 0
1171
1172 u8 res7[0x28];
1173 u8 res8[0xF00];
1174 } lbus83xx_t;
1175
1176 #if defined (CONFIG_MPC8349)
1177 /*
1178 * Serial Peripheral Interface
1179 */
1180 typedef struct spi83xx {
1181 u32 mode; /**< mode register */
1182 u32 event; /**< event register */
1183 u32 mask; /**< mask register */
1184 u32 com; /**< command register */
1185 u8 res0[0x10];
1186 u32 tx; /**< transmit register */
1187 u32 rx; /**< receive register */
1188 u8 res1[0xD8];
1189 } spi83xx_t;
1190 #endif
1191
1192 /*
1193 * DMA/Messaging Unit
1194 */
1195 typedef struct dma83xx {
1196 u32 res0[0xC]; /* 0x0-0x29 reseverd */
1197 u32 omisr; /* 0x30 Outbound message interrupt status register */
1198 u32 omimr; /* 0x34 Outbound message interrupt mask register */
1199 u32 res1[0x6]; /* 0x38-0x49 reserved */
1200
1201 u32 imr0; /* 0x50 Inbound message register 0 */
1202 u32 imr1; /* 0x54 Inbound message register 1 */
1203 u32 omr0; /* 0x58 Outbound message register 0 */
1204 u32 omr1; /* 0x5C Outbound message register 1 */
1205
1206 u32 odr; /* 0x60 Outbound doorbell register */
1207 u32 res2; /* 0x64-0x67 reserved */
1208 u32 idr; /* 0x68 Inbound doorbell register */
1209 u32 res3[0x5]; /* 0x6C-0x79 reserved */
1210
1211 u32 imisr; /* 0x80 Inbound message interrupt status register */
1212 u32 imimr; /* 0x84 Inbound message interrupt mask register */
1213 u32 res4[0x1E]; /* 0x88-0x99 reserved */
1214
1215 u32 dmamr0; /* 0x100 DMA 0 mode register */
1216 u32 dmasr0; /* 0x104 DMA 0 status register */
1217 u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */
1218 u32 res5; /* 0x10C reserved */
1219 u32 dmasar0; /* 0x110 DMA 0 source address register */
1220 u32 res6; /* 0x114 reserved */
1221 u32 dmadar0; /* 0x118 DMA 0 destination address register */
1222 u32 res7; /* 0x11C reserved */
1223 u32 dmabcr0; /* 0x120 DMA 0 byte count register */
1224 u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */
1225 u32 res8[0x16]; /* 0x128-0x179 reserved */
1226
1227 u32 dmamr1; /* 0x180 DMA 1 mode register */
1228 u32 dmasr1; /* 0x184 DMA 1 status register */
1229 u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */
1230 u32 res9; /* 0x18C reserved */
1231 u32 dmasar1; /* 0x190 DMA 1 source address register */
1232 u32 res10; /* 0x194 reserved */
1233 u32 dmadar1; /* 0x198 DMA 1 destination address register */
1234 u32 res11; /* 0x19C reserved */
1235 u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */
1236 u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */
1237 u32 res12[0x16]; /* 0x1A8-0x199 reserved */
1238
1239 u32 dmamr2; /* 0x200 DMA 2 mode register */
1240 u32 dmasr2; /* 0x204 DMA 2 status register */
1241 u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */
1242 u32 res13; /* 0x20C reserved */
1243 u32 dmasar2; /* 0x210 DMA 2 source address register */
1244 u32 res14; /* 0x214 reserved */
1245 u32 dmadar2; /* 0x218 DMA 2 destination address register */
1246 u32 res15; /* 0x21C reserved */
1247 u32 dmabcr2; /* 0x220 DMA 2 byte count register */
1248 u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */
1249 u32 res16[0x16]; /* 0x228-0x279 reserved */
1250
1251 u32 dmamr3; /* 0x280 DMA 3 mode register */
1252 u32 dmasr3; /* 0x284 DMA 3 status register */
1253 u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */
1254 u32 res17; /* 0x28C reserved */
1255 u32 dmasar3; /* 0x290 DMA 3 source address register */
1256 u32 res18; /* 0x294 reserved */
1257 u32 dmadar3; /* 0x298 DMA 3 destination address register */
1258 u32 res19; /* 0x29C reserved */
1259 u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */
1260 u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */
1261
1262 u32 dmagsr; /* 0x2A8 DMA general status register */
1263 u32 res20[0x15]; /* 0x2AC-0x2FF reserved */
1264 } dma83xx_t;
1265
1266 /* DMAMRn bits */
1267 #define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */
1268 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */
1269 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */
1270 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */
1271 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */
1272 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */
1273 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */
1274 #define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */
1275
1276 /* DMASRn bits */
1277 #define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */
1278 #define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */
1279
1280 /*
1281 * PCI Software Configuration Registers
1282 */
1283 typedef struct pciconf83xx {
1284 u32 config_address;
1285 #define PCI_CONFIG_ADDRESS_EN 0x80000000
1286 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16
1287 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
1288 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11
1289 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
1290 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8
1291 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
1292 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0
1293 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
1294 u32 config_data;
1295 u32 int_ack;
1296 u8 res[116];
1297 } pciconf83xx_t;
1298
1299 /*
1300 * PCI Outbound Translation Register
1301 */
1302 typedef struct pci_outbound_window {
1303 u32 potar;
1304 u8 res0[4];
1305 u32 pobar;
1306 u8 res1[4];
1307 u32 pocmr;
1308 u8 res2[4];
1309 } pot83xx_t;
1310
1311 /*
1312 * Sequencer
1313 */
1314 typedef struct ios83xx {
1315 pot83xx_t pot[6];
1316 #define POTAR_TA_MASK 0x000fffff
1317 #define POBAR_BA_MASK 0x000fffff
1318 #define POCMR_EN 0x80000000
1319 #define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
1320 #define POCMR_SE 0x20000000 /* streaming enable */
1321 #define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */
1322 #define POCMR_CM_MASK 0x000fffff
1323 #define POCMR_CM_4G 0x00000000
1324 #define POCMR_CM_2G 0x00080000
1325 #define POCMR_CM_1G 0x000C0000
1326 #define POCMR_CM_512M 0x000E0000
1327 #define POCMR_CM_256M 0x000F0000
1328 #define POCMR_CM_128M 0x000F8000
1329 #define POCMR_CM_64M 0x000FC000
1330 #define POCMR_CM_32M 0x000FE000
1331 #define POCMR_CM_16M 0x000FF000
1332 #define POCMR_CM_8M 0x000FF800
1333 #define POCMR_CM_4M 0x000FFC00
1334 #define POCMR_CM_2M 0x000FFE00
1335 #define POCMR_CM_1M 0x000FFF00
1336 #define POCMR_CM_512K 0x000FFF80
1337 #define POCMR_CM_256K 0x000FFFC0
1338 #define POCMR_CM_128K 0x000FFFE0
1339 #define POCMR_CM_64K 0x000FFFF0
1340 #define POCMR_CM_32K 0x000FFFF8
1341 #define POCMR_CM_16K 0x000FFFFC
1342 #define POCMR_CM_8K 0x000FFFFE
1343 #define POCMR_CM_4K 0x000FFFFF
1344 u8 res0[0x60];
1345 u32 pmcr;
1346 u8 res1[4];
1347 u32 dtcr;
1348 u8 res2[4];
1349 } ios83xx_t;
1350
1351 /*
1352 * PCI Controller Control and Status Registers
1353 */
1354 typedef struct pcictrl83xx {
1355 u32 esr;
1356 #define ESR_MERR 0x80000000
1357 #define ESR_APAR 0x00000400
1358 #define ESR_PCISERR 0x00000200
1359 #define ESR_MPERR 0x00000100
1360 #define ESR_TPERR 0x00000080
1361 #define ESR_NORSP 0x00000040
1362 #define ESR_TABT 0x00000020
1363 u32 ecdr;
1364 #define ECDR_APAR 0x00000400
1365 #define ECDR_PCISERR 0x00000200
1366 #define ECDR_MPERR 0x00000100
1367 #define ECDR_TPERR 0x00000080
1368 #define ECDR_NORSP 0x00000040
1369 #define ECDR_TABT 0x00000020
1370 u32 eer;
1371 #define EER_APAR 0x00000400
1372 #define EER_PCISERR 0x00000200
1373 #define EER_MPERR 0x00000100
1374 #define EER_TPERR 0x00000080
1375 #define EER_NORSP 0x00000040
1376 #define EER_TABT 0x00000020
1377 u32 eatcr;
1378 #define EATCR_ERRTYPR_MASK 0x70000000
1379 #define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */
1380 #define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */
1381 #define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */
1382 #define EATCR_ERRTYPR_MA 0x30000000 /* master abort */
1383 #define EATCR_ERRTYPR_TA 0x40000000 /* target abort */
1384 #define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */
1385 #define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */
1386 #define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */
1387 #define EATCR_BN_MASK 0x0f000000 /* beat number */
1388 #define EATCR_BN_1st 0x00000000
1389 #define EATCR_BN_2ed 0x01000000
1390 #define EATCR_BN_3rd 0x02000000
1391 #define EATCR_BN_4th 0x03000000
1392 #define EATCR_BN_5th 0x0400000
1393 #define EATCR_BN_6th 0x05000000
1394 #define EATCR_BN_7th 0x06000000
1395 #define EATCR_BN_8th 0x07000000
1396 #define EATCR_BN_9th 0x08000000
1397 #define EATCR_TS_MASK 0x00300000 /* transaction size */
1398 #define EATCR_TS_4 0x00000000
1399 #define EATCR_TS_1 0x00100000
1400 #define EATCR_TS_2 0x00200000
1401 #define EATCR_TS_3 0x00300000
1402 #define EATCR_ES_MASK 0x000f0000 /* error source */
1403 #define EATCR_ES_EM 0x00000000 /* external master */
1404 #define EATCR_ES_DMA 0x00050000
1405 #define EATCR_CMD_MASK 0x0000f000
1406 #if defined (CONFIG_MPC8349)
1407 #define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */
1408 #endif
1409 #define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */
1410 #if defined (CONFIG_MPC8349)
1411 #define EATCR_HPB 0x00000004 /* high parity bit */
1412 #endif
1413 #define EATCR_PB 0x00000002 /* parity bit */
1414 #define EATCR_VI 0x00000001 /* error information valid */
1415 u32 eacr;
1416 u32 eeacr;
1417 #if defined (CONFIG_MPC8349)
1418 u32 edlcr;
1419 u32 edhcr;
1420 #elif defined (CONFIG_MPC8360)
1421 u32 edcr; /* was edlcr */
1422 u8 res_edcr[0x4];
1423 #endif
1424 u32 gcr;
1425 u32 ecr;
1426 u32 gsr;
1427 u8 res0[12];
1428 u32 pitar2;
1429 u8 res1[4];
1430 u32 pibar2;
1431 u32 piebar2;
1432 u32 piwar2;
1433 u8 res2[4];
1434 u32 pitar1;
1435 u8 res3[4];
1436 u32 pibar1;
1437 u32 piebar1;
1438 u32 piwar1;
1439 u8 res4[4];
1440 u32 pitar0;
1441 u8 res5[4];
1442 u32 pibar0;
1443 u8 res6[4];
1444 u32 piwar0;
1445 u8 res7[132];
1446 #define PITAR_TA_MASK 0x000fffff
1447 #define PIBAR_MASK 0xffffffff
1448 #define PIEBAR_EBA_MASK 0x000fffff
1449 #define PIWAR_EN 0x80000000
1450 #define PIWAR_PF 0x20000000
1451 #define PIWAR_RTT_MASK 0x000f0000
1452 #define PIWAR_RTT_NO_SNOOP 0x00040000
1453 #define PIWAR_RTT_SNOOP 0x00050000
1454 #define PIWAR_WTT_MASK 0x0000f000
1455 #define PIWAR_WTT_NO_SNOOP 0x00004000
1456 #define PIWAR_WTT_SNOOP 0x00005000
1457 #define PIWAR_IWS_MASK 0x0000003F
1458 #define PIWAR_IWS_4K 0x0000000B
1459 #define PIWAR_IWS_8K 0x0000000C
1460 #define PIWAR_IWS_16K 0x0000000D
1461 #define PIWAR_IWS_32K 0x0000000E
1462 #define PIWAR_IWS_64K 0x0000000F
1463 #define PIWAR_IWS_128K 0x00000010
1464 #define PIWAR_IWS_256K 0x00000011
1465 #define PIWAR_IWS_512K 0x00000012
1466 #define PIWAR_IWS_1M 0x00000013
1467 #define PIWAR_IWS_2M 0x00000014
1468 #define PIWAR_IWS_4M 0x00000015
1469 #define PIWAR_IWS_8M 0x00000016
1470 #define PIWAR_IWS_16M 0x00000017
1471 #define PIWAR_IWS_32M 0x00000018
1472 #define PIWAR_IWS_64M 0x00000019
1473 #define PIWAR_IWS_128M 0x0000001A
1474 #define PIWAR_IWS_256M 0x0000001B
1475 #define PIWAR_IWS_512M 0x0000001C
1476 #define PIWAR_IWS_1G 0x0000001D
1477 #define PIWAR_IWS_2G 0x0000001E
1478 } pcictrl83xx_t;
1479
1480 #if defined (CONFIG_MPC8349)
1481 /*
1482 * USB
1483 */
1484 typedef struct usb83xx {
1485 u8 fixme[0x2000];
1486 } usb83xx_t;
1487
1488 /*
1489 * TSEC
1490 */
1491 typedef struct tsec83xx {
1492 u8 fixme[0x1000];
1493 } tsec83xx_t;
1494 #endif
1495
1496 /*
1497 * Security
1498 */
1499 typedef struct security83xx {
1500 u8 fixme[0x10000];
1501 } security83xx_t;
1502
1503 #if defined (CONFIG_MPC8360)
1504 /*
1505 * iram
1506 */
1507 typedef struct iram83xx {
1508 u32 iadd; /* I-RAM address register */
1509 u32 idata; /* I-RAM data register */
1510 u8 res0[0x78];
1511 } iram83xx_t;
1512
1513 /*
1514 * Interrupt Controller
1515 */
1516 typedef struct irq83xx {
1517 u32 cicr; /* QE system interrupt configuration */
1518 u32 civec; /* QE system interrupt vector register */
1519 u32 cripnr; /* QE RISC interrupt pending register */
1520 u32 cipnr; /* QE system interrupt pending register */
1521 u32 cipxcc; /* QE interrupt priority register */
1522 u32 cipycc; /* QE interrupt priority register */
1523 u32 cipwcc; /* QE interrupt priority register */
1524 u32 cipzcc; /* QE interrupt priority register */
1525 u32 cimr; /* QE system interrupt mask register */
1526 u32 crimr; /* QE RISC interrupt mask register */
1527 u32 cicnr; /* QE system interrupt control register */
1528 u8 res0[0x4];
1529 u32 ciprta; /* QE system interrupt priority register for RISC tasks A */
1530 u32 ciprtb; /* QE system interrupt priority register for RISC tasks B */
1531 u8 res1[0x4];
1532 u32 cricr; /* QE system RISC interrupt control */
1533 u8 res2[0x20];
1534 u32 chivec; /* QE high system interrupt vector */
1535 u8 res3[0x1C];
1536 } irq83xx_t;
1537
1538 /*
1539 * Communications Processor
1540 */
1541 typedef struct cp83xx {
1542 u32 cecr; /* QE command register */
1543 u32 ceccr; /* QE controller configuration register */
1544 u32 cecdr; /* QE command data register */
1545 u8 res0[0xA];
1546 u16 ceter; /* QE timer event register */
1547 u8 res1[0x2];
1548 u16 cetmr; /* QE timers mask register */
1549 u32 cetscr; /* QE time-stamp timer control register */
1550 u32 cetsr1; /* QE time-stamp register 1 */
1551 u32 cetsr2; /* QE time-stamp register 2 */
1552 u8 res2[0x8];
1553 u32 cevter; /* QE virtual tasks event register */
1554 u32 cevtmr; /* QE virtual tasks mask register */
1555 u16 cercr; /* QE RAM control register */
1556 u8 res3[0x2];
1557 u8 res4[0x24];
1558 u16 ceexe1; /* QE external request 1 event register */
1559 u8 res5[0x2];
1560 u16 ceexm1; /* QE external request 1 mask register */
1561 u8 res6[0x2];
1562 u16 ceexe2; /* QE external request 2 event register */
1563 u8 res7[0x2];
1564 u16 ceexm2; /* QE external request 2 mask register */
1565 u8 res8[0x2];
1566 u16 ceexe3; /* QE external request 3 event register */
1567 u8 res9[0x2];
1568 u16 ceexm3; /* QE external request 3 mask register */
1569 u8 res10[0x2];
1570 u16 ceexe4; /* QE external request 4 event register */
1571 u8 res11[0x2];
1572 u16 ceexm4; /* QE external request 4 mask register */
1573 u8 res12[0x2];
1574 u8 res13[0x280];
1575 } cp83xx_t;
1576
1577 /*
1578 * QE Multiplexer
1579 */
1580
1581 typedef struct qmx83xx {
1582 u32 cmxgcr; /* CMX general clock route register */
1583 u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
1584 u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
1585 u32 cmxsi1syr; /* CMX SI1 SYNC route register */
1586 u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
1587 u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
1588 u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
1589 u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
1590 u32 cmxupcr; /* CMX UPC clock route register */
1591 u8 res0[0x1C];
1592 } qmx83xx_t;
1593
1594 /*
1595 * QE Timers
1596 */
1597
1598 typedef struct qet83xx {
1599 u8 gtcfr1; /* Timer 1 and Timer 2 global configuration register */
1600 u8 res0[0x3];
1601 u8 gtcfr2; /* Timer 3 and timer 4 global configuration register */
1602 u8 res1[0xB];
1603 u16 gtmdr1; /* Timer 1 mode register */
1604 u16 gtmdr2; /* Timer 2 mode register */
1605 u16 gtrfr1; /* Timer 1 reference register */
1606 u16 gtrfr2; /* Timer 2 reference register */
1607 u16 gtcpr1; /* Timer 1 capture register */
1608 u16 gtcpr2; /* Timer 2 capture register */
1609 u16 gtcnr1; /* Timer 1 counter */
1610 u16 gtcnr2; /* Timer 2 counter */
1611 u16 gtmdr3; /* Timer 3 mode register */
1612 u16 gtmdr4; /* Timer 4 mode register */
1613 u16 gtrfr3; /* Timer 3 reference register */
1614 u16 gtrfr4; /* Timer 4 reference register */
1615 u16 gtcpr3; /* Timer 3 capture register */
1616 u16 gtcpr4; /* Timer 4 capture register */
1617 u16 gtcnr3; /* Timer 3 counter */
1618 u16 gtcnr4; /* Timer 4 counter */
1619 u16 gtevr1; /* Timer 1 event register */
1620 u16 gtevr2; /* Timer 2 event register */
1621 u16 gtevr3; /* Timer 3 event register */
1622 u16 gtevr4; /* Timer 4 event register */
1623 u16 gtps; /* Timer 1 prescale register */
1624 u8 res2[0x46];
1625 } qet83xx_t;
1626
1627 /*
1628 * spi
1629 */
1630
1631 typedef struct spi83xx {
1632 u8 res0[0x20];
1633 u32 spmode; /* SPI mode register */
1634 u8 res1[0x2];
1635 u8 spie; /* SPI event register */
1636 u8 res2[0x1];
1637 u8 res3[0x2];
1638 u8 spim; /* SPI mask register */
1639 u8 res4[0x1];
1640 u8 res5[0x1];
1641 u8 spcom; /* SPI command register */
1642 u8 res6[0x2];
1643 u32 spitd; /* SPI transmit data register (cpu mode) */
1644 u32 spird; /* SPI receive data register (cpu mode) */
1645 u8 res7[0x8];
1646 } spi83xx_t;
1647
1648 /*
1649 * mcc
1650 */
1651
1652 typedef struct mcc83xx {
1653 u32 mcce; /* MCC event register */
1654 u32 mccm; /* MCC mask register */
1655 u32 mccf; /* MCC configuration register */
1656 u32 merl; /* MCC emergency request level register */
1657 u8 res0[0xF0];
1658 } mcc83xx_t;
1659
1660 /*
1661 * brg
1662 */
1663
1664 typedef struct brg83xx {
1665 u32 brgc1; /* BRG1 configuration register */
1666 u32 brgc2; /* BRG2 configuration register */
1667 u32 brgc3; /* BRG3 configuration register */
1668 u32 brgc4; /* BRG4 configuration register */
1669 u32 brgc5; /* BRG5 configuration register */
1670 u32 brgc6; /* BRG6 configuration register */
1671 u32 brgc7; /* BRG7 configuration register */
1672 u32 brgc8; /* BRG8 configuration register */
1673 u32 brgc9; /* BRG9 configuration register */
1674 u32 brgc10; /* BRG10 configuration register */
1675 u32 brgc11; /* BRG11 configuration register */
1676 u32 brgc12; /* BRG12 configuration register */
1677 u32 brgc13; /* BRG13 configuration register */
1678 u32 brgc14; /* BRG14 configuration register */
1679 u32 brgc15; /* BRG15 configuration register */
1680 u32 brgc16; /* BRG16 configuration register */
1681 u8 res0[0x40];
1682 } brg83xx_t;
1683
1684 /*
1685 * USB
1686 */
1687
1688 typedef struct usb83xx {
1689 u8 usmod; /* USB mode register */
1690 u8 usadd; /* USB address register */
1691 u8 uscom; /* USB command register */
1692 u8 res0[0x1];
1693 u16 usep0; /* USB endpoint register 0 */
1694 u16 usep1; /* USB endpoint register 1 */
1695 u16 usep2; /* USB endpoint register 2 */
1696 u16 usep3; /* USB endpoint register 3 */
1697 u8 res1[0x4];
1698 u16 usber; /* USB event register */
1699 u8 res2[0x2];
1700 u16 usbmr; /* USB mask register */
1701 u8 res3[0x1];
1702 u8 usbs; /* USB status register */
1703 u32 ussft; /* USB start of frame timer */
1704 u8 res4[0x24];
1705 } usb83xx_t;
1706
1707 /*
1708 * SI
1709 */
1710
1711 typedef struct si1_83xx {
1712 u16 siamr1; /* SI1 TDMA mode register */
1713 u16 sibmr1; /* SI1 TDMB mode register */
1714 u16 sicmr1; /* SI1 TDMC mode register */
1715 u16 sidmr1; /* SI1 TDMD mode register */
1716 u8 siglmr1_h; /* SI1 global mode register high */
1717 u8 res0[0x1];
1718 u8 sicmdr1_h; /* SI1 command register high */
1719 u8 res2[0x1];
1720 u8 sistr1_h; /* SI1 status register high */
1721 u8 res3[0x1];
1722 u16 sirsr1_h; /* SI1 RAM shadow address register high */
1723 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
1724 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
1725 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
1726 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
1727 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
1728 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
1729 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
1730 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
1731 u8 res4[0x8];
1732 u16 siemr1; /* SI1 TDME mode register 16 bits */
1733 u16 sifmr1; /* SI1 TDMF mode register 16 bits */
1734 u16 sigmr1; /* SI1 TDMG mode register 16 bits */
1735 u16 sihmr1; /* SI1 TDMH mode register 16 bits */
1736 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
1737 u8 res5[0x1];
1738 u8 sicmdr1_l; /* SI1 command register low 8 bits */
1739 u8 res6[0x1];
1740 u8 sistr1_l; /* SI1 status register low 8 bits */
1741 u8 res7[0x1];
1742 u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
1743 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
1744 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
1745 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
1746 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
1747 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
1748 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
1749 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
1750 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
1751 u8 res8[0x8];
1752 u32 siml1; /* SI1 multiframe limit register */
1753 u8 siedm1; /* SI1 extended diagnostic mode register */
1754 u8 res9[0xBB];
1755 } si1_83xx_t;
1756
1757 /*
1758 * SI Routing Tables
1759 */
1760
1761 typedef struct sir83xx {
1762 u8 tx[0x400];
1763 u8 rx[0x400];
1764 u8 res0[0x800];
1765 } sir83xx_t;
1766
1767 /*
1768 * ucc
1769 */
1770
1771 typedef struct uslow {
1772 u32 gumr_l; /* UCCx general mode register (low) */
1773 u32 gumr_h; /* UCCx general mode register (high) */
1774 u16 upsmr; /* UCCx protocol-specific mode register */
1775 u8 res0[0x2];
1776 u16 utodr; /* UCCx transmit on demand register */
1777 u16 udsr; /* UCCx data synchronization register */
1778 u16 ucce; /* UCCx event register */
1779 u8 res1[0x2];
1780 u16 uccm; /* UCCx mask register */
1781 u8 res2[0x1];
1782 u8 uccs; /* UCCx status register */
1783 u8 res3[0x1E8];
1784 } uslow_t;
1785
1786 typedef struct ufast {
1787 u32 gumr; /* UCCx general mode register */
1788 u32 upsmr; /* UCCx protocol-specific mode register */
1789 u16 utodr; /* UCCx transmit on demand register */
1790 u8 res0[0x2];
1791 u16 udsr; /* UCCx data synchronization register */
1792 u8 res1[0x2];
1793 u32 ucce; /* UCCx event register */
1794 u32 uccm; /* UCCx mask register. */
1795 u8 uccs; /* UCCx status register */
1796 u8 res2[0x7];
1797 u32 urfb; /* UCC receive FIFO base */
1798 u16 urfs; /* UCC receive FIFO size */
1799 u8 res3[0x2];
1800 u16 urfet; /* UCC receive FIFO emergency threshold */
1801 u16 urfset; /* UCC receive FIFO special emergency threshold */
1802 u32 utfb; /* UCC transmit FIFO base */
1803 u16 utfs; /* UCC transmit FIFO size */
1804 u8 res4[0x2];
1805 u16 utfet; /* UCC transmit FIFO emergency threshold */
1806 u8 res5[0x2];
1807 u16 utftt; /* UCC transmit FIFO transmit threshold */
1808 u8 res6[0x2];
1809 u16 utpt; /* UCC transmit polling timer */
1810 u32 urtry; /* UCC retry counter register */
1811 u8 res7[0x4C];
1812 u8 guemr; /* UCC general extended mode register */
1813 u8 res8[0x3];
1814 u8 res9[0x6C];
1815 u32 maccfg1; /* Mac configuration register #1 */
1816 u32 maccfg2; /* Mac configuration register #2 */
1817 u16 ipgifg; /* Interframe gap register */
1818 u8 res10[0x2];
1819 u32 hafdup; /* Half-duplex register */
1820 u8 res11[0xC];
1821 u32 emtr; /* Ethernet MAC test register */
1822 u32 miimcfg; /* MII mgmt configuration register */
1823 u32 miimcom; /* MII mgmt command register */
1824 u32 miimadd; /* MII mgmt address register */
1825 u32 miimcon; /* MII mgmt control register */
1826 u32 miistat; /* MII mgmt status register */
1827 u32 miimnd; /* MII mgmt indication register */
1828 u32 ifctl; /* Interface control register */
1829 u32 ifstat; /* Interface status register */
1830 u32 macstnaddr1; /* Station address part 1 register */
1831 u32 macstnaddr2; /* Station address part 2 register */
1832 u8 res12[0x8];
1833 u32 uempr; /* UCC Ethernet MAC parameter register */
1834 u32 utbipa; /* UCC TBI address */
1835 u16 uescr; /* UCC Ethernet statistics control register */
1836 u8 res13[0x26];
1837 u32 tx64; /* Transmit and receive 64-byte frame counter */
1838 u32 tx127; /* Transmit and receive 65- to 127-byte frame counter */
1839 u32 tx255; /* Transmit and receive 128- to 255-byte frame counter */
1840 u32 rx64; /* Receive and receive 64-byte frame counter */
1841 u32 rx127; /* Receive and receive 65- to 127-byte frame counter */
1842 u32 rx255; /* Receive and receive 128- to 255-byte frame counter */
1843 u32 txok; /* Transmit good bytes counter */
1844 u32 txcf; /* Transmit control frame counter */
1845 u32 tmca; /* Transmit multicast control frame counter */
1846 u32 tbca; /* Transmit broadcast packet counter */
1847 u32 rxfok; /* Receive frame OK counter */
1848 u32 rbyt; /* Receive good and bad bytes counter */
1849 u32 rxbok; /* Receive bytes OK counter */
1850 u32 rmca; /* Receive multicast packet counter */
1851 u32 rbca; /* Receive broadcast packet counter */
1852 u32 scar; /* Statistics carry register */
1853 u32 scam; /* Statistics carry mask register */
1854 u8 res14[0x3C];
1855 } ufast_t;
1856
1857 typedef struct ucc83xx {
1858 union {
1859 uslow_t slow;
1860 ufast_t fast;
1861 };
1862 } ucc83xx_t;
1863
1864 /*
1865 * MultiPHY UTOPIA POS Controllers
1866 */
1867
1868 typedef struct upc83xx {
1869 u32 upgcr; /* UTOPIA/POS general configuration register */
1870 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
1871 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
1872 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
1873 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing: */
1874 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
1875 u32 uplpa; /* UTOPIA/POS last PHY address */
1876 u32 uphec; /* ATM HEC register */
1877 u32 upuc; /* UTOPIA/POS UCC configuration */
1878 u32 updc1; /* UTOPIA/POS device 1 configuration */
1879 u32 updc2; /* UTOPIA/POS device 2 configuration */
1880 u32 updc3; /* UTOPIA/POS device 3 configuration */
1881 u32 updc4; /* UTOPIA/POS device 4 configuration */
1882 u32 upstpa; /* UTOPIA/POS STPA threshold */
1883 u8 res0[0xC];
1884 u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
1885 u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
1886 u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
1887 u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
1888 u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
1889 u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
1890 u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
1891 u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
1892 u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
1893 u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
1894 u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
1895 u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
1896 u32 upde1; /* UTOPIA/POS device 1 event */
1897 u32 upde2; /* UTOPIA/POS device 2 event */
1898 u32 upde3; /* UTOPIA/POS device 3 event */
1899 u32 upde4; /* UTOPIA/POS device 4 event */
1900 u16 uprp1;
1901 u16 uprp2;
1902 u16 uprp3;
1903 u16 uprp4;
1904 u8 res1[0x8];
1905 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
1906 u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
1907 u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
1908 u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
1909 u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
1910 u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
1911 u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
1912 u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
1913 u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
1914 u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
1915 u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
1916 u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
1917 u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
1918 u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
1919 u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
1920 u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
1921 u32 uper1; /* Device 1 port enable register */
1922 u32 uper2; /* Device 2 port enable register */
1923 u32 uper3; /* Device 3 port enable register */
1924 u32 uper4; /* Device 4 port enable register */
1925 u8 res2[0x150];
1926 } upc83xx_t;
1927
1928 /*
1929 * SDMA
1930 */
1931
1932 typedef struct sdma83xx {
1933 u32 sdsr; /* Serial DMA status register */
1934 u32 sdmr; /* Serial DMA mode register */
1935 u32 sdtr1; /* SDMA system bus threshold register */
1936 u32 sdtr2; /* SDMA secondary bus threshold register */
1937 u32 sdhy1; /* SDMA system bus hysteresis register */
1938 u32 sdhy2; /* SDMA secondary bus hysteresis register */
1939 u32 sdta1; /* SDMA system bus address register */
1940 u32 sdta2; /* SDMA secondary bus address register */
1941 u32 sdtm1; /* SDMA system bus MSNUM register */
1942 u32 sdtm2; /* SDMA secondary bus MSNUM register */
1943 u8 res0[0x10];
1944 u32 sdaqr; /* SDMA address bus qualify register */
1945 u32 sdaqmr; /* SDMA address bus qualify mask register */
1946 u8 res1[0x4];
1947 u32 sdwbcr; /* SDMA CAM entries base register */
1948 u8 res2[0x38];
1949 } sdma83xx_t;
1950
1951 /*
1952 * Debug Space
1953 */
1954
1955 typedef struct dbg83xx {
1956 u32 bpdcr; /* Breakpoint debug command register */
1957 u32 bpdsr; /* Breakpoint debug status register */
1958 u32 bpdmr; /* Breakpoint debug mask register */
1959 u32 bprmrr0; /* Breakpoint request mode risc register 0 */
1960 u32 bprmrr1; /* Breakpoint request mode risc register 1 */
1961 u8 res0[0x8];
1962 u32 bprmtr0; /* Breakpoint request mode trb register 0 */
1963 u32 bprmtr1; /* Breakpoint request mode trb register 1 */
1964 u8 res1[0x8];
1965 u32 bprmir; /* Breakpoint request mode immediate register */
1966 u32 bprmsr; /* Breakpoint request mode serial register */
1967 u32 bpemr; /* Breakpoint exit mode register */
1968 u8 res2[0x48];
1969 } dbg83xx_t;
1970
1971 /*
1972 * RISC Special Registers (Trap and Breakpoint)
1973 */
1974
1975 typedef struct rsp83xx {
1976 u8 fixme[0x100];
1977 } rsp83xx_t;
1978 #endif
1979
1980 typedef struct immap {
1981 sysconf83xx_t sysconf; /* System configuration */
1982 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
1983 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
1984 rtclk83xx_t pit; /* Periodic Interval Timer */
1985 gtm83xx_t gtm[2]; /* Global Timers Module */
1986 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
1987 arbiter83xx_t arbiter; /* System Arbiter Registers */
1988 reset83xx_t reset; /* Reset Module */
1989 clk83xx_t clk; /* System Clock Module */
1990 pmc83xx_t pmc; /* Power Management Control Module */
1991 #if defined (CONFIG_MPC8349)
1992 gpio83xx_t pgio[2]; /* general purpose I/O module */
1993 #elif defined (CONFIG_MPC8360)
1994 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
1995 #endif
1996 u8 res0[0x200];
1997 #if defined (CONFIG_MPC8360)
1998 u8 DLL_LBDDR[0x100];
1999 #endif
2000 u8 DDL_DDR[0x100];
2001 u8 DDL_LBIU[0x100];
2002 #if defined (CONFIG_MPC8349)
2003 u8 res1[0xE00];
2004 #elif defined (CONFIG_MPC8360)
2005 u8 res1[0x200];
2006 gpio83xx_t gpio; /* General purpose I/O module */
2007 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
2008 #endif
2009 ddr83xx_t ddr; /* DDR Memory Controller Memory */
2010 fsl_i2c_t i2c[2]; /* I2C Controllers */
2011 u8 res2[0x1300];
2012 duart83xx_t duart[2]; /* DUART */
2013 #if defined (CONFIG_MPC8349)
2014 u8 res3[0x900];
2015 lbus83xx_t lbus; /* Local Bus Controller Registers */
2016 u8 res4[0x1000];
2017 spi83xx_t spi; /* Serial Peripheral Interface */
2018 u8 res5[0xF00];
2019 #elif defined (CONFIG_MPC8360)
2020 u8 res3[0x900];
2021 lbus83xx_t lbus; /* Local Bus Controller */
2022 u8 res4[0x2000];
2023 #endif
2024 dma83xx_t dma; /* DMA */
2025 #if defined (CONFIG_MPC8349)
2026 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
2027 ios83xx_t ios; /* Sequencer */
2028 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
2029 u8 res6[0x19900];
2030 usb83xx_t usb;
2031 tsec83xx_t tsec[2];
2032 u8 res7[0xA000];
2033 security83xx_t security;
2034 #elif defined (CONFIG_MPC8360)
2035 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
2036 u8 res_5[128];
2037 ios83xx_t ios; /* Sequencer (IOS) */
2038 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
2039 u8 res6[0x4A00];
2040 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
2041 u8 res7[0x22000];
2042 security83xx_t security;
2043 u8 res8[0xC0000];
2044 iram83xx_t iram; /* IRAM */
2045 irq83xx_t irq; /* Interrupt Controller */
2046 cp83xx_t cp; /* Communications Processor */
2047 qmx83xx_t qmx; /* QE Multiplexer */
2048 qet83xx_t qet; /* QE Timers */
2049 spi83xx_t spi[0x2]; /* spi */
2050 mcc83xx_t mcc; /* mcc */
2051 brg83xx_t brg; /* brg */
2052 usb83xx_t usb; /* USB */
2053 si1_83xx_t si1; /* SI */
2054 u8 res9[0x800];
2055 sir83xx_t sir; /* SI Routing Tables */
2056 ucc83xx_t ucc1; /* ucc1 */
2057 ucc83xx_t ucc3; /* ucc3 */
2058 ucc83xx_t ucc5; /* ucc5 */
2059 ucc83xx_t ucc7; /* ucc7 */
2060 u8 res10[0x600];
2061 upc83xx_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
2062 ucc83xx_t ucc2; /* ucc2 */
2063 ucc83xx_t ucc4; /* ucc4 */
2064 ucc83xx_t ucc6; /* ucc6 */
2065 ucc83xx_t ucc8; /* ucc8 */
2066 u8 res11[0x600];
2067 upc83xx_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
2068 sdma83xx_t sdma; /* SDMA */
2069 dbg83xx_t dbg; /* Debug Space */
2070 rsp83xx_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint) */
2071 u8 res12[0x300];
2072 u8 res13[0x3A00];
2073 u8 res14[0x8000]; /* 0x108000 - 0x110000 */
2074 u8 res15[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
2075 u8 res16[0x24000]; /* 0x11C000 - 0x140000 */
2076 u8 res17[0xC0000]; /* 0x140000 - 0x200000 */
2077 #endif
2078 } immap_t;
2079
2080 #endif /* __IMMAP_83xx__ */
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