include/asm-ppc/immap_83xx.h

   1 /*
   2  * MPC8349 Internal Memory Map
   3  * Copyright (c) 2004 Freescale Semiconductor.
   4  * Eran Liberty (liberty@freescale.com)
   5  *
   6  * based on:
   7  * - MPC8260 Internal Memory Map
   8  *   Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
   9  * - MPC85xx Internal Memory Map
  10  *   Copyright(c) 2002,2003 Motorola Inc.
  11  *   Xianghua Xiao (x.xiao@motorola.com)
  12  */
  13 #ifndef __IMMAP_8349__
  14 #define __IMMAP_8349__
  15
  16 #include <asm/types.h>
  17 #include <asm/i2c.h>
  18
  19 /*
  20  * Local Access Window.
  21  */
  22 typedef struct law8349 {
  23         u32 bar; /* LBIU local access window base address register */
  24 /* Identifies the 20 most-significant address bits of the base of local
  25  * access window n. The specified base address should be aligned to the
  26  * window size, as defined by LBLAWARn[SIZE].
  27  */
  28 #define LAWBAR_BAR         0xFFFFF000
  29 #define LAWBAR_RES           ~(LAWBAR_BAR)
  30         u32 ar; /* LBIU local access window attribute register */
  31 /*
  32  * This Macro were moved into mmu.h
  33  */
  34 #if 0
  35 /* 0 The local bus local access window n is disabled. 1 The local bus
  36  * local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields
  37  * combine to identify an address range for this window.
  38  */
  39 #define LAWAR_EN           0x80000000
  40 /* Identifies the size of the window from the starting address. Window
  41  * size is 2^(SIZE+1) bytes. 000000\96001010Reserved. Window is
  42  * undefined.
  43  */
  44 #define LAWAR_SIZE         0x0000003F
  45 #define LAWAR_SIZE_4K   0x0000000B
  46 #define LAWAR_SIZE_8K   0x0000000C
  47 #define LAWAR_SIZE_16K  0x0000000D
  48 #define LAWAR_SIZE_32K  0x0000000E
  49 #define LAWAR_SIZE_64K  0x0000000F
  50 #define LAWAR_SIZE_128K 0x00000010
  51 #define LAWAR_SIZE_256K 0x00000011
  52 #define LAWAR_SIZE_512K 0x00000012
  53 #define LAWAR_SIZE_1M   0x00000013
  54 #define LAWAR_SIZE_2M   0x00000014
  55 #define LAWAR_SIZE_4M   0x00000015
  56 #define LAWAR_SIZE_8M   0x00000016
  57 #define LAWAR_SIZE_16M  0x00000017
  58 #define LAWAR_SIZE_32M  0x00000018
  59 #define LAWAR_SIZE_64M  0x00000019
  60 #define LAWAR_SIZE_128M 0x0000001A
  61 #define LAWAR_SIZE_256M 0x0000001B
  62 #define LAWAR_SIZE_512M 0x0000001C
  63 #define LAWAR_SIZE_1G   0x0000001D
  64 #define LAWAR_SIZE_2G   0x0000001E
  65 #define LAWAR_RES          ~(LAWAR_EN|LAWAR_SIZE)
  66 #endif
  67
  68 } law8349_t;
  69
  70 /*
  71  * System configuration registers.
  72  */
  73 typedef struct sysconf8349 {
  74         u32 immrbar; /* Internal memory map base address register */
  75         u8 res0[0x04];
  76         u32 altcbar; /* Alternate configuration base address register */
  77 /* Identifies the12 most significant address bits of an alternate base
  78  * address used for boot sequencer configuration accesses.
  79  */
  80 #define ALTCBAR_BASE_ADDR     0xFFF00000
  81 #define ALTCBAR_RES           ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
  82         u8 res1[0x14];
  83         law8349_t lblaw[4]; /* LBIU local access window */
  84         u8 res2[0x20];
  85         law8349_t pcilaw[2]; /* PCI local access window */
  86         u8 res3[0x30];
  87         law8349_t ddrlaw[2]; /* DDR local access window */
  88         u8 res4[0x50];
  89         u32 sgprl; /* System General Purpose Register Low */
  90         u32 sgprh; /* System General Purpose Register High */
  91         u32 spridr; /* System Part and Revision ID Register */
  92 #define SPRIDR_PARTID         0xFFFF0000 /* Part Identification. */
  93 #define SPRIDR_REVID          0x0000FFFF /* Revision Identification. */
  94         u8 res5[0x04];
  95         u32 spcr; /* System Priority Configuration Register */
  96 #define SPCR_PCIHPE   0x10000000 /* PCI Highest Priority Enable. */
  97 #define SPCR_PCIPR    0x03000000 /* PCI bridge system bus request priority. */
  98 #define SPCR_TBEN     0x00400000 /* E300 PowerPC core time base unit enable. */
  99 #define SPCR_COREPR   0x00300000 /* E300 PowerPC Core system bus request priority. */
 100 #define SPCR_TSEC1DP  0x00003000 /* TSEC1 data priority. */
 101 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
 102 #define SPCR_TSEC1EP  0x00000300 /* TSEC1 emergency priority. */
 103 #define SPCR_TSEC2DP  0x00000030 /* TSEC2 data priority. */
 104 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
 105 #define SPCR_TSEC2EP  0x00000003 /* TSEC2 emergency priority. */
 106 #define SPCR_RES      ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
 107                         | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
 108                         | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
 109         u32 sicrl; /* System General Purpose Register Low */
 110 #define SICRL_LDP_A   0x80000000
 111 #define SICRL_USB0    0x40000000
 112 #define SICRL_USB1    0x20000000
 113 #define SICRL_UART    0x0C000000
 114 #define SICRL_GPIO1_A 0x02000000
 115 #define SICRL_GPIO1_B 0x01000000
 116 #define SICRL_GPIO1_C 0x00800000
 117 #define SICRL_GPIO1_D 0x00400000
 118 #define SICRL_GPIO1_E 0x00200000
 119 #define SICRL_GPIO1_F 0x00180000
 120 #define SICRL_GPIO1_G 0x00040000
 121 #define SICRL_GPIO1_H 0x00020000
 122 #define SICRL_GPIO1_I 0x00010000
 123 #define SICRL_GPIO1_J 0x00008000
 124 #define SICRL_GPIO1_K 0x00004000
 125 #define SICRL_GPIO1_L 0x00003000
 126 #define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
 127                         | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
 128                         | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
 129                         | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
 130                         | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
 131         u32 sicrh; /* System General Purpose Register High */
 132 #define SICRH_DDR     0x80000000
 133 #define SICRH_TSEC1_A 0x10000000
 134 #define SICRH_TSEC1_B 0x08000000
 135 #define SICRH_TSEC1_C 0x04000000
 136 #define SICRH_TSEC1_D 0x02000000
 137 #define SICRH_TSEC1_E 0x01000000
 138 #define SICRH_TSEC1_F 0x00800000
 139 #define SICRH_TSEC2_A 0x00400000
 140 #define SICRH_TSEC2_B 0x00200000
 141 #define SICRH_TSEC2_C 0x00100000
 142 #define SICRH_TSEC2_D 0x00080000
 143 #define SICRH_TSEC2_E 0x00040000
 144 #define SICRH_TSEC2_F 0x00020000
 145 #define SICRH_TSEC2_G 0x00010000
 146 #define SICRH_TSEC2_H 0x00008000
 147 #define SICRH_GPIO2_A 0x00004000
 148 #define SICRH_GPIO2_B 0x00002000
 149 #define SICRH_GPIO2_C 0x00001000
 150 #define SICRH_GPIO2_D 0x00000800
 151 #define SICRH_GPIO2_E 0x00000400
 152 #define SICRH_GPIO2_F 0x00000200
 153 #define SICRH_GPIO2_G 0x00000180
 154 #define SICRH_GPIO2_H 0x00000060
 155 #define SICRH_TSOBI1  0x00000002
 156 #define SICRH_TSOBI2  0x00000001
 157 #define SICRh_RES     ~(  SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
 158                         | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
 159                         | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
 160                         | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
 161                         | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
 162                         | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
 163                         | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
 164                         | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
 165                         | SICRH_TSOBI2)
 166         u8 res6[0xE4];
 167 } sysconf8349_t;
 168
 169 /*
 170  * Watch Dog Timer (WDT) Registers
 171  */
 172 typedef struct wdt8349 {
 173         u8 res0[4];
 174         u32 swcrr; /* System watchdog control register */
 175         u32 swcnr; /* System watchdog count register */
 176 #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
 177 #define SWCNR_RES  ~(SWCNR_SWCN)
 178         u8 res1[2];
 179         u16 swsrr; /* System watchdog service register */
 180         u8 res2[0xF0];
 181 } wdt8349_t;
 182
 183 /*
 184  * RTC/PIT Module Registers
 185  */
 186 typedef struct rtclk8349 {
 187         u32 cnr; /* control register */
 188 #define CNR_CLEN 0x00000080 /* Clock Enable Control Bit  */
 189 #define CNR_CLIN 0x00000040 /* Input Clock Control Bit  */
 190 #define CNR_AIM  0x00000002 /* Alarm Interrupt Mask Bit  */
 191 #define CNR_SIM  0x00000001 /* Second Interrupt Mask Bit  */
 192 #define CNR_RES  ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
 193         u32 ldr; /* load register */
 194         u32 psr; /* prescale register */
 195         u32 ctr; /* register */
 196         u32 evr; /* event register */
 197 #define RTEVR_SIF  0x00000001 /* Second Interrupt Flag Bit  */
 198 #define RTEVR_AIF  0x00000002 /* Alarm Interrupt Flag Bit  */
 199 #define RTEVR_RES  ~(EVR_SIF | EVR_AIF)
 200         u32 alr; /* alarm register */
 201         u8 res0[0xE8];
 202 } rtclk8349_t;
 203
 204 /*
 205  * Global timper module
 206  */
 207
 208 typedef struct gtm8349 {
 209         u8    cfr1; /* Timer1/2 Configuration  */
 210 #define CFR1_PCAS 0x80 /* Pair Cascade mode  */
 211 #define CFR1_BCM  0x40  /* Backward compatible mode  */
 212 #define CFR1_STP2 0x20 /* Stop timer  */
 213 #define CFR1_RST2 0x10 /* Reset timer  */
 214 #define CFR1_GM2  0x08 /* Gate mode for pin 2  */
 215 #define CFR1_GM1  0x04 /* Gate mode for pin 1  */
 216 #define CFR1_STP1 0x02 /* Stop timer  */
 217 #define CFR1_RST1 0x01 /* Reset timer  */
 218         u8    res0[3];
 219         u8    cfr2; /* Timer3/4 Configuration  */
 220 #define CFR2_PCAS 0x80 /* Pair Cascade mode  */
 221 #define CFR2_SCAS 0x40 /* Super Cascade mode  */
 222 #define CFR2_STP4 0x20 /* Stop timer  */
 223 #define CFR2_RST4 0x10 /* Reset timer  */
 224 #define CFR2_GM4  0x08 /* Gate mode for pin 4  */
 225 #define CFR2_GM3  0x04 /* Gate mode for pin 3  */
 226 #define CFR2_STP3 0x02 /* Stop timer  */
 227 #define CFR2_RST3 0x01 /* Reset timer  */
 228         u8    res1[10];
 229         u16   mdr1; /* Timer1 Mode Register  */
 230 #define MDR_SPS  0xff00 /* Secondary Prescaler value  */
 231 #define MDR_CE   0x00c0 /* Capture edge and enable interrupt  */
 232 #define MDR_OM   0x0020 /* Output mode  */
 233 #define MDR_ORI  0x0010 /* Output reference interrupt enable  */
 234 #define MDR_FRR  0x0008 /* Free run/restart  */
 235 #define MDR_ICLK 0x0006 /* Input clock source for the timer  */
 236 #define MDR_GE   0x0001 /* Gate enable  */
 237         u16   mdr2; /* Timer2 Mode Register  */
 238         u16   rfr1; /* Timer1 Reference Register  */
 239         u16   rfr2; /* Timer2 Reference Register  */
 240         u16   cpr1; /* Timer1 Capture Register  */
 241         u16   cpr2; /* Timer2 Capture Register  */
 242         u16   cnr1; /* Timer1 Counter Register  */
 243         u16   cnr2; /* Timer2 Counter Register  */
 244         u16   mdr3; /* Timer3 Mode Register  */
 245         u16   mdr4; /* Timer4 Mode Register  */
 246         u16   rfr3; /* Timer3 Reference Register  */
 247         u16   rfr4; /* Timer4 Reference Register  */
 248         u16   cpr3; /* Timer3 Capture Register  */
 249         u16   cpr4; /* Timer4 Capture Register  */
 250         u16   cnr3; /* Timer3 Counter Register  */
 251         u16   cnr4; /* Timer4 Counter Register  */
 252         u16   evr1; /* Timer1 Event Register  */
 253         u16   evr2; /* Timer2 Event Register  */
 254         u16   evr3; /* Timer3 Event Register  */
 255         u16   evr4; /* Timer4 Event Register  */
 256 #define GTEVR_REF 0x0002 /* Output reference event  */
 257 #define GTEVR_CAP 0x0001 /* Counter Capture event   */
 258 #define GTEVR_RES ~(EVR_CAP|EVR_REF)
 259         u16   psr1; /* Timer1 Prescaler Register  */
 260         u16   psr2; /* Timer2 Prescaler Register  */
 261         u16   psr3; /* Timer3 Prescaler Register  */
 262         u16   psr4; /* Timer4 Prescaler Register  */
 263         u8    res[0xC0];
 264 } gtm8349_t;
 265
 266 /*
 267  * Integrated Programmable Interrupt Controller
 268  */
 269 typedef struct ipic8349 {
 270         u32    sicfr; /*  System Global Interrupt Configuration Register (SICFR)  */
 271 #define SICFR_HPI  0x7f000000 /*  Highest Priority Interrupt  */
 272 #define SICFR_MPSB 0x00400000 /*  Mixed interrupts Priority Scheme for group B  */
 273 #define SICFR_MPSA 0x00200000 /*  Mixed interrupts Priority Scheme for group A  */
 274 #define SICFR_IPSD 0x00080000 /*  Internal interrupts Priority Scheme for group D  */
 275 #define SICFR_IPSA 0x00010000 /*  Internal interrupts Priority Scheme for group A  */
 276 #define SICFR_HPIT 0x00000300 /*  HPI priority position IPIC output interrupt Type  */
 277 #define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
 278         u32    sivcr; /*  System Global Interrupt Vector Register (SIVCR)  */
 279 #define SICVR_IVECX 0xfc000000 /*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
 280 #define SICVR_IVEC  0x0000007f /*  Interrupt vector  */
 281 #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
 282         u32    sipnr_h; /*  System Internal Interrupt Pending Register - High (SIPNR_H)  */
 283 #define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt  */
 284 #define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt  */
 285 #define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
 286 #define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt  */
 287 #define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt  */
 288 #define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
 289 #define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
 290 #define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt  */
 291 #define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
 292 #define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
 293 #define SIIH_SEC     0x00000020 /*  SEC interrupt  */
 294 #define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
 295 #define SIIH_I2C2    0x00000002 /*  I2C1 interrupt  */
 296 #define SIIH_SPI     0x00000001 /*  SPI interrupt  */
 297 #define SIIH_RES        ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
 298                         | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
 299                         | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
 300                         | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
 301                         | SIIH_I2C2 | SIIH_SPI)
 302         u32    sipnr_l; /*  System Internal Interrupt Pending Register - Low (SIPNR_L)  */
 303 #define SIIL_RTCS  0x80000000 /*  RTC SECOND interrupt  */
 304 #define SIIL_PIT   0x40000000 /*  PIT interrupt  */
 305 #define SIIL_PCI1  0x20000000 /*  PCI1 interrupt  */
 306 #define SIIL_PCI2  0x10000000 /*  PCI2 interrupt  */
 307 #define SIIL_RTCA  0x08000000 /*  RTC ALARM interrupt  */
 308 #define SIIL_MU    0x04000000 /*  Message Unit interrupt  */
 309 #define SIIL_SBA   0x02000000 /*  System Bus Arbiter interrupt  */
 310 #define SIIL_DMA   0x01000000 /*  DMA interrupt  */
 311 #define SIIL_GTM4  0x00800000 /*  GTM4 interrupt  */
 312 #define SIIL_GTM8  0x00400000 /*  GTM8 interrupt  */
 313 #define SIIL_GPIO1 0x00200000 /*  GPIO1 interrupt  */
 314 #define SIIL_GPIO2 0x00100000 /*  GPIO2 interrupt  */
 315 #define SIIL_DDR   0x00080000 /*  DDR interrupt  */
 316 #define SIIL_LBC   0x00040000 /*  LBC interrupt  */
 317 #define SIIL_GTM2  0x00020000 /*  GTM2 interrupt  */
 318 #define SIIL_GTM6  0x00010000 /*  GTM6 interrupt  */
 319 #define SIIL_PMC   0x00008000 /*  PMC interrupt  */
 320 #define SIIL_GTM3  0x00000800 /*  GTM3 interrupt  */
 321 #define SIIL_GTM7  0x00000400 /*  GTM7 interrupt  */
 322 #define SIIL_GTM1  0x00000020 /*  GTM1 interrupt  */
 323 #define SIIL_GTM5  0x00000010 /*  GTM5 interrupt  */
 324 #define SIIL_DPTC  0x00000001 /*  DPTC interrupt (!!! Invisible for user !!!)  */
 325 #define SIIL_RES        ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
 326                         | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
 327                         | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
 328                         | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
 329                         | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
 330                         | SIIL_GTM5 |SIIL_DPTC )
 331         u32    siprr_a; /*  System Internal Interrupt Group A Priority Register (PRR)  */
 332         u8     res0[8];
 333         u32    siprr_d; /*  System Internal Interrupt Group D Priority Register (PRR)  */
 334         u32    simsr_h; /*  System Internal Interrupt Mask Register - High (SIIH)  */
 335         u32    simsr_l; /*  System Internal Interrupt Mask Register - Low (SIIL)  */
 336         u8     res1[4];
 337         u32    sepnr;   /*  System External Interrupt Pending Register (SEI)  */
 338         u32    smprr_a; /*  System Mixed Interrupt Group A Priority Register (PRR)  */
 339         u32    smprr_b; /*  System Mixed Interrupt Group B Priority Register (PRR)  */
 340 #define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
 341 #define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
 342 #define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
 343 #define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
 344 #define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
 345 #define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
 346 #define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
 347 #define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
 348 #define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
 349         u32    semsr; /*  System External Interrupt Mask Register (SEI)  */
 350 #define SEI_IRQ0  0x80000000 /*  IRQ0 external interrupt  */
 351 #define SEI_IRQ1  0x40000000 /*  IRQ1 external interrupt  */
 352 #define SEI_IRQ2  0x20000000 /*  IRQ2 external interrupt  */
 353 #define SEI_IRQ3  0x10000000 /*  IRQ3 external interrupt  */
 354 #define SEI_IRQ4  0x08000000 /*  IRQ4 external interrupt  */
 355 #define SEI_IRQ5  0x04000000 /*  IRQ5 external interrupt  */
 356 #define SEI_IRQ6  0x02000000 /*  IRQ6 external interrupt  */
 357 #define SEI_IRQ7  0x01000000 /*  IRQ7 external interrupt  */
 358 #define SEI_SIRQ0 0x00008000 /*  SIRQ0 external interrupt  */
 359 #define SEI_RES         ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
 360                         | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
 361                         | SEI_SIRQ0)
 362         u32    secnr; /*  System External Interrupt Control Register (SECNR) */
 363 #define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type  */
 364 #define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type  */
 365 #define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type  */
 366 #define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type  */
 367 #define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
 368 #define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
 369 #define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
 370 #define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
 371 #define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
 372 #define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
 373 #define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
 374 #define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
 375 #define SECNR_RES       ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
 376                         | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
 377                         | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
 378                         | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
 379         u32   sersr; /*  System Error Status Register (SERR)  */
 380         u32   sermr; /*  System Error Mask Register (SERR)  */
 381 #define SERR_IRQ0 0x80000000 /*  IRQ0 MCP request  */
 382 #define SERR_WDT  0x40000000 /*  WDT MCP request  */
 383 #define SERR_SBA  0x20000000 /*  SBA MCP request  */
 384 #define SERR_DDR  0x10000000 /*  DDR MCP request  */
 385 #define SERR_LBC  0x08000000 /*  LBC MCP request  */
 386 #define SERR_PCI1 0x04000000 /*  PCI1 MCP request  */
 387 #define SERR_PCI2 0x02000000 /*  PCI2 MCP request  */
 388 #define SERR_MU   0x01000000 /*  MU MCP request  */
 389 #define SERR_RNC  0x00010000 /*  MU MCP request (!!! Non-visible for users !!!)  */
 390 #define SERR_RES        ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
 391                         |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
 392                         |SERR_RNC )
 393         u32    sercr; /*  System Error Control Register  (SERCR)  */
 394 #define SERCR_MCPR 0x00000001 /*  MCP Route  */
 395 #define SERCR_RES ~(SERCR_MCPR)
 396         u8    res2[4];
 397         u32   sifcr_h; /*  System Internal Interrupt Force Register - High (SIIH)  */
 398         u32   sifcr_l; /*  System Internal Interrupt Force Register - Low (SIIL)  */
 399         u32   sefcr;   /*  System External Interrupt Force Register (SEI)  */
 400         u32   serfr;   /*  System Error Force Register (SERR)  */
 401         u8    res3[0xA0];
 402 } ipic8349_t;
 403
 404 /*
 405  * System Arbiter Registers
 406  */
 407 typedef struct arbiter8349 {
 408         u32 acr; /* Arbiter Configuration Register */
 409 #define ACR_COREDIS    0x10000000 /* Core disable. */
 410 #define ACR_PIPE_DEP   0x00070000 /* Pipeline depth (number of outstanding transactions). */
 411 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
 412 #define ACR_RPTCNT     0x00000700 /* Repeat count. */
 413 #define ACR_APARK      0x00000030 /* Address parking. */
 414 #define ACR_PARKM          0x0000000F /* Parking master. */
 415 #define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
 416         u32 atr; /* Arbiter Timers Register */
 417 #define ATR_DTO 0x00FF0000 /* Data time out. */
 418 #define ATR_ATO 0x000000FF /* Address time out. */
 419 #define ATR_RES ~(ATR_DTO|ATR_ATO)
 420         u8 res[4];
 421         u32 aer; /* Arbiter Event Register (AE)*/
 422         u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
 423         u32 amr; /* Arbiter Mask Register (AE) */
 424         u32 aeatr; /* Arbiter Event Attributes Register */
 425 #define AEATR_EVENT   0x07000000 /* Event type. */
 426 #define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
 427 #define AEATR_TBST    0x00000800 /* Transfer burst. */
 428 #define AEATR_TSIZE   0x00000700 /* Transfer Size. */
 429 #define AEATR_TTYPE       0x0000001F /* Transfer Type. */
 430 #define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
 431         u32 aeadr; /* Arbiter Event Address Register */
 432         u32 aerr; /* Arbiter Event Response Register (AE)*/
 433 #define AE_ETEA 0x00000020 /* Transfer error. */
 434 #define AE_RES_ 0x00000010 /* Reserved transfer type. */
 435 #define AE_ECW  0x00000008 /* External control word transfer type. */
 436 #define AE_AO   0x00000004 /* Address Only transfer type. */
 437 #define AE_DTO  0x00000002 /* Data time out. */
 438 #define AE_ATO  0x00000001 /* Address time out. */
 439 #define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
 440         u8 res1[0xDC];
 441 } arbiter8349_t;
 442
 443 /*
 444  * Reset Module
 445  */
 446 typedef struct reset8349 {
 447         u32    rcwl; /* RCWL Register  */
 448 #define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
 449 #define RCWL_LBIUCM_SHIFT    31
 450 #define RCWL_DDRCM   0x40000000 /* DDRCM  */
 451 #define RCWL_DDRCM_SHIFT     30
 452 #define RCWL_SVCOD   0x30000000 /* SVCOD  */
 453 #define RCWL_SPMF    0x0f000000 /* SPMF  */
 454 #define RCWL_SPMF_SHIFT      24
 455 #define RCWL_COREPLL 0x007F0000 /* COREPLL  */
 456 #define RCWL_COREPLL_SHIFT   16
 457 #define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
 458 #define RCWL_CEPDF   0x00000020 /* CEPDF  */
 459 #define RCWL_CEPMF   0x0000001F /* CEPMF  */
 460 #define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
 461         u32    rcwh; /* RCHL Register  */
 462 #define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 463 #define RCWH_PCIHOST_SHIFT   31
 464 #define RCWH_PCI64   0x40000000 /* PCI64  */
 465 #define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
 466 #define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
 467 #define RCWH_COREDIS 0x08000000 /* COREDIS  */
 468 #define RCWH_BMS     0x04000000 /* BMS  */
 469 #define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
 470 #define RCWH_SWEN    0x00800000 /* SWEN  */
 471 #define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
 472 #define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
 473 #define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
 474 #define RCWH_TPR     0x00000100 /* TPR  */
 475 #define RCWH_TLE     0x00000008 /* TLE  */
 476 #define RCWH_LALE    0x00000004 /* LALE  */
 477 #define RCWH_RES        ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
 478                         | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
 479                         | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
 480                         | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
 481                         | RCWH_TLE | RCWH_LALE)
 482         u8     res0[8];
 483         u32    rsr; /* Reset status Register  */
 484 #define RSR_RSTSRC 0xE0000000 /* Reset source  */
 485 #define RSR_RSTSRC_SHIFT   29
 486 #define RSR_BSF    0x00010000 /* Boot seq. fail  */
 487 #define RSR_BSF_SHIFT      16
 488 #define RSR_SWSR   0x00002000 /* software soft reset  */
 489 #define RSR_SWSR_SHIFT     13
 490 #define RSR_SWHR   0x00001000 /* software hard reset  */
 491 #define RSR_SWHR_SHIFT     12
 492 #define RSR_JHRS   0x00000200 /* jtag hreset  */
 493 #define RSR_JHRS_SHIFT      9
 494 #define RSR_JSRS   0x00000100 /* jtag sreset status  */
 495 #define RSR_JSRS_SHIFT      8
 496 #define RSR_CSHR   0x00000010 /* checkstop reset status  */
 497 #define RSR_CSHR_SHIFT      4
 498 #define RSR_SWRS   0x00000008 /* software watchdog reset status  */
 499 #define RSR_SWRS_SHIFT      3
 500 #define RSR_BMRS   0x00000004 /* bus monitop reset status  */
 501 #define RSR_BMRS_SHIFT      2
 502 #define RSR_SRS    0x00000002 /* soft reset status  */
 503 #define RSR_SRS_SHIFT       1
 504 #define RSR_HRS    0x00000001 /* hard reset status  */
 505 #define RSR_HRS_SHIFT       0
 506 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
 507         u32    rmr; /* Reset mode Register  */
 508 #define RMR_CSRE   0x00000001 /* checkstop reset enable  */
 509 #define RMR_CSRE_SHIFT      0
 510 #define RMR_RES ~(RMR_CSRE)
 511         u32    rpr; /* Reset protection Register  */
 512         u32    rcr; /* Reset Control Register  */
 513 #define RCR_SWHR 0x00000002 /* software hard reset  */
 514 #define RCR_SWSR 0x00000001 /* software soft reset  */
 515 #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
 516         u32    rcer; /* Reset Control Enable Register  */
 517 #define RCER_CRE 0x00000001 /* software hard reset  */
 518 #define RCER_RES ~(RCER_CRE)
 519         u8     res1[0xDC];
 520 } reset8349_t;
 521
 522 typedef struct clk8349 {
 523         u32    spmr; /* system PLL mode Register  */
 524 #define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
 525 #define SPMR_DDRCM   0x40000000 /* DDRCM  */
 526 #define SPMR_SVCOD   0x30000000 /* SVCOD  */
 527 #define SPMR_SPMF    0x0F000000 /* SPMF  */
 528 #define SPMR_CKID    0x00800000 /* CKID  */
 529 #define SPMR_CKID_SHIFT 23
 530 #define SPMR_COREPLL 0x007F0000 /* COREPLL  */
 531 #define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
 532 #define SPMR_CEPDF   0x00000020 /* CEPDF  */
 533 #define SPMR_CEPMF   0x0000001F /* CEPMF  */
 534 #define SPMR_RES        ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
 535                         | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
 536                         | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
 537         u32    occr; /* output clock control Register  */
 538 #define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
 539 #define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
 540 #define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
 541 #define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
 542 #define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
 543 #define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
 544 #define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
 545 #define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
 546 #define OCCR_PCICD0  0x00800000 /* PCICD0  */
 547 #define OCCR_PCICD1  0x00400000 /* PCICD1  */
 548 #define OCCR_PCICD2  0x00200000 /* PCICD2  */
 549 #define OCCR_PCICD3  0x00100000 /* PCICD3  */
 550 #define OCCR_PCICD4  0x00080000 /* PCICD4  */
 551 #define OCCR_PCICD5  0x00040000 /* PCICD5  */
 552 #define OCCR_PCICD6  0x00020000 /* PCICD6  */
 553 #define OCCR_PCICD7  0x00010000 /* PCICD7  */
 554 #define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
 555 #define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
 556 #define OCCR_RES        ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
 557                         | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
 558                         | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
 559                         | OCCR_PCICD1 | OCCR_PCICD2  | OCCR_PCICD3 \
 560                         | OCCR_PCICD4  | OCCR_PCICD5 | OCCR_PCICD6  \
 561                         | OCCR_PCICD7  | OCCR_PCI1CR  | OCCR_PCI2CR )
 562         u32    sccr; /* system clock control Register  */
 563 #define SCCR_TSEC1CM  0xc0000000 /* TSEC1CM  */
 564 #define SCCR_TSEC1CM_SHIFT 30
 565 #define SCCR_TSEC2CM  0x30000000 /* TSEC2CM  */
 566 #define SCCR_TSEC2CM_SHIFT 28
 567 #define SCCR_ENCCM    0x03000000 /* ENCCM  */
 568 #define SCCR_ENCCM_SHIFT 24
 569 #define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM  */
 570 #define SCCR_USBMPHCM_SHIFT 22
 571 #define SCCR_USBDRCM  0x00300000 /* USBDRCM  */
 572 #define SCCR_USBDRCM_SHIFT 20
 573 #define SCCR_PCICM    0x00010000 /* PCICM  */
 574 #define SCCR_RES        ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
 575                         | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
 576         u8     res0[0xF4];
 577 } clk8349_t;
 578
 579 /*
 580  * Power Management Control Module
 581  */
 582 typedef struct pmc8349 {
 583         u32    pmccr; /* PMC Configuration Register  */
 584 #define PMCCR_SLPEN 0x00000001 /* System Low Power Enable  */
 585 #define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable  */
 586 #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
 587         u32    pmcer; /* PMC Event Register  */
 588 #define PMCER_PMCI  0x00000001 /* PMC Interrupt  */
 589 #define PMCER_RES ~(PMCER_PMCI)
 590         u32    pmcmr; /* PMC Mask Register  */
 591 #define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable  */
 592 #define PMCMR_RES ~(PMCMR_PMCIE)
 593         u8 res0[0xF4];
 594 } pmc8349_t;
 595
 596
 597 /*
 598  * general purpose I/O module
 599  */
 600 typedef struct gpio8349 {
 601         u32 dir; /* direction register */
 602         u32 odr; /* open drain register */
 603         u32 dat; /* data register */
 604         u32 ier; /* interrupt event register */
 605         u32 imr; /* interrupt mask register */
 606         u32 icr; /* external interrupt control register */
 607         u8 res0[0xE8];
 608 } gpio8349_t;
 609
 610 /*
 611  * DDR Memory Controller Memory Map
 612  */
 613 typedef struct ddr_cs_bnds{
 614         u32 csbnds;
 615 #define CSBNDS_SA 0x00FF0000
 616 #define CSBNDS_SA_SHIFT    8
 617 #define CSBNDS_EA 0x000000FF
 618 #define CSBNDS_EA_SHIFT   24
 619         u8  res0[4];
 620 } ddr_cs_bnds_t;
 621
 622 typedef struct ddr8349{
 623         ddr_cs_bnds_t csbnds[4];            /**< Chip Select x Memory Bounds */
 624         u8 res0[0x60];
 625         u32 cs_config[4];       /**< Chip Select x Configuration */
 626 #define CSCONFIG_EN         0x80000000
 627 #define CSCONFIG_AP         0x00800000
 628 #define CSCONFIG_ROW_BIT    0x00000700
 629 #define CSCONFIG_ROW_BIT_12 0x00000000
 630 #define CSCONFIG_ROW_BIT_13 0x00000100
 631 #define CSCONFIG_ROW_BIT_14 0x00000200
 632 #define CSCONFIG_COL_BIT    0x00000007
 633 #define CSCONFIG_COL_BIT_8  0x00000000
 634 #define CSCONFIG_COL_BIT_9  0x00000001
 635 #define CSCONFIG_COL_BIT_10 0x00000002
 636 #define CSCONFIG_COL_BIT_11 0x00000003
 637         u8 res1[0x78];
 638         u32 timing_cfg_1;       /**< SDRAM Timing Configuration 1 */
 639 #define TIMING_CFG1_PRETOACT 0x70000000
 640 #define TIMING_CFG1_PRETOACT_SHIFT   28
 641 #define TIMING_CFG1_ACTTOPRE 0x0F000000
 642 #define TIMING_CFG1_ACTTOPRE_SHIFT   24
 643 #define TIMING_CFG1_ACTTORW  0x00700000
 644 #define TIMING_CFG1_ACTTORW_SHIFT    20
 645 #define TIMING_CFG1_CASLAT   0x00070000
 646 #define TIMING_CFG1_CASLAT_SHIFT     16
 647 #define TIMING_CFG1_REFREC   0x0000F000
 648 #define TIMING_CFG1_REFREC_SHIFT     12
 649 #define TIMING_CFG1_WRREC    0x00000700
 650 #define TIMING_CFG1_WRREC_SHIFT       8
 651 #define TIMING_CFG1_ACTTOACT 0x00000070
 652 #define TIMING_CFG1_ACTTOACT_SHIFT    4
 653 #define TIMING_CFG1_WRTORD   0x00000007
 654 #define TIMING_CFG1_WRTORD_SHIFT      0
 655 #define TIMING_CFG1_CASLAT_20 0x00030000  /* CAS latency = 2.0 */
 656 #define TIMING_CFG1_CASLAT_25 0x00040000  /* CAS latency = 2.5 */
 657
 658         u32 timing_cfg_2;       /**< SDRAM Timing Configuration 2 */
 659 #define TIMING_CFG2_CPO           0x0F000000
 660 #define TIMING_CFG2_CPO_SHIFT             24
 661 #define TIMING_CFG2_ACSM          0x00080000
 662 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
 663 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT   10
 664 #define TIMING_CFG2_CPO_DEF       0x00000000  /* default (= CASLAT + 1) */
 665
 666         u32 sdram_cfg;          /**< SDRAM Control Configuration */
 667 #define SDRAM_CFG_MEM_EN     0x80000000
 668 #define SDRAM_CFG_SREN       0x40000000
 669 #define SDRAM_CFG_ECC_EN     0x20000000
 670 #define SDRAM_CFG_RD_EN      0x10000000
 671 #define SDRAM_CFG_SDRAM_TYPE 0x03000000
 672 #define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
 673 #define SDRAM_CFG_DYN_PWR    0x00200000
 674 #define SDRAM_CFG_32_BE      0x00080000
 675 #define SDRAM_CFG_8_BE       0x00040000
 676 #define SDRAM_CFG_NCAP       0x00020000
 677 #define SDRAM_CFG_2T_EN      0x00008000
 678 #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
 679
 680         u8 res2[4];
 681         u32 sdram_mode;         /**< SDRAM Mode Configuration */
 682 #define SDRAM_MODE_ESD 0xFFFF0000
 683 #define SDRAM_MODE_ESD_SHIFT   16
 684 #define SDRAM_MODE_SD  0x0000FFFF
 685 #define SDRAM_MODE_SD_SHIFT     0
 686 #define DDR_MODE_EXT_MODEREG    0x4000  /* select extended mode reg */
 687 #define DDR_MODE_EXT_OPMODE     0x3FF8  /* operating mode, mask */
 688 #define DDR_MODE_EXT_OP_NORMAL  0x0000  /* normal operation */
 689 #define DDR_MODE_QFC            0x0004  /* QFC / compatibility, mask */
 690 #define DDR_MODE_QFC_COMP       0x0000  /* compatible to older SDRAMs */
 691 #define DDR_MODE_WEAK           0x0002  /* weak drivers */
 692 #define DDR_MODE_DLL_DIS        0x0001  /* disable DLL */
 693 #define DDR_MODE_CASLAT         0x0070  /* CAS latency, mask */
 694 #define DDR_MODE_CASLAT_15      0x0010  /* CAS latency 1.5 */
 695 #define DDR_MODE_CASLAT_20      0x0020  /* CAS latency 2 */
 696 #define DDR_MODE_CASLAT_25      0x0060  /* CAS latency 2.5 */
 697 #define DDR_MODE_CASLAT_30      0x0030  /* CAS latency 3 */
 698 #define DDR_MODE_BTYPE_SEQ      0x0000  /* sequential burst */
 699 #define DDR_MODE_BTYPE_ILVD     0x0008  /* interleaved burst */
 700 #define DDR_MODE_BLEN_2         0x0001  /* burst length 2 */
 701 #define DDR_MODE_BLEN_4         0x0002  /* burst length 4 */
 702 #define DDR_REFINT_166MHZ_7US   1302        /* exact value for 7.8125 µs */
 703 #define DDR_BSTOPRE     256     /* use 256 cycles as a starting point */
 704 #define DDR_MODE_MODEREG        0x0000  /* select mode register */
 705
 706         u8 res3[8];
 707         u32 sdram_interval;     /**< SDRAM Interval Configuration */
 708 #define SDRAM_INTERVAL_REFINT  0x3FFF0000
 709 #define SDRAM_INTERVAL_REFINT_SHIFT    16
 710 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
 711 #define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
 712         u8   res9[8];
 713         u32  sdram_clk_cntl;
 714 #define DDR_SDRAM_CLK_CNTL_SS_EN                0x80000000
 715 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05        0x02000000
 716
 717         u8 res4[0xCCC];
 718         u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
 719         u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
 720         u32 ecc_err_inject;     /**< Memory Data Path Error Injection Mask ECC */
 721         u8 res5[0x14];
 722         u32 capture_data_hi;    /**< Memory Data Path Read Capture High */
 723         u32 capture_data_lo;    /**< Memory Data Path Read Capture Low */
 724         u32 capture_ecc;        /**< Memory Data Path Read Capture ECC */
 725         u8 res6[0x14];
 726         u32 err_detect;         /**< Memory Error Detect */
 727         u32 err_disable;        /**< Memory Error Disable */
 728         u32 err_int_en;         /**< Memory Error Interrupt Enable */
 729         u32 capture_attributes; /**< Memory Error Attributes Capture */
 730         u32 capture_address;    /**< Memory Error Address Capture */
 731         u32 capture_ext_address;/**< Memory Error Extended Address Capture */
 732         u32 err_sbe;            /**< Memory Single-Bit ECC Error Management */
 733         u8 res7[0xA4];
 734         u32 debug_reg;
 735         u8 res8[0xFC];
 736 } ddr8349_t;
 737
 738 /*
 739  * I2C1 Controller
 740  */
 741
 742
 743 /*
 744  * DUART
 745  */
 746 typedef struct duart8349{
 747         u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
 748         u8 uier_udmb;      /**< combined register for UIER and UDMB */
 749         u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
 750         u8 ulcr;        /**< line control register */
 751         u8 umcr;        /**< MODEM control register */
 752         u8 ulsr;        /**< line status register */
 753         u8 umsr;        /**< MODEM status register */
 754         u8 uscr;        /**< scratch register */
 755         u8 res0[8];
 756         u8 udsr;        /**< DMA status register */
 757         u8 res1[3];
 758         u8 res2[0xEC];
 759 } duart8349_t;
 760
 761 /*
 762  * Local Bus Controller Registers
 763  */
 764 typedef struct lbus_bank{
 765         u32 br;             /**< Base Register  */
 766         u32 or;             /**< Base Register  */
 767 } lbus_bank_t;
 768
 769 typedef struct lbus8349 {
 770         lbus_bank_t bank[8];
 771         u8 res0[0x28];
 772         u32 mar;                /**< UPM Address Register */
 773         u8 res1[0x4];
 774         u32 mamr;               /**< UPMA Mode Register */
 775         u32 mbmr;               /**< UPMB Mode Register */
 776         u32 mcmr;               /**< UPMC Mode Register */
 777         u8 res2[0x8];
 778         u32 mrtpr;              /**< Memory Refresh Timer Prescaler Register */
 779         u32 mdr;                /**< UPM Data Register */
 780         u8 res3[0x8];
 781         u32 lsdmr;              /**< SDRAM Mode Register */
 782         u8 res4[0x8];
 783         u32 lurt;               /**< UPM Refresh Timer */
 784         u32 lsrt;               /**< SDRAM Refresh Timer */
 785         u8 res5[0x8];
 786         u32 ltesr;              /**< Transfer Error Status Register */
 787         u32 ltedr;              /**< Transfer Error Disable Register */
 788         u32 lteir;              /**< Transfer Error Interrupt Register */
 789         u32 lteatr;             /**< Transfer Error Attributes Register */
 790         u32 ltear;              /**< Transfer Error Address Register */
 791         u8 res6[0xC];
 792         u32 lbcr;               /**< Configuration Register */
 793 #define LBCR_LDIS  0x80000000
 794 #define LBCR_LDIS_SHIFT    31
 795 #define LBCR_BCTLC 0x00C00000
 796 #define LBCR_BCTLC_SHIFT   22
 797 #define LBCR_LPBSE 0x00020000
 798 #define LBCR_LPBSE_SHIFT   17
 799 #define LBCR_EPAR  0x00010000
 800 #define LBCR_EPAR_SHIFT    16
 801 #define LBCR_BMT   0x0000FF00
 802 #define LBCR_BMT_SHIFT      8
 803         u32 lcrr;               /**< Clock Ratio Register */
 804 #define LCRR_DBYP    0x80000000
 805 #define LCRR_DBYP_SHIFT      31
 806 #define LCRR_BUFCMDC 0x30000000
 807 #define LCRR_BUFCMDC_SHIFT   28
 808 #define LCRR_ECL     0x03000000
 809 #define LCRR_ECL_SHIFT       24
 810 #define LCRR_EADC    0x00030000
 811 #define LCRR_EADC_SHIFT      16
 812 #define LCRR_CLKDIV  0x0000000F
 813 #define LCRR_CLKDIV_SHIFT     0
 814
 815
 816         u8 res7[0x28];
 817         u8 res8[0xF00];
 818 } lbus8349_t;
 819
 820 /*
 821  * Serial Peripheral Interface
 822  */
 823 typedef struct spi8349
 824 {
 825         u32 mode;     /**< mode register  */
 826         u32 event;    /**< event register */
 827         u32 mask;     /**< mask register  */
 828         u32 com;      /**< command register */
 829         u8 res0[0x10];
 830         u32 tx;       /**< transmit register */
 831         u32 rx;       /**< receive register */
 832         u8 res1[0xD8];
 833 } spi8349_t;
 834
 835 typedef struct dma8349 {
 836         u8 fixme[0x300];
 837 } dma8349_t;
 838
 839 /*
 840  * PCI Software Configuration Registers
 841  */
 842 typedef struct pciconf8349 {
 843         u32     config_address;
 844 #define PCI_CONFIG_ADDRESS_EN   0x80000000
 845 #define PCI_CONFIG_ADDRESS_BN_SHIFT     16
 846 #define PCI_CONFIG_ADDRESS_BN_MASK      0x00ff0000
 847 #define PCI_CONFIG_ADDRESS_DN_SHIFT     11
 848 #define PCI_CONFIG_ADDRESS_DN_MASK      0x0000f800
 849 #define PCI_CONFIG_ADDRESS_FN_SHIFT     8
 850 #define PCI_CONFIG_ADDRESS_FN_MASK      0x00000700
 851 #define PCI_CONFIG_ADDRESS_RN_SHIFT     0
 852 #define PCI_CONFIG_ADDRESS_RN_MASK      0x000000fc
 853         u32 config_data;
 854         u32 int_ack;
 855         u8      res[116];
 856 } pciconf8349_t;
 857
 858 /*
 859  * PCI Outbound Translation Register
 860  */
 861 typedef struct pci_outbound_window {
 862         u32     potar;
 863         u8      res0[4];
 864         u32     pobar;
 865         u8      res1[4];
 866         u32     pocmr;
 867         u8      res2[4];
 868 } pot8349_t;
 869 /*
 870  * Sequencer
 871  */
 872 typedef struct ios8349 {
 873         pot8349_t       pot[6];
 874 #define POTAR_TA_MASK   0x000fffff
 875 #define POBAR_BA_MASK   0x000fffff
 876 #define POCMR_EN        0x80000000
 877 #define POCMR_IO        0x40000000      /* 0--memory space 1--I/O space */
 878 #define POCMR_SE        0x20000000      /* streaming enable */
 879 #define POCMR_DST       0x10000000      /* 0--PCI1 1--PCI2*/
 880 #define POCMR_CM_MASK   0x000fffff
 881 #define POCMR_CM_4G     0x00000000
 882 #define POCMR_CM_2G     0x00080000
 883 #define POCMR_CM_1G     0x000C0000
 884 #define POCMR_CM_512M   0x000E0000
 885 #define POCMR_CM_256M   0x000F0000
 886 #define POCMR_CM_128M   0x000F8000
 887 #define POCMR_CM_64M    0x000FC000
 888 #define POCMR_CM_32M    0x000FE000
 889 #define POCMR_CM_16M    0x000FF000
 890 #define POCMR_CM_8M     0x000FF800
 891 #define POCMR_CM_4M     0x000FFC00
 892 #define POCMR_CM_2M     0x000FFE00
 893 #define POCMR_CM_1M     0x000FFF00
 894 #define POCMR_CM_512K   0x000FFF80
 895 #define POCMR_CM_256K   0x000FFFC0
 896 #define POCMR_CM_128K   0x000FFFE0
 897 #define POCMR_CM_64K    0x000FFFF0
 898 #define POCMR_CM_32K    0x000FFFF8
 899 #define POCMR_CM_16K    0x000FFFFC
 900 #define POCMR_CM_8K     0x000FFFFE
 901 #define POCMR_CM_4K     0x000FFFFF
 902         u8      res0[0x60];
 903         u32     pmcr;
 904         u8      res1[4];
 905         u32     dtcr;
 906         u8      res2[4];
 907 } ios8349_t;
 908
 909 /*
 910  * PCI Controller Control and Status Registers
 911  */
 912 typedef struct pcictrl8349 {
 913         u32     esr;
 914 #define ESR_MERR        0x80000000
 915 #define ESR_APAR        0x00000400
 916 #define ESR_PCISERR     0x00000200
 917 #define ESR_MPERR       0x00000100
 918 #define ESR_TPERR       0x00000080
 919 #define ESR_NORSP       0x00000040
 920 #define ESR_TABT        0x00000020
 921         u32     ecdr;
 922 #define ECDR_APAR       0x00000400
 923 #define ECDR_PCISERR    0x00000200
 924 #define ECDR_MPERR      0x00000100
 925 #define ECDR_TPERR      0x00000080
 926 #define ECDR_NORSP      0x00000040
 927 #define ECDR_TABT       0x00000020
 928         u32 eer;
 929 #define EER_APAR        0x00000400
 930 #define EER_PCISERR     0x00000200
 931 #define EER_MPERR       0x00000100
 932 #define EER_TPERR       0x00000080
 933 #define EER_NORSP       0x00000040
 934 #define EER_TABT        0x00000020
 935         u32     eatcr;
 936 #define EATCR_ERRTYPR_MASK      0x70000000
 937 #define EATCR_ERRTYPR_APR       0x00000000      /* address parity error */
 938 #define EATCR_ERRTYPR_WDPR      0x10000000      /* write data parity error */
 939 #define EATCR_ERRTYPR_RDPR      0x20000000      /* read data parity error */
 940 #define EATCR_ERRTYPR_MA        0x30000000      /* master abort */
 941 #define EATCR_ERRTYPR_TA        0x40000000      /* target abort */
 942 #define EATCR_ERRTYPR_SE        0x50000000      /* system error indication received */
 943 #define EATCR_ERRTYPR_PEA       0x60000000      /* parity error indication received on a read */
 944 #define EATCR_ERRTYPR_PEW       0x70000000      /* parity error indication received on a write */
 945 #define EATCR_BN_MASK           0x0f000000      /* beat number */
 946 #define EATCR_BN_1st            0x00000000
 947 #define EATCR_BN_2ed            0x01000000
 948 #define EATCR_BN_3rd            0x02000000
 949 #define EATCR_BN_4th            0x03000000
 950 #define EATCR_BN_5th            0x0400000
 951 #define EATCR_BN_6th            0x05000000
 952 #define EATCR_BN_7th            0x06000000
 953 #define EATCR_BN_8th            0x07000000
 954 #define EATCR_BN_9th            0x08000000
 955 #define EATCR_TS_MASK           0x00300000      /* transaction size */
 956 #define EATCR_TS_4              0x00000000
 957 #define EATCR_TS_1              0x00100000
 958 #define EATCR_TS_2              0x00200000
 959 #define EATCR_TS_3              0x00300000
 960 #define EATCR_ES_MASK           0x000f0000      /* error source */
 961 #define EATCR_ES_EM             0x00000000      /* external master */
 962 #define EATCR_ES_DMA            0x00050000
 963 #define EATCR_CMD_MASK          0x0000f000
 964 #define EATCR_HBE_MASK          0x00000f00      /* PCI high byte enable*/
 965 #define EATCR_BE_MASK           0x000000f0      /* PCI byte enable */
 966 #define EATCR_HPB               0x00000004      /* high parity bit */
 967 #define EATCR_PB                0x00000002      /* parity bit*/
 968 #define EATCR_VI                0x00000001      /* error information valid */
 969         u32     eacr;
 970         u32     eeacr;
 971         u32     edlcr;
 972         u32     edhcr;
 973         u32     gcr;
 974         u32     ecr;
 975         u32     gsr;
 976         u8      res0[12];
 977         u32     pitar2;
 978         u8      res1[4];
 979         u32     pibar2;
 980         u32     piebar2;
 981         u32     piwar2;
 982         u8      res2[4];
 983         u32     pitar1;
 984         u8      res3[4];
 985         u32     pibar1;
 986         u32     piebar1;
 987         u32     piwar1;
 988         u8      res4[4];
 989         u32     pitar0;
 990         u8      res5[4];
 991         u32     pibar0;
 992         u8      res6[4];
 993         u32     piwar0;
 994         u8      res7[132];
 995 #define PITAR_TA_MASK           0x000fffff
 996 #define PIBAR_MASK              0xffffffff
 997 #define PIEBAR_EBA_MASK         0x000fffff
 998 #define PIWAR_EN                0x80000000
 999 #define PIWAR_PF                0x20000000
1000 #define PIWAR_RTT_MASK          0x000f0000
1001 #define PIWAR_RTT_NO_SNOOP      0x00040000
1002 #define PIWAR_RTT_SNOOP         0x00050000
1003 #define PIWAR_WTT_MASK          0x0000f000
1004 #define PIWAR_WTT_NO_SNOOP      0x00004000
1005 #define PIWAR_WTT_SNOOP         0x00005000
1006 #define PIWAR_IWS_MASK  0x0000003F
1007 #define PIWAR_IWS_4K    0x0000000B
1008 #define PIWAR_IWS_8K    0x0000000C
1009 #define PIWAR_IWS_16K   0x0000000D
1010 #define PIWAR_IWS_32K   0x0000000E
1011 #define PIWAR_IWS_64K   0x0000000F
1012 #define PIWAR_IWS_128K  0x00000010
1013 #define PIWAR_IWS_256K  0x00000011
1014 #define PIWAR_IWS_512K  0x00000012
1015 #define PIWAR_IWS_1M    0x00000013
1016 #define PIWAR_IWS_2M    0x00000014
1017 #define PIWAR_IWS_4M    0x00000015
1018 #define PIWAR_IWS_8M    0x00000016
1019 #define PIWAR_IWS_16M   0x00000017
1020 #define PIWAR_IWS_32M   0x00000018
1021 #define PIWAR_IWS_64M   0x00000019
1022 #define PIWAR_IWS_128M  0x0000001A
1023 #define PIWAR_IWS_256M  0x0000001B
1024 #define PIWAR_IWS_512M  0x0000001C
1025 #define PIWAR_IWS_1G    0x0000001D
1026 #define PIWAR_IWS_2G    0x0000001E
1027 } pcictrl8349_t;
1028
1029 /*
1030  * USB
1031  */
1032 typedef struct usb8349 {
1033         u8 fixme[0x2000];
1034 } usb8349_t;
1035
1036 /*
1037  * TSEC
1038  */
1039 typedef struct tsec8349 {
1040         u8 fixme[0x1000];
1041 } tsec8349_t;
1042
1043 /*
1044  * Security
1045  */
1046 typedef struct security8349 {
1047         u8 fixme[0x10000];
1048 } security8349_t;
1049
1050 typedef struct immap {
1051         sysconf8349_t sysconf; /* System configuration */
1052         wdt8349_t     wdt;     /* Watch Dog Timer (WDT) Registers */
1053         rtclk8349_t   rtc;     /* Real Time Clock Module Registers */
1054         rtclk8349_t   pit;     /* Periodic Interval Timer */
1055         gtm8349_t     gtm[2];  /* Global Timers Module */
1056         ipic8349_t    ipic;    /* Integrated Programmable Interrupt Controller */
1057         arbiter8349_t arbiter; /* System Arbiter Registers */
1058         reset8349_t   reset;   /* Reset Module */
1059         clk8349_t     clk;     /* System Clock Module */
1060         pmc8349_t     pmc;     /* Power Management Control Module */
1061         gpio8349_t    pgio[2]; /* general purpose I/O module */
1062         u8 res0[0x200];
1063         u8 DDL_DDR[0x100];
1064         u8 DDL_LBIU[0x100];
1065         u8 res1[0xE00];
1066         ddr8349_t     ddr;     /* DDR Memory Controller Memory */
1067         i2c_t     i2c[2];      /* I2C1 Controller */
1068         u8 res2[0x1300];
1069         duart8349_t   duart[2];/* DUART */
1070         u8 res3[0x900];
1071         lbus8349_t    lbus;    /* Local Bus Controller Registers */
1072         u8 res4[0x1000];
1073         spi8349_t     spi;     /* Serial Peripheral Interface */
1074         u8 res5[0xF00];
1075         dma8349_t     dma;     /* DMA */
1076         pciconf8349_t pci_conf[2];  /* PCI Software Configuration Registers */
1077         ios8349_t     ios;     /* Sequencer */
1078         pcictrl8349_t pci_ctrl[2];  /* PCI Controller Control and Status Registers */
1079         u8 res6[0x19900];
1080         usb8349_t     usb;
1081         tsec8349_t    tsec[2];
1082         u8 res7[0xA000];
1083         security8349_t security;
1084 } immap_t;
1085
1086 #endif /* __IMMAP_8349__ */