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[people/ms/u-boot.git] / include / asm-ppc / processor.h
1 #ifndef __ASM_PPC_PROCESSOR_H
2 #define __ASM_PPC_PROCESSOR_H
3
4 /*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10 #include <linux/config.h>
11
12 #include <asm/ptrace.h>
13 #include <asm/types.h>
14
15 /* Machine State Register (MSR) Fields */
16
17 #ifdef CONFIG_PPC64BRIDGE
18 #define MSR_SF (1<<63)
19 #define MSR_ISF (1<<61)
20 #endif /* CONFIG_PPC64BRIDGE */
21 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
22 #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
23 #define MSR_SPE (1<<25) /* Enable SPE(e500) */
24 #define MSR_POW (1<<18) /* Enable Power Management */
25 #define MSR_WE (1<<18) /* Wait State Enable */
26 #define MSR_TGPR (1<<17) /* TLB Update registers in use */
27 #define MSR_CE (1<<17) /* Critical Interrupt Enable */
28 #define MSR_ILE (1<<16) /* Interrupt Little Endian */
29 #define MSR_EE (1<<15) /* External Interrupt Enable */
30 #define MSR_PR (1<<14) /* Problem State / Privilege Level */
31 #define MSR_FP (1<<13) /* Floating Point enable */
32 #define MSR_ME (1<<12) /* Machine Check Enable */
33 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
34 #define MSR_SE (1<<10) /* Single Step */
35 #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
36 #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
37 #define MSR_BE (1<<9) /* Branch Trace */
38 #define MSR_DE (1<<9) /* Debug Exception Enable */
39 #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
40 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
41 #define MSR_IR (1<<5) /* Instruction Relocate */
42 #define MSR_IS (1<<5) /* Book E Instruction space */
43 #define MSR_DR (1<<4) /* Data Relocate */
44 #define MSR_DS (1<<4) /* Book E Data space */
45 #define MSR_PE (1<<3) /* Protection Enable */
46 #define MSR_PX (1<<2) /* Protection Exclusive Mode */
47 #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
48 #define MSR_RI (1<<1) /* Recoverable Exception */
49 #define MSR_LE (1<<0) /* Little Endian */
50
51 #ifdef CONFIG_APUS_FAST_EXCEPT
52 #define MSR_ MSR_ME|MSR_IP|MSR_RI
53 #else
54 #define MSR_ MSR_ME|MSR_RI
55 #endif
56 #ifndef CONFIG_E500
57 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR
58 #else
59 #define MSR_KERNEL MSR_ME
60 #endif
61
62 /* Floating Point Status and Control Register (FPSCR) Fields */
63
64 #define FPSCR_FX 0x80000000 /* FPU exception summary */
65 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
66 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
67 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
68 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
69 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
70 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
71 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
72 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
73 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
74 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
75 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
76 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
77 #define FPSCR_FR 0x00040000 /* Fraction rounded */
78 #define FPSCR_FI 0x00020000 /* Fraction inexact */
79 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
80 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
81 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
82 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
83 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
84 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
85 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
86 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
87 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
88 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
89 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
90 #define FPSCR_RN 0x00000003 /* FPU rounding control */
91
92 /* Special Purpose Registers (SPRNs)*/
93
94 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
95 #define SPRN_CTR 0x009 /* Count Register */
96 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
97 #ifndef CONFIG_BOOKE
98 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
99 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
100 #else
101 #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
102 #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
103 #endif /* CONFIG_BOOKE */
104 #define SPRN_DAR 0x013 /* Data Address Register */
105 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
106 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
107 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
108 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
109 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
110 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
111 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
112 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
113 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
114 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
115 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
116 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
117 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
118 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
119 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
120 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
121 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
122 #define DBCR_EDM 0x80000000
123 #define DBCR_IDM 0x40000000
124 #define DBCR_RST(x) (((x) & 0x3) << 28)
125 #define DBCR_RST_NONE 0
126 #define DBCR_RST_CORE 1
127 #define DBCR_RST_CHIP 2
128 #define DBCR_RST_SYSTEM 3
129 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
130 #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
131 #define DBCR_EDE 0x02000000 /* Exception Debug Event */
132 #define DBCR_TDE 0x01000000 /* TRAP Debug Event */
133 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
134 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
135 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
136 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
137 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
138 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
139 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
140 #define DAC_BYTE 0
141 #define DAC_HALF 1
142 #define DAC_WORD 2
143 #define DAC_QUAD 3
144 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
145 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
146 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
147 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
148 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
149 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
150 #define DBCR_SIA 0x00000008 /* Second IAC Enable */
151 #define DBCR_SDA 0x00000004 /* Second DAC Enable */
152 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
153 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
154 #ifndef CONFIG_BOOKE
155 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
156 #else
157 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
158 #endif /* CONFIG_BOOKE */
159 #ifndef CONFIG_BOOKE
160 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
161 #define SPRN_DBSR 0x3F0 /* Debug Status Register */
162 #else
163 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
164 #define SPRN_DBSR 0x130 /* Book E Debug Status Register */
165 #define DBSR_IC 0x08000000 /* Book E Instruction Completion */
166 #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
167 #endif /* CONFIG_BOOKE */
168 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
169 #define DCCR_NOCACHE 0 /* Noncacheable */
170 #define DCCR_CACHE 1 /* Cacheable */
171 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
172 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
173 #define DCWR_COPY 0 /* Copy-back */
174 #define DCWR_WRITE 1 /* Write-through */
175 #ifndef CONFIG_BOOKE
176 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
177 #else
178 #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
179 #endif /* CONFIG_BOOKE */
180 #define SPRN_DEC 0x016 /* Decrement Register */
181 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
182 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
183 #define SPRN_EAR 0x11A /* External Address Register */
184 #ifndef CONFIG_BOOKE
185 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
186 #else
187 #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
188 #endif /* CONFIG_BOOKE */
189 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
190 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
191 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
192 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
193 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
194 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
195 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
196 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
197 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
198 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
199 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
200 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
201 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
202
203 #define HID0_ICE_SHIFT 15
204 #define HID0_DCE_SHIFT 14
205 #define HID0_DLOCK_SHIFT 12
206
207 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
208 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
209 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
210 #define HID0_SBCLK (1<<27)
211 #define HID0_EICE (1<<26)
212 #define HID0_ECLK (1<<25)
213 #define HID0_PAR (1<<24)
214 #define HID0_DOZE (1<<23)
215 #define HID0_NAP (1<<22)
216 #define HID0_SLEEP (1<<21)
217 #define HID0_DPM (1<<20)
218 #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
219 #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
220 #define HID0_TBEN (1<<14) /* Time Base Enable */
221 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
222 #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
223 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
224 #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
225 #define HID0_DCI HID0_DCFI
226 #define HID0_SPD (1<<9) /* Speculative disable */
227 #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
228 #define HID0_SGE (1<<7) /* Store Gathering Enable */
229 #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
230 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
231 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
232 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
233 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
234 #define HID0_BTCD (1<<1) /* Branch target cache disable */
235 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
236 #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
237 #define HID1_ASTME (1<<13) /* Address bus streaming mode */
238 #define HID1_ABE (1<<12) /* Address broadcast enable */
239 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
240 #ifndef CONFIG_BOOKE
241 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
242 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
243 #else
244 #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
245 #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
246 #endif /* CONFIG_BOOKE */
247 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
248 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
249 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
250 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
251 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
252 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
253 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
254 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
255 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
256 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
257 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
258 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
259 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
260 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
261 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
262 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
263 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
264 #define ICCR_NOCACHE 0 /* Noncacheable */
265 #define ICCR_CACHE 1 /* Cacheable */
266 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
267 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
268 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
269 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
270 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
271 #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
272 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
273 #define SPRN_LR 0x008 /* Link Register */
274 #define SPRN_MBAR 0x137 /* System memory base address */
275 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
276 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
277 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
278 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
279 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
280 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
281 #ifndef CONFIG_BOOKE
282 #define SPRN_PID 0x3B1 /* Process ID */
283 #define SPRN_PIR 0x3FF /* Processor Identification Register */
284 #else
285 #define SPRN_PID 0x030 /* Book E Process ID */
286 #define SPRN_PIR 0x11E /* Book E Processor Identification Register */
287 #endif /* CONFIG_BOOKE */
288 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
289 #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
290 #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
291 #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
292 #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
293 #define SPRN_PVR 0x11F /* Processor Version Register */
294 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
295 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
296 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
297 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
298 #define SGR_NORMAL 0
299 #define SGR_GUARDED 1
300 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
301 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
302 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
303 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
304 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
305 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
306 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
307 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
308 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
309 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
310 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
311 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
312 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
313 #ifdef CONFIG_BOOKE
314 #define SPRN_SVR 0x3FF /* System Version Register */
315 #else
316 #define SPRN_SVR 0x11E /* System Version Register */
317 #endif
318 #define SPRN_TBHI 0x3DC /* Time Base High */
319 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
320 #define SPRN_TBLO 0x3DD /* Time Base Low */
321 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
322 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
323 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
324 #define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
325 #define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
326 #ifndef CONFIG_BOOKE
327 #define SPRN_TCR 0x3DA /* Timer Control Register */
328 #else
329 #define SPRN_TCR 0x154 /* Book E Timer Control Register */
330 #endif /* CONFIG_BOOKE */
331 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
332 #define WP_2_17 0 /* 2^17 clocks */
333 #define WP_2_21 1 /* 2^21 clocks */
334 #define WP_2_25 2 /* 2^25 clocks */
335 #define WP_2_29 3 /* 2^29 clocks */
336 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
337 #define WRC_NONE 0 /* No reset will occur */
338 #define WRC_CORE 1 /* Core reset will occur */
339 #define WRC_CHIP 2 /* Chip reset will occur */
340 #define WRC_SYSTEM 3 /* System reset will occur */
341 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
342 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
343 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
344 #define FP_2_9 0 /* 2^9 clocks */
345 #define FP_2_13 1 /* 2^13 clocks */
346 #define FP_2_17 2 /* 2^17 clocks */
347 #define FP_2_21 3 /* 2^21 clocks */
348 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
349 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
350 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
351 #define THRM1_TIN (1<<0)
352 #define THRM1_TIV (1<<1)
353 #define THRM1_THRES (0x7f<<2)
354 #define THRM1_TID (1<<29)
355 #define THRM1_TIE (1<<30)
356 #define THRM1_V (1<<31)
357 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
358 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
359 #define THRM3_E (1<<31)
360 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
361 #ifndef CONFIG_BOOKE
362 #define SPRN_TSR 0x3D8 /* Timer Status Register */
363 #else
364 #define SPRN_TSR 0x150 /* Book E Timer Status Register */
365 #endif /* CONFIG_BOOKE */
366 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
367 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
368 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
369 #define WRS_NONE 0 /* No WDT reset occurred */
370 #define WRS_CORE 1 /* WDT forced core reset */
371 #define WRS_CHIP 2 /* WDT forced chip reset */
372 #define WRS_SYSTEM 3 /* WDT forced system reset */
373 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
374 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
375 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
376 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
377 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
378 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
379 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
380 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
381 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
382 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
383 #define SPRN_ZPR 0x3B0 /* Zone Protection Register */
384
385 /* Book E definitions */
386 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
387 #define SPRN_CSRR0 0x03A /* Critical SRR0 */
388 #define SPRN_CSRR1 0x03B /* Critical SRR0 */
389 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
390 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
391 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
392 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
393 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
394 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
395 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
396 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
397 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
398 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
399 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
400 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
401 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
402 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
403 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
404 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
405 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
406 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
407 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
408 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
409 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
410 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
411 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
412 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
413 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
414 #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
415 #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
416 #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
417 #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
418 #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
419 #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
420
421 /* e500 definitions */
422 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
423 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
424 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
425 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
426 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
427 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
428 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
429 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
430
431 #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
432 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
433 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
434 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
435 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
436 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
437 #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
438 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
439 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
440
441 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
442 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
443 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
444 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
445 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
446
447 #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
448 #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
449 #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
450 #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
451 #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
452 #define SPRN_PID1 0x279 /* Process ID Register 1 */
453 #define SPRN_PID2 0x27a /* Process ID Register 2 */
454 #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
455 #define SPRN_MCAR 0x23d /* Machine Check Address register */
456 #ifdef CONFIG_440
457 #define MCSR_MCS 0x80000000 /* Machine Check Summary */
458 #define MCSR_IB 0x40000000 /* Instruction PLB Error */
459 #define MCSR_DRB 0x20000000 /* Data Read PLB Error */
460 #define MCSR_DWB 0x10000000 /* Data Write PLB Error */
461 #define MCSR_TLBP 0x08000000 /* TLB Parity Error */
462 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
463 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
464 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
465 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
466 #endif
467 #define ESR_ST 0x00800000 /* Store Operation */
468
469 #if defined(CONFIG_MPC86xx)
470 #define SPRN_MSSCR0 0x3f6
471 #define SPRN_MSSSR0 0x3f7
472 #endif
473
474
475 /* Short-hand versions for a number of the above SPRNs */
476
477 #define CTR SPRN_CTR /* Counter Register */
478 #define DAR SPRN_DAR /* Data Address Register */
479 #define DABR SPRN_DABR /* Data Address Breakpoint Register */
480 #define DAC1 SPRN_DAC1 /* Data Address Register 1 */
481 #define DAC2 SPRN_DAC2 /* Data Address Register 2 */
482 #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
483 #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
484 #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
485 #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
486 #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
487 #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
488 #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
489 #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
490 #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
491 #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
492 #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
493 #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
494 #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
495 #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
496 #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
497 #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
498 #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
499 #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
500 #define DBSR SPRN_DBSR /* Debug Status Register */
501 #define DCMP SPRN_DCMP /* Data TLB Compare Register */
502 #define DEC SPRN_DEC /* Decrement Register */
503 #define DMISS SPRN_DMISS /* Data TLB Miss Register */
504 #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
505 #define EAR SPRN_EAR /* External Address Register */
506 #define ESR SPRN_ESR /* Exception Syndrome Register */
507 #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
508 #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
509 #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
510 #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
511 #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
512 #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
513 #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
514 #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
515 #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
516 #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
517 #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
518 #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
519 #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
520 #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
521 #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
522 #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
523 #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
524 #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
525 #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
526 #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
527 #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
528 #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
529 #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
530 #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
531 #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
532 #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
533 #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
534 #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
535 #define LR SPRN_LR
536 #define MBAR SPRN_MBAR /* System memory base address */
537 #if defined(CONFIG_MPC86xx)
538 #define MSSCR0 SPRN_MSSCR0
539 #endif
540 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
541 #define PIR SPRN_PIR
542 #endif
543 #define SVR SPRN_SVR /* System-On-Chip Version Register */
544 #define PVR SPRN_PVR /* Processor Version */
545 #define RPA SPRN_RPA /* Required Physical Address Register */
546 #define SDR1 SPRN_SDR1 /* MMU hash base register */
547 #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
548 #define SPR1 SPRN_SPRG1
549 #define SPR2 SPRN_SPRG2
550 #define SPR3 SPRN_SPRG3
551 #define SPRG0 SPRN_SPRG0
552 #define SPRG1 SPRN_SPRG1
553 #define SPRG2 SPRN_SPRG2
554 #define SPRG3 SPRN_SPRG3
555 #define SPRG4 SPRN_SPRG4
556 #define SPRG5 SPRN_SPRG5
557 #define SPRG6 SPRN_SPRG6
558 #define SPRG7 SPRN_SPRG7
559 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
560 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
561 #define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
562 #define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
563 #define SVR SPRN_SVR /* System Version Register */
564 #define TBRL SPRN_TBRL /* Time Base Read Lower Register */
565 #define TBRU SPRN_TBRU /* Time Base Read Upper Register */
566 #define TBWL SPRN_TBWL /* Time Base Write Lower Register */
567 #define TBWU SPRN_TBWU /* Time Base Write Upper Register */
568 #define TCR SPRN_TCR /* Timer Control Register */
569 #define TSR SPRN_TSR /* Timer Status Register */
570 #define ICTC 1019
571 #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
572 #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
573 #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
574 #define XER SPRN_XER
575
576 #define DECAR SPRN_DECAR
577 #define CSRR0 SPRN_CSRR0
578 #define CSRR1 SPRN_CSRR1
579 #define IVPR SPRN_IVPR
580 #define USPRG0 SPRN_USPRG
581 #define SPRG4R SPRN_SPRG4R
582 #define SPRG5R SPRN_SPRG5R
583 #define SPRG6R SPRN_SPRG6R
584 #define SPRG7R SPRN_SPRG7R
585 #define SPRG4W SPRN_SPRG4W
586 #define SPRG5W SPRN_SPRG5W
587 #define SPRG6W SPRN_SPRG6W
588 #define SPRG7W SPRN_SPRG7W
589 #define DEAR SPRN_DEAR
590 #define DBCR2 SPRN_DBCR2
591 #define IAC3 SPRN_IAC3
592 #define IAC4 SPRN_IAC4
593 #define DVC1 SPRN_DVC1
594 #define DVC2 SPRN_DVC2
595 #define IVOR0 SPRN_IVOR0
596 #define IVOR1 SPRN_IVOR1
597 #define IVOR2 SPRN_IVOR2
598 #define IVOR3 SPRN_IVOR3
599 #define IVOR4 SPRN_IVOR4
600 #define IVOR5 SPRN_IVOR5
601 #define IVOR6 SPRN_IVOR6
602 #define IVOR7 SPRN_IVOR7
603 #define IVOR8 SPRN_IVOR8
604 #define IVOR9 SPRN_IVOR9
605 #define IVOR10 SPRN_IVOR10
606 #define IVOR11 SPRN_IVOR11
607 #define IVOR12 SPRN_IVOR12
608 #define IVOR13 SPRN_IVOR13
609 #define IVOR14 SPRN_IVOR14
610 #define IVOR15 SPRN_IVOR15
611 #define IVOR32 SPRN_IVOR32
612 #define IVOR33 SPRN_IVOR33
613 #define IVOR34 SPRN_IVOR34
614 #define IVOR35 SPRN_IVOR35
615 #define MCSRR0 SPRN_MCSRR0
616 #define MCSRR1 SPRN_MCSRR1
617 #define L1CSR0 SPRN_L1CSR0
618 #define L1CSR1 SPRN_L1CSR1
619 #define MCSR SPRN_MCSR
620 #define MMUCSR0 SPRN_MMUCSR0
621 #define BUCSR SPRN_BUCSR
622 #define PID0 SPRN_PID
623 #define PID1 SPRN_PID1
624 #define PID2 SPRN_PID2
625 #define MAS0 SPRN_MAS0
626 #define MAS1 SPRN_MAS1
627 #define MAS2 SPRN_MAS2
628 #define MAS3 SPRN_MAS3
629 #define MAS4 SPRN_MAS4
630 #define MAS5 SPRN_MAS5
631 #define MAS6 SPRN_MAS6
632 #define MAS7 SPRN_MAS7
633
634 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
635 #define DAR_DEAR DEAR
636 #else
637 #define DAR_DEAR DAR
638 #endif
639
640 /* Device Control Registers */
641
642 #define DCRN_BEAR 0x090 /* Bus Error Address Register */
643 #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
644 #define BESR_DSES 0x80000000 /* Data-Side Error Status */
645 #define BESR_DMES 0x40000000 /* DMA Error Status */
646 #define BESR_RWS 0x20000000 /* Read/Write Status */
647 #define BESR_ETMASK 0x1C000000 /* Error Type */
648 #define ET_PROT 0
649 #define ET_PARITY 1
650 #define ET_NCFG 2
651 #define ET_BUSERR 4
652 #define ET_BUSTO 6
653 #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
654 #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
655 #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
656 #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
657 #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
658 #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
659 #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
660 #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
661 #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
662 #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
663 #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
664 #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
665 #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
666 #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
667 #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
668 #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
669 #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
670 #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
671 #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
672 #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
673 #define DCRN_DMASR 0x0E0 /* DMA Status Register */
674 #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
675 #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
676 #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
677 #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
678 #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
679 #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
680 #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
681 #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
682 #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
683 #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
684 #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
685 #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
686 #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
687 #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
688 #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
689 #define DCRN_EXISR 0x040 /* External Interrupt Status Register */
690 #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
691 #define IOCR_E0TE 0x80000000
692 #define IOCR_E0LP 0x40000000
693 #define IOCR_E1TE 0x20000000
694 #define IOCR_E1LP 0x10000000
695 #define IOCR_E2TE 0x08000000
696 #define IOCR_E2LP 0x04000000
697 #define IOCR_E3TE 0x02000000
698 #define IOCR_E3LP 0x01000000
699 #define IOCR_E4TE 0x00800000
700 #define IOCR_E4LP 0x00400000
701 #define IOCR_EDT 0x00080000
702 #define IOCR_SOR 0x00040000
703 #define IOCR_EDO 0x00008000
704 #define IOCR_2XC 0x00004000
705 #define IOCR_ATC 0x00002000
706 #define IOCR_SPD 0x00001000
707 #define IOCR_BEM 0x00000800
708 #define IOCR_PTD 0x00000400
709 #define IOCR_ARE 0x00000080
710 #define IOCR_DRC 0x00000020
711 #define IOCR_RDM(x) (((x) & 0x3) << 3)
712 #define IOCR_TCS 0x00000004
713 #define IOCR_SCS 0x00000002
714 #define IOCR_SPC 0x00000001
715
716 /* System-On-Chip Version Register */
717
718 /* System-On-Chip Version Register (SVR) field extraction */
719
720 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
721 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
722
723 #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
724 #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
725 #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
726 #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
727 #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
728 #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
729 #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
730
731
732 /* Processor Version Register */
733
734 /* Processor Version Register (PVR) field extraction */
735
736 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
737 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
738
739 /*
740 * AMCC has further subdivided the standard PowerPC 16-bit version and
741 * revision subfields of the PVR for the PowerPC 403s into the following:
742 */
743
744 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
745 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
746 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
747 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
748 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
749 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
750
751 /* Processor Version Numbers */
752
753 #define PVR_403GA 0x00200000
754 #define PVR_403GB 0x00200100
755 #define PVR_403GC 0x00200200
756 #define PVR_403GCX 0x00201400
757 #define PVR_405GP 0x40110000
758 #define PVR_405GP_RB 0x40110040
759 #define PVR_405GP_RC 0x40110082
760 #define PVR_405GP_RD 0x401100C4
761 #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
762 #define PVR_405CR_RA 0x40110041
763 #define PVR_405CR_RB 0x401100C5
764 #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
765 #define PVR_405EP_RA 0x51210950
766 #define PVR_405GPR_RB 0x50910951
767 #define PVR_405EZ_RA 0x41511460
768 #define PVR_440GP_RB 0x40120440
769 #define PVR_440GP_RC 0x40120481
770 #define PVR_440EP_RA 0x42221850
771 #define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
772 #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
773 #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
774 #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
775 #define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
776 #define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
777 #define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
778 #define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
779 #define PVR_440GX_RA 0x51B21850
780 #define PVR_440GX_RB 0x51B21851
781 #define PVR_440GX_RC 0x51B21892
782 #define PVR_440GX_RF 0x51B21894
783 #define PVR_405EP_RB 0x51210950
784 #define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
785 #define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
786 #define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
787 #define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
788 #define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
789 #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
790 #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
791 #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
792 #define PVR_601 0x00010000
793 #define PVR_602 0x00050000
794 #define PVR_603 0x00030000
795 #define PVR_603e 0x00060000
796 #define PVR_603ev 0x00070000
797 #define PVR_603r 0x00071000
798 #define PVR_604 0x00040000
799 #define PVR_604e 0x00090000
800 #define PVR_604r 0x000A0000
801 #define PVR_620 0x00140000
802 #define PVR_740 0x00080000
803 #define PVR_750 PVR_740
804 #define PVR_740P 0x10080000
805 #define PVR_750P PVR_740P
806 #define PVR_7400 0x000C0000
807 #define PVR_7410 0x800C0000
808 #define PVR_7450 0x80000000
809
810 #define PVR_85xx 0x80200000
811 #define PVR_85xx_REV1 (PVR_85xx | 0x0010)
812 #define PVR_85xx_REV2 (PVR_85xx | 0x0020)
813
814 #define PVR_86xx 0x80040000
815 #define PVR_86xx_REV1 (PVR_86xx | 0x0010)
816
817 /*
818 * For the 8xx processors, all of them report the same PVR family for
819 * the PowerPC core. The various versions of these processors must be
820 * differentiated by the version number in the Communication Processor
821 * Module (CPM).
822 */
823 #define PVR_821 0x00500000
824 #define PVR_823 PVR_821
825 #define PVR_850 PVR_821
826 #define PVR_860 PVR_821
827 #define PVR_7400 0x000C0000
828 #define PVR_8240 0x00810100
829
830 /*
831 * PowerQUICC II family processors report different PVR values depending
832 * on silicon process (HiP3, HiP4, HiP7, etc.)
833 */
834 #define PVR_8260 PVR_8240
835 #define PVR_8260_HIP3 0x00810101
836 #define PVR_8260_HIP4 0x80811014
837 #define PVR_8260_HIP7 0x80822011
838 #define PVR_8260_HIP7R1 0x80822013
839 #define PVR_8260_HIP7RA 0x80822014
840
841 /*
842 * MPC 52xx
843 */
844 #define PVR_5200 0x80822011
845 #define PVR_5200B 0x80822014
846
847
848 /*
849 * System Version Register
850 */
851
852 /* System Version Register (SVR) field extraction */
853
854 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
855 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
856
857 #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
858
859 #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
860 #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
861
862 #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
863 #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
864
865
866 /*
867 * SVR_VER() Version Values
868 */
869
870 #define SVR_8540 0x8030
871 #define SVR_8560 0x8070
872 #define SVR_8555 0x8079
873 #define SVR_8541 0x807A
874 #define SVR_8544 0x8034
875 #define SVR_8544_E 0x803C
876 #define SVR_8548 0x8031
877 #define SVR_8548_E 0x8039
878 #define SVR_8610 0x80A0
879 #define SVR_8641 0x8090
880 #define SVR_8568_E 0x807D
881
882
883 /* I am just adding a single entry for 8260 boards. I think we may be
884 * able to combine mbx, fads, rpxlite, bseip, and classic into a single
885 * generic 8xx as well. The boards containing these processors are either
886 * identical at the processor level (due to the high integration) or so
887 * wildly different that testing _machine at run time is best replaced by
888 * conditional compilation by board type (found in their respective .h file).
889 * -- Dan
890 */
891 #define _MACH_prep 0x00000001
892 #define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
893 #define _MACH_chrp 0x00000004 /* chrp machine */
894 #define _MACH_mbx 0x00000008 /* Motorola MBX board */
895 #define _MACH_apus 0x00000010 /* amiga with phase5 powerup */
896 #define _MACH_fads 0x00000020 /* Motorola FADS board */
897 #define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */
898 #define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */
899 #define _MACH_yk 0x00000100 /* Motorola Yellowknife */
900 #define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */
901 #define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */
902 #define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */
903 #define _MACH_walnut 0x00001000 /* AMCC "Walnut" 405GP eval. board */
904 #define _MACH_8260 0x00002000 /* Generic 8260 */
905 #define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */
906 #define _MACH_tqm860 0x00008000 /* TQM860/L */
907 #define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */
908 #define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */
909
910
911 /* see residual.h for these */
912 #define _PREP_Motorola 0x01 /* motorola prep */
913 #define _PREP_Firm 0x02 /* firmworks prep */
914 #define _PREP_IBM 0x00 /* ibm prep */
915 #define _PREP_Bull 0x03 /* bull prep */
916 #define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */
917
918 /*
919 * Radstone board types
920 */
921 #define RS_SYS_TYPE_PPC1 0
922 #define RS_SYS_TYPE_PPC2 1
923 #define RS_SYS_TYPE_PPC1a 2
924 #define RS_SYS_TYPE_PPC2a 3
925 #define RS_SYS_TYPE_PPC4 4
926 #define RS_SYS_TYPE_PPC4a 5
927 #define RS_SYS_TYPE_PPC2ep 6
928
929 /* these are arbitrary */
930 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
931 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
932
933 #define _GLOBAL(n)\
934 .globl n;\
935 n:
936
937 /* Macros for setting and retrieving special purpose registers */
938
939 #define stringify(s) tostring(s)
940 #define tostring(s) #s
941
942 #define mfdcr(rn) ({unsigned int rval; \
943 asm volatile("mfdcr %0," stringify(rn) \
944 : "=r" (rval)); rval;})
945 #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
946
947 #define mfmsr() ({unsigned int rval; \
948 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
949 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
950
951 #define mfspr(rn) ({unsigned int rval; \
952 asm volatile("mfspr %0," stringify(rn) \
953 : "=r" (rval)); rval;})
954 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
955
956 #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
957
958 /* Segment Registers */
959
960 #define SR0 0
961 #define SR1 1
962 #define SR2 2
963 #define SR3 3
964 #define SR4 4
965 #define SR5 5
966 #define SR6 6
967 #define SR7 7
968 #define SR8 8
969 #define SR9 9
970 #define SR10 10
971 #define SR11 11
972 #define SR12 12
973 #define SR13 13
974 #define SR14 14
975 #define SR15 15
976
977 #ifndef __ASSEMBLY__
978 #ifndef CONFIG_MACH_SPECIFIC
979 extern int _machine;
980 extern int have_of;
981 #endif /* CONFIG_MACH_SPECIFIC */
982
983 /* what kind of prep workstation we are */
984 extern int _prep_type;
985 /*
986 * This is used to identify the board type from a given PReP board
987 * vendor. Board revision is also made available.
988 */
989 extern unsigned char ucSystemType;
990 extern unsigned char ucBoardRev;
991 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
992
993 struct task_struct;
994 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
995 void release_thread(struct task_struct *);
996
997 /*
998 * Create a new kernel thread.
999 */
1000 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
1001
1002 /*
1003 * Bus types
1004 */
1005 #define EISA_bus 0
1006 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
1007 #define MCA_bus 0
1008 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
1009
1010 /* Lazy FPU handling on uni-processor */
1011 extern struct task_struct *last_task_used_math;
1012 extern struct task_struct *last_task_used_altivec;
1013
1014 /*
1015 * this is the minimum allowable io space due to the location
1016 * of the io areas on prep (first one at 0x80000000) but
1017 * as soon as I get around to remapping the io areas with the BATs
1018 * to match the mac we can raise this. -- Cort
1019 */
1020 #define TASK_SIZE (0x80000000UL)
1021
1022 /* This decides where the kernel will search for a free chunk of vm
1023 * space during mmap's.
1024 */
1025 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
1026
1027 typedef struct {
1028 unsigned long seg;
1029 } mm_segment_t;
1030
1031 struct thread_struct {
1032 unsigned long ksp; /* Kernel stack pointer */
1033 unsigned long wchan; /* Event task is sleeping on */
1034 struct pt_regs *regs; /* Pointer to saved register state */
1035 mm_segment_t fs; /* for get_fs() validation */
1036 void *pgdir; /* root of page-table tree */
1037 signed long last_syscall;
1038 double fpr[32]; /* Complete floating point set */
1039 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
1040 unsigned long fpscr; /* Floating point status */
1041 #ifdef CONFIG_ALTIVEC
1042 vector128 vr[32]; /* Complete AltiVec set */
1043 vector128 vscr; /* AltiVec status */
1044 unsigned long vrsave;
1045 #endif /* CONFIG_ALTIVEC */
1046 };
1047
1048 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
1049
1050 #define INIT_THREAD { \
1051 INIT_SP, /* ksp */ \
1052 0, /* wchan */ \
1053 (struct pt_regs *)INIT_SP - 1, /* regs */ \
1054 KERNEL_DS, /*fs*/ \
1055 swapper_pg_dir, /* pgdir */ \
1056 0, /* last_syscall */ \
1057 {0}, 0, 0 \
1058 }
1059
1060 /*
1061 * Note: the vm_start and vm_end fields here should *not*
1062 * be in kernel space. (Could vm_end == vm_start perhaps?)
1063 */
1064 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
1065 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
1066 1, NULL, NULL }
1067
1068 /*
1069 * Return saved PC of a blocked thread. For now, this is the "user" PC
1070 */
1071 static inline unsigned long thread_saved_pc(struct thread_struct *t)
1072 {
1073 return (t->regs) ? t->regs->nip : 0;
1074 }
1075
1076 #define copy_segments(tsk, mm) do { } while (0)
1077 #define release_segments(mm) do { } while (0)
1078 #define forget_segments() do { } while (0)
1079
1080 unsigned long get_wchan(struct task_struct *p);
1081
1082 #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
1083 #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
1084
1085 /*
1086 * NOTE! The task struct and the stack go together
1087 */
1088 #define THREAD_SIZE (2*PAGE_SIZE)
1089 #define alloc_task_struct() \
1090 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
1091 #define free_task_struct(p) free_pages((unsigned long)(p),1)
1092 #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
1093
1094 /* in process.c - for early bootup debug -- Cort */
1095 int ll_printk(const char *, ...);
1096 void ll_puts(const char *);
1097
1098 #define init_task (init_task_union.task)
1099 #define init_stack (init_task_union.stack)
1100
1101 /* In misc.c */
1102 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
1103
1104 #endif /* ndef ASSEMBLY*/
1105
1106 #ifdef CONFIG_MACH_SPECIFIC
1107 #if defined(CONFIG_8xx)
1108 #define _machine _MACH_8xx
1109 #define have_of 0
1110 #elif defined(CONFIG_OAK)
1111 #define _machine _MACH_oak
1112 #define have_of 0
1113 #elif defined(CONFIG_WALNUT)
1114 #define _machine _MACH_walnut
1115 #define have_of 0
1116 #elif defined(CONFIG_APUS)
1117 #define _machine _MACH_apus
1118 #define have_of 0
1119 #elif defined(CONFIG_GEMINI)
1120 #define _machine _MACH_gemini
1121 #define have_of 0
1122 #elif defined(CONFIG_8260)
1123 #define _machine _MACH_8260
1124 #define have_of 0
1125 #elif defined(CONFIG_SANDPOINT)
1126 #define _machine _MACH_sandpoint
1127 #elif defined(CONFIG_HIDDEN_DRAGON)
1128 #define _machine _MACH_hidden_dragon
1129 #define have_of 0
1130 #else
1131 #error "Machine not defined correctly"
1132 #endif
1133 #endif /* CONFIG_MACH_SPECIFIC */
1134
1135 #endif /* __ASM_PPC_PROCESSOR_H */
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