include/asm-sparc/processor.h

   1 /* SPARC Processor specifics
   2  * taken from the SPARC port of Linux (ptrace.h).
   3  *
   4  * (C) Copyright 2007
   5  * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #ifndef __ASM_SPARC_PROCESSOR_H
  25 #define __ASM_SPARC_PROCESSOR_H
  26
  27 #include <asm/arch/asi.h>
  28
  29 /* Includeprocessor specific header file here */
  30 #error Unknown SPARC Processor
  31
  32 #ifndef __ASSEMBLY__
  33
  34 /* flush data cache */
  35 static __inline__ void sparc_dcache_flush_all(void)
  36 {
  37       __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
  38 }
  39
  40 /* flush instruction cache */
  41 static __inline__ void sparc_icache_flush_all(void)
  42 {
  43       __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH):"memory");
  44 }
  45
  46 /* do a cache miss load */
  47 static __inline__ unsigned long long sparc_load_reg_cachemiss_qword(unsigned
  48                                                                     long paddr)
  49 {
  50         unsigned long long retval;
  51         __asm__ __volatile__("ldda [%1] %2, %0\n\t":
  52                              "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
  53         return retval;
  54 }
  55
  56 static __inline__ unsigned long sparc_load_reg_cachemiss(unsigned long paddr)
  57 {
  58         unsigned long retval;
  59         __asm__ __volatile__("lda [%1] %2, %0\n\t":
  60                              "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
  61         return retval;
  62 }
  63
  64 static __inline__ unsigned short sparc_load_reg_cachemiss_word(unsigned long
  65                                                                paddr)
  66 {
  67         unsigned short retval;
  68         __asm__ __volatile__("lduha [%1] %2, %0\n\t":
  69                              "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
  70         return retval;
  71 }
  72
  73 static __inline__ unsigned char sparc_load_reg_cachemiss_byte(unsigned long
  74                                                               paddr)
  75 {
  76         unsigned char retval;
  77         __asm__ __volatile__("lduba [%1] %2, %0\n\t":
  78                              "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
  79         return retval;
  80 }
  81
  82 /* do a physical address bypass write, i.e. for 0x80000000 */
  83 static __inline__ void sparc_store_reg_bypass(unsigned long paddr,
  84                                               unsigned long value)
  85 {
  86         __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(value), "r"(paddr),
  87                              "i"(ASI_BYPASS):"memory");
  88 }
  89
  90 static __inline__ unsigned long sparc_load_reg_bypass(unsigned long paddr)
  91 {
  92         unsigned long retval;
  93         __asm__ __volatile__("lda [%1] %2, %0\n\t":
  94                              "=r"(retval):"r"(paddr), "i"(ASI_BYPASS));
  95         return retval;
  96 }
  97
  98 /* Macros for bypassing cache when reading */
  99 #define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address))
 100 #define SPARC_NOCACHE_READ(address)       sparc_load_reg_cachemiss((unsigned int)(address))
 101 #define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address))
 102 #define SPARC_NOCACHE_READ_BYTE(address)  sparc_load_reg_cachemiss_byte((unsigned int)(address))
 103
 104 #define SPARC_BYPASS_READ(address)        sparc_load_reg_bypass((unsigned int)(address))
 105 #define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value))
 106
 107 #endif
 108
 109 #endif                          /* __ASM_SPARC_PROCESSOR_H */