include/atmel_hlcdc.h

   1 /*
   2  *  Header file for AT91/AT32 MULTI LAYER LCD Controller
   3  *
   4  *  Data structure and register user interface
   5  *
   6  *  Copyright (C) 2012 Atmel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 #ifndef __ATMEL_HLCDC_H__
  23 #define __ATMEL_HLCDC_H__
  24
  25 /* Atmel multi layer lcdc hardware registers */
  26 struct atmel_hlcd_regs {
  27         u32     lcdc_lcdcfg0;
  28         u32     lcdc_lcdcfg1;
  29         u32     lcdc_lcdcfg2;
  30         u32     lcdc_lcdcfg3;
  31         u32     lcdc_lcdcfg4;
  32         u32     lcdc_lcdcfg5;
  33         u32     lcdc_lcdcfg6;
  34         u32     res1;
  35         u32     lcdc_lcden;
  36         u32     lcdc_lcddis;
  37         u32     lcdc_lcdsr;
  38         u32     res2;
  39         u32     lcdc_lcdidr;
  40         u32     res3[3];
  41         u32     lcdc_basecher;
  42         u32     res4[3];
  43         u32     lcdc_baseidr;
  44         u32     res5[3];
  45         u32     lcdc_baseaddr;
  46         u32     lcdc_basectrl;
  47         u32     lcdc_basenext;
  48         u32     lcdc_basecfg0;
  49         u32     lcdc_basecfg1;
  50         u32     lcdc_basecfg2;
  51         u32     lcdc_basecfg3;
  52         u32     lcdc_basecfg4;
  53 };
  54
  55 #define LCDC_LCDCFG0_CLKPOL     (0x1 << 0)
  56 #define LCDC_LCDCFG0_CLKSEL     (0x1 << 2)
  57 #define LCDC_LCDCFG0_CLKPWMSEL  (0x1 << 3)
  58 #define LCDC_LCDCFG0_CGDISBASE  (0x1 << 8)
  59 #define LCDC_LCDCFG0_CGDISOVR1  (0x1 << 9)
  60 #define LCDC_LCDCFG0_CGDISHEO   (0x1 << 11)
  61 #define LCDC_LCDCFG0_CGDISHCR   (0x1 << 12)
  62 #define LCDC_LCDCFG0_CLKDIV_Pos 16
  63 #define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos)
  64 #define LCDC_LCDCFG0_CLKDIV(value) \
  65         ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
  66
  67 #define LCDC_LCDCFG1_HSPW_Pos   0
  68 #define LCDC_LCDCFG1_HSPW_Msk   (0x3f << LCDC_LCDCFG1_HSPW_Pos)
  69 #define LCDC_LCDCFG1_HSPW(value) \
  70         ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
  71 #define LCDC_LCDCFG1_VSPW_Pos   16
  72 #define LCDC_LCDCFG1_VSPW_Msk   (0x3f << LCDC_LCDCFG1_VSPW_Pos)
  73 #define LCDC_LCDCFG1_VSPW(value) \
  74         ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
  75
  76 #define LCDC_LCDCFG2_VFPW_Pos   0
  77 #define LCDC_LCDCFG2_VFPW_Msk   (0x3f << LCDC_LCDCFG2_VFPW_Pos)
  78 #define LCDC_LCDCFG2_VFPW(value) \
  79         ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
  80 #define LCDC_LCDCFG2_VBPW_Pos   16
  81 #define LCDC_LCDCFG2_VBPW_Msk   (0x3f << LCDC_LCDCFG2_VBPW_Pos)
  82 #define LCDC_LCDCFG2_VBPW(value) \
  83         ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
  84
  85 #define LCDC_LCDCFG3_HFPW_Pos   0
  86 #define LCDC_LCDCFG3_HFPW_Msk   (0xff << LCDC_LCDCFG3_HFPW_Pos)
  87 #define LCDC_LCDCFG3_HFPW(value) \
  88         ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
  89 #define LCDC_LCDCFG3_HBPW_Pos   16
  90 #define LCDC_LCDCFG3_HBPW_Msk   (0xff << LCDC_LCDCFG3_HBPW_Pos)
  91 #define LCDC_LCDCFG3_HBPW(value) \
  92         ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
  93
  94 #define LCDC_LCDCFG4_PPL_Pos    0
  95 #define LCDC_LCDCFG4_PPL_Msk    (0x7ff << LCDC_LCDCFG4_PPL_Pos)
  96 #define LCDC_LCDCFG4_PPL(value) \
  97         ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
  98 #define LCDC_LCDCFG4_RPF_Pos    16
  99 #define LCDC_LCDCFG4_RPF_Msk    (0x7ff << LCDC_LCDCFG4_RPF_Pos)
 100 #define LCDC_LCDCFG4_RPF(value) \
 101         ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
 102
 103 #define LCDC_LCDCFG5_HSPOL      (0x1 << 0)
 104 #define LCDC_LCDCFG5_VSPOL      (0x1 << 1)
 105 #define LCDC_LCDCFG5_VSPDLYS    (0x1 << 2)
 106 #define LCDC_LCDCFG5_VSPDLYE    (0x1 << 3)
 107 #define LCDC_LCDCFG5_DISPPOL    (0x1 << 4)
 108 #define LCDC_LCDCFG5_SERIAL     (0x1 << 5)
 109 #define LCDC_LCDCFG5_DITHER     (0x1 << 6)
 110 #define LCDC_LCDCFG5_DISPDLY    (0x1 << 7)
 111 #define LCDC_LCDCFG5_MODE_Pos   8
 112 #define LCDC_LCDCFG5_MODE_Msk   (0x3 << LCDC_LCDCFG5_MODE_Pos)
 113 #define LCDC_LCDCFG5_MODE_OUTPUT_12BPP  (0x0 << 8)
 114 #define LCDC_LCDCFG5_MODE_OUTPUT_16BPP  (0x1 << 8)
 115 #define LCDC_LCDCFG5_MODE_OUTPUT_18BPP  (0x2 << 8)
 116 #define LCDC_LCDCFG5_MODE_OUTPUT_24BPP  (0x3 << 8)
 117 #define LCDC_LCDCFG5_VSPSU              (0x1 << 12)
 118 #define LCDC_LCDCFG5_VSPHO              (0x1 << 13)
 119 #define LCDC_LCDCFG5_GUARDTIME_Pos      16
 120 #define LCDC_LCDCFG5_GUARDTIME_Msk      (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
 121 #define LCDC_LCDCFG5_GUARDTIME(value) \
 122         ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
 123
 124 #define LCDC_LCDCFG6_PWMPS_Pos          0
 125 #define LCDC_LCDCFG6_PWMPS_Msk          (0x7 << LCDC_LCDCFG6_PWMPS_Pos)
 126 #define LCDC_LCDCFG6_PWMPS(value) \
 127         ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
 128 #define LCDC_LCDCFG6_PWMPOL             (0x1 << 4)
 129 #define LCDC_LCDCFG6_PWMCVAL_Pos        8
 130 #define LCDC_LCDCFG6_PWMCVAL_Msk        (0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
 131 #define LCDC_LCDCFG6_PWMCVAL(value) \
 132         ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
 133
 134 #define LCDC_LCDEN_CLKEN        (0x1 << 0)
 135 #define LCDC_LCDEN_SYNCEN       (0x1 << 1)
 136 #define LCDC_LCDEN_DISPEN       (0x1 << 2)
 137 #define LCDC_LCDEN_PWMEN        (0x1 << 3)
 138
 139 #define LCDC_LCDDIS_CLKDIS      (0x1 << 0)
 140 #define LCDC_LCDDIS_SYNCDIS     (0x1 << 1)
 141 #define LCDC_LCDDIS_DISPDIS     (0x1 << 2)
 142 #define LCDC_LCDDIS_PWMDIS      (0x1 << 3)
 143 #define LCDC_LCDDIS_CLKRST      (0x1 << 8)
 144 #define LCDC_LCDDIS_SYNCRST     (0x1 << 9)
 145 #define LCDC_LCDDIS_DISPRST     (0x1 << 10)
 146 #define LCDC_LCDDIS_PWMRST      (0x1 << 11)
 147
 148 #define LCDC_LCDSR_CLKSTS       (0x1 << 0)
 149 #define LCDC_LCDSR_LCDSTS       (0x1 << 1)
 150 #define LCDC_LCDSR_DISPSTS      (0x1 << 2)
 151 #define LCDC_LCDSR_PWMSTS       (0x1 << 3)
 152 #define LCDC_LCDSR_SIPSTS       (0x1 << 4)
 153
 154 #define LCDC_LCDIDR_SOFID       (0x1 << 0)
 155 #define LCDC_LCDIDR_DISID       (0x1 << 1)
 156 #define LCDC_LCDIDR_DISPID      (0x1 << 2)
 157 #define LCDC_LCDIDR_FIFOERRID   (0x1 << 4)
 158 #define LCDC_LCDIDR_BASEID      (0x1 << 8)
 159 #define LCDC_LCDIDR_OVR1ID      (0x1 << 9)
 160 #define LCDC_LCDIDR_HEOID       (0x1 << 11)
 161 #define LCDC_LCDIDR_HCRID       (0x1 << 12)
 162
 163 #define LCDC_BASECHER_CHEN      (0x1 << 0)
 164 #define LCDC_BASECHER_UPDATEEN  (0x1 << 1)
 165 #define LCDC_BASECHER_A2QEN     (0x1 << 2)
 166
 167 #define LCDC_BASEIDR_DMA        (0x1 << 2)
 168 #define LCDC_BASEIDR_DSCR       (0x1 << 3)
 169 #define LCDC_BASEIDR_ADD        (0x1 << 4)
 170 #define LCDC_BASEIDR_DONE       (0x1 << 5)
 171 #define LCDC_BASEIDR_OVR        (0x1 << 6)
 172
 173 #define LCDC_BASECTRL_DFETCH    (0x1 << 0)
 174 #define LCDC_BASECTRL_LFETCH    (0x1 << 1)
 175 #define LCDC_BASECTRL_DMAIEN    (0x1 << 2)
 176 #define LCDC_BASECTRL_DSCRIEN   (0x1 << 3)
 177 #define LCDC_BASECTRL_ADDIEN    (0x1 << 4)
 178 #define LCDC_BASECTRL_DONEIEN   (0x1 << 5)
 179
 180 #define LCDC_BASECFG0_BLEN_Pos          4
 181 #define LCDC_BASECFG0_BLEN_AHB_SINGLE   (0x0 << 4)
 182 #define LCDC_BASECFG0_BLEN_AHB_INCR4    (0x1 << 4)
 183 #define LCDC_BASECFG0_BLEN_AHB_INCR8    (0x2 << 4)
 184 #define LCDC_BASECFG0_BLEN_AHB_INCR16   (0x3 << 4)
 185 #define LCDC_BASECFG0_DLBO              (0x1 << 8)
 186
 187 #define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444             (0x0 << 4)
 188 #define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444           (0x1 << 4)
 189 #define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444           (0x2 << 4)
 190 #define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565             (0x3 << 4)
 191 #define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555           (0x4 << 4)
 192 #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666             (0x5 << 4)
 193 #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED      (0x6 << 4)
 194 #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666           (0x7 << 4)
 195 #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED         (0x8 << 4)
 196 #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888             (0x9 << 4)
 197 #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED      (0xA << 4)
 198 #define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888           (0xB << 4)
 199 #define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888           (0xC << 4)
 200 #define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888           (0xD << 4)
 201
 202 #define LCDC_BASECFG2_XSTRIDE_Pos 0
 203 #define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
 204 #define LCDC_BASECFG2_XSTRIDE(value) \
 205         ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
 206
 207 #define LCDC_BASECFG3_BDEF_Pos  0
 208 #define LCDC_BASECFG3_BDEF_Msk  (0xff << LCDC_BASECFG3_BDEF_Pos)
 209 #define LCDC_BASECFG3_BDEF(value) \
 210         ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
 211 #define LCDC_BASECFG3_GDEF_Pos  8
 212 #define LCDC_BASECFG3_GDEF_Msk  (0xff << LCDC_BASECFG3_GDEF_Pos)
 213 #define LCDC_BASECFG3_GDEF(value) \
 214         ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
 215 #define LCDC_BASECFG3_RDEF_Pos  16
 216 #define LCDC_BASECFG3_RDEF_Msk  (0xff << LCDC_BASECFG3_RDEF_Pos)
 217 #define LCDC_BASECFG3_RDEF(value) \
 218         ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
 219
 220 #define LCDC_BASECFG4_DMA       (0x1 << 8)
 221 #define LCDC_BASECFG4_REP       (0x1 << 9)
 222
 223 struct lcd_dma_desc {
 224         u32     address;
 225         u32     control;
 226         u32     next;
 227 };
 228
 229 #define ATMEL_LCDC_LUT(n)       (0x0400 + ((n)*4))
 230
 231 #endif /* __ATMEL_HLCDC_H__ */