]>
git.ipfire.org Git - u-boot.git/blob - include/bedbug/tables.h
6 /* This is only included by common/bedbug.c, and depends on the following
7 * files to already be included
14 struct operand operands
[] = {
15 /*Field Name Bits Shift Hint Position */
16 /*----- ------ ----- ----- ---- ------------ */
17 { O_AA
, "O_AA", 1, 1, OH_SILENT
}, /* 30 */
18 { O_BD
, "O_BD", 14, 2, OH_ADDR
}, /* 16-29 */
19 { O_BI
, "O_BI", 5, 16, 0 }, /* 11-15 */
20 { O_BO
, "O_BO", 5, 21, 0 }, /* 6-10 */
21 { O_crbD
, "O_crbD", 5, 21, 0 }, /* 6-10 */
22 { O_crbA
, "O_crbA", 5, 16, 0 }, /* 11-15 */
23 { O_crbB
, "O_crbB", 5, 11, 0 }, /* 16-20 */
24 { O_CRM
, "O_CRM", 8, 12, 0 }, /* 12-19 */
25 { O_d
, "O_d", 15, 0, OH_OFFSET
}, /* 16-31 */
26 { O_frC
, "O_frC", 5, 6, 0 }, /* 21-25 */
27 { O_frD
, "O_frD", 5, 21, 0 }, /* 6-10 */
28 { O_frS
, "O_frS", 5, 21, 0 }, /* 6-10 */
29 { O_IMM
, "O_IMM", 4, 12, 0 }, /* 16-19 */
30 { O_LI
, "O_LI", 24, 2, OH_ADDR
}, /* 6-29 */
31 { O_LK
, "O_LK", 1, 0, OH_SILENT
}, /* 31 */
32 { O_MB
, "O_MB", 5, 6, 0 }, /* 21-25 */
33 { O_ME
, "O_ME", 5, 1, 0 }, /* 26-30 */
34 { O_NB
, "O_NB", 5, 11, 0 }, /* 16-20 */
35 { O_OE
, "O_OE", 1, 10, OH_SILENT
}, /* 21 */
36 { O_rA
, "O_rA", 5, 16, OH_REG
}, /* 11-15 */
37 { O_rB
, "O_rB", 5, 11, OH_REG
}, /* 16-20 */
38 { O_Rc
, "O_Rc", 1, 0, OH_SILENT
}, /* 31 */
39 { O_rD
, "O_rD", 5, 21, OH_REG
}, /* 6-10 */
40 { O_rS
, "O_rS", 5, 21, OH_REG
}, /* 6-10 */
41 { O_SH
, "O_SH", 5, 11, 0 }, /* 16-20 */
42 { O_SIMM
, "O_SIMM", 16, 0, 0 }, /* 16-31 */
43 { O_SR
, "O_SR", 4, 16, 0 }, /* 12-15 */
44 { O_TO
, "O_TO", 5, 21, 0 }, /* 6-10 */
45 { O_UIMM
, "O_UIMM", 16, 0, 0 }, /* 16-31 */
46 { O_crfD
, "O_crfD", 3, 23, 0 }, /* 6- 8 */
47 { O_crfS
, "O_crfS", 3, 18, 0 }, /* 11-13 */
48 { O_L
, "O_L", 1, 21, 0 }, /* 10 */
49 { O_spr
, "O_spr", 10, 11, OH_SPR
}, /* 11-20 */
50 { O_tbr
, "O_tbr", 10, 11, OH_TBR
}, /* 11-20 */
51 { O_cr2
, "O_cr2", 0, 0, OH_LITERAL
}, /* "cr2" */
54 const unsigned int n_operands
= sizeof(operands
) / sizeof(operands
[0]);
56 /* A note about the fields array in the opcodes structure:
57 The operands are listed in the order they appear in the output.
59 This table is arranged in numeric order of the opcode. Note that some
60 opcodes have defined bits in odd places so not all forms of a command
61 will be in the same place. This is done so that a binary search can be
62 done to find the opcodes. Note that table D.2 in the MPC860 User's
63 Manual "Instructions Sorted by Opcode" does not account for these
66 struct opcode opcodes
[] = {
67 { D_OPCODE(3), D_MASK
, {O_TO
, O_rA
, O_SIMM
, 0},
69 { D_OPCODE(7), D_MASK
, {O_rD
, O_rA
, O_SIMM
, 0},
71 { D_OPCODE(8), D_MASK
, {O_rD
, O_rA
, O_SIMM
, 0},
73 { D_OPCODE(10), D_MASK
, {O_crfD
, O_L
, O_rA
, O_UIMM
, 0},
75 { D_OPCODE(11), D_MASK
, {O_crfD
, O_L
, O_rA
, O_SIMM
, 0},
77 { D_OPCODE(12), D_MASK
, {O_rD
, O_rA
, O_SIMM
, 0},
79 { D_OPCODE(13), D_MASK
, {O_rD
, O_rA
, O_SIMM
, 0},
81 { D_OPCODE(14), D_MASK
, {O_rD
, O_rA
, O_SIMM
, 0},
82 0, "addi", H_RA0_IS_0
},
83 { D_OPCODE(15), D_MASK
, {O_rD
, O_rA
, O_SIMM
, 0},
84 0, "addis", H_RA0_IS_0
|H_IMM_HIGH
},
85 { B_OPCODE(16,0,0), B_MASK
, {O_BO
, O_BI
, O_BD
, O_AA
, O_LK
, 0},
86 handle_bc
, "bc", H_RELATIVE
},
87 { B_OPCODE(16,0,1), B_MASK
, {O_BO
, O_BI
, O_BD
, O_AA
, O_LK
, 0},
88 0, "bcl", H_RELATIVE
},
89 { B_OPCODE(16,1,0), B_MASK
, {O_BO
, O_BI
, O_BD
, O_AA
, O_LK
, 0},
91 { B_OPCODE(16,1,1), B_MASK
, {O_BO
, O_BI
, O_BD
, O_AA
, O_LK
, 0},
93 { SC_OPCODE(17), SC_MASK
, {0},
95 { I_OPCODE(18,0,0), I_MASK
, {O_LI
, O_AA
, O_LK
, 0},
97 { I_OPCODE(18,0,1), I_MASK
, {O_LI
, O_AA
, O_LK
, 0},
98 0, "bl", H_RELATIVE
},
99 { I_OPCODE(18,1,0), I_MASK
, {O_LI
, O_AA
, O_LK
, 0},
101 { I_OPCODE(18,1,1), I_MASK
, {O_LI
, O_AA
, O_LK
, 0},
103 { XL_OPCODE(19,0,0), XL_MASK
, {O_crfD
, O_crfS
},
105 { XL_OPCODE(19,16,0), XL_MASK
, {O_BO
, O_BI
, O_LK
, 0},
107 { XL_OPCODE(19,16,1), XL_MASK
, {O_BO
, O_BI
, O_LK
, 0},
109 { XL_OPCODE(19,33,0), XL_MASK
, {O_crbD
, O_crbA
, O_crbB
, 0},
111 { XL_OPCODE(19,50,0), XL_MASK
, {0},
113 { XL_OPCODE(19,129,0), XL_MASK
, {O_crbD
, O_crbA
, O_crbB
, 0},
115 { XL_OPCODE(19,150,0), XL_MASK
, {0},
117 { XL_OPCODE(19,193,0), XL_MASK
, {O_crbD
, O_crbA
, O_crbB
, 0},
119 { XL_OPCODE(19,225,0), XL_MASK
, {O_crbD
, O_crbA
, O_crbB
, 0},
121 { XL_OPCODE(19,257,0), XL_MASK
, {O_crbD
, O_crbA
, O_crbB
, 0},
123 { XL_OPCODE(19,289,0), XL_MASK
, {O_crbD
, O_crbA
, O_crbB
, 0},
125 { XL_OPCODE(19,417,0), XL_MASK
, {O_crbD
, O_crbA
, O_crbB
, 0},
127 { XL_OPCODE(19,449,0), XL_MASK
, {O_crbD
, O_crbA
, O_crbB
, 0},
129 { XL_OPCODE(19,528,0), XL_MASK
, {O_BO
, O_BI
, O_LK
, 0},
131 { XL_OPCODE(19,528,1), XL_MASK
, {O_BO
, O_BI
, O_LK
, 0},
133 { M_OPCODE(20,0), M_MASK
, {O_rA
, O_rS
, O_SH
, O_MB
, O_ME
, O_Rc
, 0},
135 { M_OPCODE(20,1), M_MASK
, {O_rA
, O_rS
, O_SH
, O_MB
, O_ME
, O_Rc
, 0},
137 { M_OPCODE(21,0), M_MASK
, {O_rA
, O_rS
, O_SH
, O_MB
, O_ME
, O_Rc
, 0},
139 { M_OPCODE(21,1), M_MASK
, {O_rA
, O_rS
, O_SH
, O_MB
, O_ME
, O_Rc
, 0},
141 { M_OPCODE(23,0), M_MASK
, {O_rA
, O_rS
, O_rB
, O_MB
, O_ME
, O_Rc
, 0},
143 { M_OPCODE(23,1), M_MASK
, {O_rA
, O_rS
, O_rB
, O_MB
, O_ME
, O_Rc
, 0},
145 { D_OPCODE(24), D_MASK
, {O_rA
, O_rS
, O_UIMM
, 0},
147 { D_OPCODE(25), D_MASK
, {O_rA
, O_rS
, O_UIMM
, 0},
148 0, "oris", H_IMM_HIGH
},
149 { D_OPCODE(26), D_MASK
, {O_rA
, O_rS
, O_UIMM
, 0},
151 { D_OPCODE(27), D_MASK
, {O_rA
, O_rS
, O_UIMM
, 0},
152 0, "xoris", H_IMM_HIGH
},
153 { D_OPCODE(28), D_MASK
, {O_rA
, O_rS
, O_UIMM
, 0},
155 { D_OPCODE(29), D_MASK
, {O_rA
, O_rS
, O_UIMM
, 0},
156 0, "andis.", H_IMM_HIGH
},
157 { X_OPCODE(31,0,0), X_MASK
, {O_crfD
, O_L
, O_rA
, O_rB
, 0},
159 { X_OPCODE(31,4,0), X_MASK
, {O_TO
, O_rA
, O_rB
, 0},
161 { XO_OPCODE(31,8,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
163 { XO_OPCODE(31,8,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
165 { XO_OPCODE(31,10,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
167 { XO_OPCODE(31,10,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
169 { XO_OPCODE(31,11,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_Rc
, 0},
171 { XO_OPCODE(31,11,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_Rc
, 0},
173 { X_OPCODE(31,19,0), X_MASK
, {O_rD
, 0},
175 { X_OPCODE(31,20,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
176 0, "lwarx", H_RA0_IS_0
},
177 { X_OPCODE(31,23,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
178 0, "lwzx", H_RA0_IS_0
},
179 { X_OPCODE(31,24,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
181 { X_OPCODE(31,24,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
183 { X_OPCODE(31,26,0), X_MASK
, {O_rA
, O_rS
, O_Rc
, 0 },
185 { X_OPCODE(31,26,1), X_MASK
, {O_rA
, O_rS
, O_Rc
, 0},
187 { X_OPCODE(31,28,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
189 { X_OPCODE(31,28,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
191 { X_OPCODE(31,32,0), X_MASK
, {O_crfD
, O_L
, O_rA
, O_rB
, 0},
193 { XO_OPCODE(31,40,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
195 { XO_OPCODE(31,40,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
197 { X_OPCODE(31,54,0), X_MASK
, {O_rA
, O_rB
, 0},
198 0, "dcbst", H_RA0_IS_0
},
199 { X_OPCODE(31,55,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
201 { X_OPCODE(31,60,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
203 { X_OPCODE(31,60,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
205 { XO_OPCODE(31,75,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_Rc
, 0},
207 { XO_OPCODE(31,75,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_Rc
, 0},
209 { X_OPCODE(31,83,0), X_MASK
, {O_rD
, 0},
211 { X_OPCODE(31,86,0), X_MASK
, {O_rA
, O_rB
, 0},
212 0, "dcbf", H_RA0_IS_0
},
213 { X_OPCODE(31,87,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
214 0, "lbzx", H_RA0_IS_0
},
215 { XO_OPCODE(31,104,0,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
217 { XO_OPCODE(31,104,0,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
219 { X_OPCODE(31,119,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
221 { X_OPCODE(31,124,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
223 { X_OPCODE(31,124,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
225 { XO_OPCODE(31,136,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
227 { XO_OPCODE(31,136,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
229 { XO_OPCODE(31,138,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
231 { XO_OPCODE(31,138,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
233 { XFX_OPCODE(31,144,0), XFX_MASK
, {O_CRM
, O_rS
, 0},
235 { X_OPCODE(31,146,0), X_MASK
, {O_rS
, 0},
237 { X_OPCODE(31,150,1), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
239 { X_OPCODE(31,151,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
241 { X_OPCODE(31,183,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
243 { XO_OPCODE(31,200,0,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
245 { XO_OPCODE(31,200,0,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
247 { XO_OPCODE(31,202,0,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
249 { XO_OPCODE(31,202,0,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
251 { X_OPCODE(31,210,0), X_MASK
, {O_SR
, O_rS
, 0},
253 { X_OPCODE(31,215,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
254 0, "stbx", H_RA0_IS_0
},
255 { XO_OPCODE(31,232,0,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
257 { XO_OPCODE(31,232,0,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
259 { XO_OPCODE(31,234,0,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
261 { XO_OPCODE(31,234,0,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
263 { XO_OPCODE(31,235,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
265 { XO_OPCODE(31,235,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
267 { X_OPCODE(31,242,0), X_MASK
, {O_rS
, O_rB
, 0},
269 { X_OPCODE(31,246,0), X_MASK
, {O_rA
, O_rB
, 0},
270 0, "dcbtst", H_RA0_IS_0
},
271 { X_OPCODE(31,247,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
273 { XO_OPCODE(31,266,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
275 { XO_OPCODE(31,266,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
277 { X_OPCODE(31,278,0), X_MASK
, {O_rA
, O_rB
, 0},
278 0, "dcbt", H_RA0_IS_0
},
279 { X_OPCODE(31,279,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
280 0, "lhzx", H_RA0_IS_0
},
281 { X_OPCODE(31,284,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
283 { X_OPCODE(31,284,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
285 { X_OPCODE(31,306,0), X_MASK
, {O_rB
, 0},
287 { X_OPCODE(31,310,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
288 0, "eciwx", H_RA0_IS_0
},
289 { X_OPCODE(31,311,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
291 { X_OPCODE(31,316,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
293 { X_OPCODE(31,316,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
295 { XFX_OPCODE(31,339,0), XFX_MASK
, {O_rD
, O_spr
, 0},
297 { X_OPCODE(31,343,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
298 0, "lhax", H_RA0_IS_0
},
299 { X_OPCODE(31,370,0), X_MASK
, {0},
301 { XFX_OPCODE(31,371,0), XFX_MASK
, {O_rD
, O_tbr
, 0},
303 { X_OPCODE(31,375,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
305 { X_OPCODE(31,407,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
306 0, "sthx", H_RA0_IS_0
},
307 { X_OPCODE(31,412,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
309 { X_OPCODE(31,412,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
311 { X_OPCODE(31,438,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
312 0, "ecowx", H_RA0_IS_0
},
313 { X_OPCODE(31,439,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
315 { X_OPCODE(31,444,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
317 { X_OPCODE(31,444,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
319 { XO_OPCODE(31,459,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
321 { XO_OPCODE(31,459,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
323 { XFX_OPCODE(31,467,0), XFX_MASK
, {O_spr
, O_rS
, 0},
325 { X_OPCODE(31,470,0), X_MASK
, {O_rA
, O_rB
, 0},
326 0, "dcbi", H_RA0_IS_0
},
327 { X_OPCODE(31,476,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
329 { X_OPCODE(31,476,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
,0},
331 { XO_OPCODE(31,491,0,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
333 { XO_OPCODE(31,491,0,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
335 { X_OPCODE(31,512,0), X_MASK
, {O_crfD
, 0},
337 { XO_OPCODE(31,8,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
339 { XO_OPCODE(31,8,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
341 { XO_OPCODE(31,10,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
343 { XO_OPCODE(31,10,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
345 { X_OPCODE(31,533,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
346 0, "lswx", H_RA0_IS_0
},
347 { X_OPCODE(31,534,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
348 0, "lwbrx", H_RA0_IS_0
},
349 { X_OPCODE(31,536,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
351 { X_OPCODE(31,536,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
353 { XO_OPCODE(31,40,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
355 { XO_OPCODE(31,40,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
357 { X_OPCODE(31,566,0), X_MASK
, {0},
359 { X_OPCODE(31,595,0), X_MASK
, {O_rD
, O_SR
, 0},
361 { X_OPCODE(31,597,0), X_MASK
, {O_rD
, O_rA
, O_NB
, 0},
362 0, "lswi", H_RA0_IS_0
},
363 { X_OPCODE(31,598,0), X_MASK
, {0},
365 { XO_OPCODE(31,104,1,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
367 { XO_OPCODE(31,104,1,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
369 { XO_OPCODE(31,136,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
371 { XO_OPCODE(31,136,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
373 { XO_OPCODE(31,138,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
375 { XO_OPCODE(31,138,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
377 { X_OPCODE(31,659,0), X_MASK
, {O_rD
, O_rB
, 0},
379 { X_OPCODE(31,661,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
380 0, "stswx", H_RA0_IS_0
},
381 { X_OPCODE(31,662,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
382 0, "stwbrx", H_RA0_IS_0
},
383 { XO_OPCODE(31,200,1,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
385 { XO_OPCODE(31,200,1,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
387 { XO_OPCODE(31,202,1,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
389 { XO_OPCODE(31,202,1,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
391 { X_OPCODE(31,725,0), X_MASK
, {O_rS
, O_rA
, O_NB
, 0},
392 0, "stswi", H_RA0_IS_0
},
393 { XO_OPCODE(31,232,1,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
395 { XO_OPCODE(31,232,1,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
397 { XO_OPCODE(31,234,1,0), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
399 { XO_OPCODE(31,234,1,1), XO_MASK
, {O_rD
, O_rA
, O_OE
, O_Rc
, 0},
401 { XO_OPCODE(31,235,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
403 { XO_OPCODE(31,235,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
405 { XO_OPCODE(31,266,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
407 { XO_OPCODE(31,266,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
409 { X_OPCODE(31,790,0), X_MASK
, {O_rD
, O_rA
, O_rB
, 0},
410 0, "lhbrx", H_RA0_IS_0
},
411 { X_OPCODE(31,792,0), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
413 { X_OPCODE(31,792,1), X_MASK
, {O_rA
, O_rS
, O_rB
, O_Rc
, 0},
415 { X_OPCODE(31,824,0), X_MASK
, {O_rA
, O_rS
, O_SH
, O_Rc
, 0},
417 { X_OPCODE(31,824,1), X_MASK
, {O_rA
, O_rS
, O_SH
, O_Rc
, 0},
419 { X_OPCODE(31,854,0), X_MASK
, {0},
421 { X_OPCODE(31,918,0), X_MASK
, {O_rS
, O_rA
, O_rB
, 0},
422 0, "sthbrx", H_RA0_IS_0
},
423 { X_OPCODE(31,922,0), X_MASK
, {O_rA
, O_rS
, O_Rc
, 0},
425 { X_OPCODE(31,922,1), X_MASK
, {O_rA
, O_rS
, O_Rc
, 0},
427 { X_OPCODE(31,954,0), X_MASK
, {O_rA
, O_rS
, O_Rc
, 0},
429 { X_OPCODE(31,954,1), X_MASK
, {O_rA
, O_rS
, O_Rc
, 0},
431 { XO_OPCODE(31,459,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
433 { XO_OPCODE(31,459,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
435 { X_OPCODE(31,978,0), X_MASK
, {O_rB
, 0},
437 { X_OPCODE(31,982,0), X_MASK
, {O_rA
, O_rB
, 0},
438 0, "icbi", H_RA0_IS_0
},
439 { XO_OPCODE(31,491,1,0), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
441 { XO_OPCODE(31,491,1,1), XO_MASK
, {O_rD
, O_rA
, O_rB
, O_OE
, O_Rc
, 0},
443 { X_OPCODE(31,1010,0), X_MASK
, {O_rB
, 0},
445 { X_OPCODE(31,1014,0), X_MASK
, {O_rA
, O_rB
, 0},
446 0, "dcbz", H_RA0_IS_0
},
447 { D_OPCODE(32), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
448 0, "lwz", H_RA0_IS_0
},
449 { D_OPCODE(33), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
451 { D_OPCODE(34), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
452 0, "lbz", H_RA0_IS_0
},
453 { D_OPCODE(35), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
455 { D_OPCODE(36), D_MASK
, {O_rS
, O_d
, O_rA
, 0},
456 0, "stw", H_RA0_IS_0
},
457 { D_OPCODE(37), D_MASK
, {O_rS
, O_d
, O_rA
, 0},
459 { D_OPCODE(38), D_MASK
, {O_rS
, O_d
, O_rA
, 0},
460 0, "stb", H_RA0_IS_0
},
461 { D_OPCODE(39), D_MASK
, {O_rS
, O_d
, O_rA
, 0},
463 { D_OPCODE(40), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
464 0, "lhz", H_RA0_IS_0
},
465 { D_OPCODE(41), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
467 { D_OPCODE(42), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
468 0, "lha", H_RA0_IS_0
},
469 { D_OPCODE(43), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
471 { D_OPCODE(44), D_MASK
, {O_rS
, O_d
, O_rA
, 0},
472 0, "sth", H_RA0_IS_0
},
473 { D_OPCODE(45), D_MASK
, {O_rS
, O_d
, O_rA
, 0},
475 { D_OPCODE(46), D_MASK
, {O_rD
, O_d
, O_rA
, 0},
476 0, "lmw", H_RA0_IS_0
},
477 { D_OPCODE(47), D_MASK
, {O_rS
, O_d
, O_rA
, 0},
478 0, "stmw", H_RA0_IS_0
},
481 const unsigned int n_opcodes
= sizeof(opcodes
) / sizeof(opcodes
[0]);
483 struct spr_info spr_map
[] = {
487 { SPR_DSISR
, "DSISR" },
490 { SPR_SRR0
, "SRR0" },
491 { SPR_SRR1
, "SRR1" },
494 { SPR_CMPA
, "CMPA" },
495 { SPR_CMPB
, "CMPB" },
496 { SPR_CMPC
, "CMPC" },
497 { SPR_CMPD
, "CMPD" },
500 { SPR_COUNTA
, "COUNTA" },
501 { SPR_COUNTB
, "COUNTB" },
502 { SPR_CMPE
, "CMPE" },
503 { SPR_CMPF
, "CMPF" },
504 { SPR_CMPG
, "CMPG" },
505 { SPR_CMPH
, "CMPH" },
506 { SPR_LCTRL1
, "LCTRL1" },
507 { SPR_LCTRL2
, "LCTRL2" },
508 { SPR_ICTRL
, "ICTRL" },
510 { SPR_USPRG0
, "USPRG0" },
511 { SPR_SPRG4_RO
, "SPRG4_RO" },
512 { SPR_SPRG5_RO
, "SPRG5_RO" },
513 { SPR_SPRG6_RO
, "SPRG6_RO" },
514 { SPR_SPRG7_RO
, "SPRG7_RO" },
515 { SPR_SPRG0
, "SPRG0" },
516 { SPR_SPRG1
, "SPRG1" },
517 { SPR_SPRG2
, "SPRG2" },
518 { SPR_SPRG3
, "SPRG3" },
519 { SPR_SPRG4
, "SPRG4" },
520 { SPR_SPRG5
, "SPRG5" },
521 { SPR_SPRG6
, "SPRG6" },
522 { SPR_SPRG7
, "SPRG7" },
526 { SPR_IC_CST
, "IC_CST" },
527 { SPR_IC_ADR
, "IC_ADR" },
528 { SPR_IC_DAT
, "IC_DAT" },
529 { SPR_DC_CST
, "DC_CST" },
530 { SPR_DC_ADR
, "DC_ADR" },
531 { SPR_DC_DAT
, "DC_DAT" },
532 { SPR_DPDR
, "DPDR" },
533 { SPR_IMMR
, "IMMR" },
534 { SPR_MI_CTR
, "MI_CTR" },
535 { SPR_MI_AP
, "MI_AP" },
536 { SPR_MI_EPN
, "MI_EPN" },
537 { SPR_MI_TWC
, "MI_TWC" },
538 { SPR_MI_RPN
, "MI_RPN" },
539 { SPR_MD_CTR
, "MD_CTR" },
540 { SPR_M_CASID
, "M_CASID" },
541 { SPR_MD_AP
, "MD_AP" },
542 { SPR_MD_EPN
, "MD_EPN" },
543 { SPR_M_TWB
, "M_TWB" },
544 { SPR_MD_TWC
, "MD_TWC" },
545 { SPR_MD_RPN
, "MD_RPN" },
546 { SPR_M_TW
, "M_TW" },
547 { SPR_MI_DBCAM
, "MI_DBCAM" },
548 { SPR_MI_DBRAM0
, "MI_DBRAM0" },
549 { SPR_MI_DBRAM1
, "MI_DBRAM1" },
550 { SPR_MD_DBCAM
, "MD_DBCAM" },
551 { SPR_MD_DBRAM0
, "MD_DBRAM0" },
552 { SPR_MD_DBRAM1
, "MD_DBRAM1" },
555 { SPR_CCR0
, "CCR0" },
556 { SPR_IAC3
, "IAC3" },
557 { SPR_IAC4
, "IAC4" },
558 { SPR_DVC1
, "DVC1" },
559 { SPR_DVC2
, "DVC2" },
561 { SPR_DCWR
, "DCWR" },
562 { SPR_SLER
, "SLER" },
563 { SPR_SU0R
, "SU0R" },
564 { SPR_DBCR1
, "DBCR1" },
565 { SPR_ICDBDR
, "ICDBDR" },
567 { SPR_DEAR
, "DEAR" },
568 { SPR_EVPR
, "EVPR" },
572 { SPR_SRR2
, "SRR2" },
573 { SPR_SRR3
, "SRR3" },
574 { SPR_DBSR
, "DBSR" },
575 { SPR_DBCR0
, "DBCR0" },
576 { SPR_IAC1
, "IAC1" },
577 { SPR_IAC2
, "IAC2" },
578 { SPR_DAC1
, "DAC1" },
579 { SPR_DAC2
, "DAC2" },
580 { SPR_DCCR
, "DCCR" },
581 { SPR_ICCR
, "ICCR" },
584 const unsigned int n_sprs
= sizeof(spr_map
) / sizeof(spr_map
[0]);
589 * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
590 * All rights reserved.
592 * Redistribution and use in source and binary forms are freely
593 * permitted provided that the above copyright notice and this
594 * paragraph and the following disclaimer are duplicated in all
597 * This software is provided "AS IS" and without any express or
598 * implied warranties, including, without limitation, the implied
599 * warranties of merchantability and fitness for a particular