include/commproc.h

   1 /*
   2  * MPC8xx Communication Processor Module.
   3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   4  *
   5  * This file contains structures and information for the communication
   6  * processor channels.  Some CPM control and status is available
   7  * throught the MPC8xx internal memory map.  See immap.h for details.
   8  * This file only contains what I need for the moment, not the total
   9  * CPM capabilities.  I (or someone else) will add definitions as they
  10  * are needed.  -- Dan
  11  *
  12  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  13  * bytes of the DP RAM and relocates the I2C parameter area to the
  14  * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  15  * or other use.
  16  */
  17 #ifndef __CPM_8XX__
  18 #define __CPM_8XX__
  19
  20 #include <linux/config.h>
  21 #include <asm/8xx_immap.h>
  22
  23 /* CPM Command register.
  24 */
  25 #define CPM_CR_RST              ((ushort)0x8000)
  26 #define CPM_CR_OPCODE           ((ushort)0x0f00)
  27 #define CPM_CR_CHAN             ((ushort)0x00f0)
  28 #define CPM_CR_FLG              ((ushort)0x0001)
  29
  30 /* Some commands (there are more...later)
  31 */
  32 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
  33 #define CPM_CR_INIT_RX          ((ushort)0x0001)
  34 #define CPM_CR_INIT_TX          ((ushort)0x0002)
  35 #define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  36 #define CPM_CR_STOP_TX          ((ushort)0x0004)
  37 #define CPM_CR_RESTART_TX       ((ushort)0x0006)
  38 #define CPM_CR_SET_GADDR        ((ushort)0x0008)
  39
  40 /* Channel numbers.
  41 */
  42 #define CPM_CR_CH_SCC1          ((ushort)0x0000)
  43 #define CPM_CR_CH_I2C           ((ushort)0x0001)    /* I2C and IDMA1 */
  44 #define CPM_CR_CH_SCC2          ((ushort)0x0004)
  45 #define CPM_CR_CH_SPI           ((ushort)0x0005)    /* SPI/IDMA2/Timers */
  46 #define CPM_CR_CH_SCC3          ((ushort)0x0008)
  47 #define CPM_CR_CH_SMC1          ((ushort)0x0009)    /* SMC1 / DSP1 */
  48 #define CPM_CR_CH_SCC4          ((ushort)0x000c)
  49 #define CPM_CR_CH_SMC2          ((ushort)0x000d)    /* SMC2 / DSP2 */
  50
  51 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  52
  53 /*
  54  * DPRAM defines and allocation functions
  55  */
  56
  57 /* The dual ported RAM is multi-functional.  Some areas can be (and are
  58  * being) used for microcode.  There is an area that can only be used
  59  * as data ram for buffer descriptors, which is all we use right now.
  60  * Currently the first 512 and last 256 bytes are used for microcode.
  61  */
  62 #ifdef  CFG_ALLOC_DPRAM
  63
  64 #define CPM_DATAONLY_BASE       ((uint)0x0800)
  65 #define CPM_DATAONLY_SIZE       ((uint)0x0700)
  66 #define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  67
  68 #else
  69
  70 #define CPM_SERIAL_BASE         0x0800
  71 #define CPM_I2C_BASE            0x0820
  72 #define CPM_SPI_BASE            0x0840
  73 #define CPM_FEC_BASE            0x0860
  74 #define CPM_WLKBD_BASE          0x0880
  75 #define CPM_SCC_BASE            0x0900
  76 #define CPM_POST_BASE           0x0980
  77
  78 #endif
  79
  80 #ifndef CFG_CPM_POST_WORD_ADDR
  81 #define CPM_POST_WORD_ADDR      0x07FC
  82 #else
  83 #define CPM_POST_WORD_ADDR      CFG_CPM_POST_WORD_ADDR
  84 #endif
  85
  86 #ifndef CFG_CPM_BOOTCOUNT_ADDR
  87 #define CPM_BOOTCOUNT_ADDR      (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
  88 #else
  89 #define CPM_BOOTCOUNT_ADDR      CFG_CPM_BOOTCOUNT_ADDR
  90 #endif
  91
  92 #define BD_IIC_START    ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
  93
  94 /* Export the base address of the communication processor registers
  95  * and dual port ram.
  96  */
  97 extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
  98
  99 /* Buffer descriptors used by many of the CPM protocols.
 100 */
 101 typedef struct cpm_buf_desc {
 102         ushort  cbd_sc;         /* Status and Control */
 103         ushort  cbd_datlen;     /* Data length in buffer */
 104         uint    cbd_bufaddr;    /* Buffer address in host memory */
 105 } cbd_t;
 106
 107 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Recieve is empty */
 108 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
 109 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
 110 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
 111 #define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
 112 #define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
 113 #define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
 114 #define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
 115 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
 116 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
 117 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
 118 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
 119 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
 120 #define BD_SC_CD        ((ushort)0x0001)        /* Carrier Detect lost */
 121
 122 /* Parameter RAM offsets.
 123 */
 124 #define PROFF_SCC1      ((uint)0x0000)
 125 #define PROFF_IIC       ((uint)0x0080)
 126 #define PROFF_SCC2      ((uint)0x0100)
 127 #define PROFF_SPI       ((uint)0x0180)
 128 #define PROFF_SCC3      ((uint)0x0200)
 129 #define PROFF_SMC1      ((uint)0x0280)
 130 #define PROFF_SCC4      ((uint)0x0300)
 131 #define PROFF_SMC2      ((uint)0x0380)
 132
 133 /* Define enough so I can at least use the serial port as a UART.
 134  * The MBX uses SMC1 as the host serial port.
 135  */
 136 typedef struct smc_uart {
 137         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 138         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 139         u_char  smc_rfcr;       /* Rx function code */
 140         u_char  smc_tfcr;       /* Tx function code */
 141         ushort  smc_mrblr;      /* Max receive buffer length */
 142         uint    smc_rstate;     /* Internal */
 143         uint    smc_idp;        /* Internal */
 144         ushort  smc_rbptr;      /* Internal */
 145         ushort  smc_ibc;        /* Internal */
 146         uint    smc_rxtmp;      /* Internal */
 147         uint    smc_tstate;     /* Internal */
 148         uint    smc_tdp;        /* Internal */
 149         ushort  smc_tbptr;      /* Internal */
 150         ushort  smc_tbc;        /* Internal */
 151         uint    smc_txtmp;      /* Internal */
 152         ushort  smc_maxidl;     /* Maximum idle characters */
 153         ushort  smc_tmpidl;     /* Temporary idle counter */
 154         ushort  smc_brklen;     /* Last received break length */
 155         ushort  smc_brkec;      /* rcv'd break condition counter */
 156         ushort  smc_brkcr;      /* xmt break count register */
 157         ushort  smc_rmask;      /* Temporary bit mask */
 158 } smc_uart_t;
 159
 160 /* Function code bits.
 161 */
 162 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 163
 164 /* SMC uart mode register.
 165 */
 166 #define SMCMR_REN       ((ushort)0x0001)
 167 #define SMCMR_TEN       ((ushort)0x0002)
 168 #define SMCMR_DM        ((ushort)0x000c)
 169 #define SMCMR_SM_GCI    ((ushort)0x0000)
 170 #define SMCMR_SM_UART   ((ushort)0x0020)
 171 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 172 #define SMCMR_SM_MASK   ((ushort)0x0030)
 173 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 174 #define SMCMR_REVD      SMCMR_PM_EVEN
 175 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 176 #define SMCMR_BS        SMCMR_PEN
 177 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 178 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 179 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 180
 181 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
 182  * it can only receive or transmit.  The parameter ram values for
 183  * each direction are either unique or properly overlap, so we can
 184  * include them in one structure.
 185  */
 186 typedef struct smc_centronics {
 187         ushort  scent_rbase;
 188         ushort  scent_tbase;
 189         u_char  scent_cfcr;
 190         u_char  scent_smask;
 191         ushort  scent_mrblr;
 192         uint    scent_rstate;
 193         uint    scent_r_ptr;
 194         ushort  scent_rbptr;
 195         ushort  scent_r_cnt;
 196         uint    scent_rtemp;
 197         uint    scent_tstate;
 198         uint    scent_t_ptr;
 199         ushort  scent_tbptr;
 200         ushort  scent_t_cnt;
 201         uint    scent_ttemp;
 202         ushort  scent_max_sl;
 203         ushort  scent_sl_cnt;
 204         ushort  scent_character1;
 205         ushort  scent_character2;
 206         ushort  scent_character3;
 207         ushort  scent_character4;
 208         ushort  scent_character5;
 209         ushort  scent_character6;
 210         ushort  scent_character7;
 211         ushort  scent_character8;
 212         ushort  scent_rccm;
 213         ushort  scent_rccr;
 214 } smc_cent_t;
 215
 216 /* Centronics Status Mask Register.
 217 */
 218 #define SMC_CENT_F      ((u_char)0x08)
 219 #define SMC_CENT_PE     ((u_char)0x04)
 220 #define SMC_CENT_S      ((u_char)0x02)
 221
 222 /* SMC Event and Mask register.
 223 */
 224 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 225 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 226 #define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 227 #define SMCM_BSY        ((unsigned char)0x04)
 228 #define SMCM_TX         ((unsigned char)0x02)
 229 #define SMCM_RX         ((unsigned char)0x01)
 230
 231 /* Baud rate generators.
 232 */
 233 #define CPM_BRG_RST             ((uint)0x00020000)
 234 #define CPM_BRG_EN              ((uint)0x00010000)
 235 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 236 #define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 237 #define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 238 #define CPM_BRG_ATB             ((uint)0x00002000)
 239 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 240 #define CPM_BRG_DIV16           ((uint)0x00000001)
 241
 242 /* SI Clock Route Register
 243 */
 244 #define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 245 #define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 246 #define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 247 #define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 248 #define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 249 #define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 250 #define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 251 #define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 252
 253 /* SCCs.
 254 */
 255 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 256 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 257 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 258 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 259 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 260 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 261 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 262 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 263 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 264 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 265 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 266 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 267 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 268 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 269 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 270 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 271 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 272 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 273 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 274 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 275
 276 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 277 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 278 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 279 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 280 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 281 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 282 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 283 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 284 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 285 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 286 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 287 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 288 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 289 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 290 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 291 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 292 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 293 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 294 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 295 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 296 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 297 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 298 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 299 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 300 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 301 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 302 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 303 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 304 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 305 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 306 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 307 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 308 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 309 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 310 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 311 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 312 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 313 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 314 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 315 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 316 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 317 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 318 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 319 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 320 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 321 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 322 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 323 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 324 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 325 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 326 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 327 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 328 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 329 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 330 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 331 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 332 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 333 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 334
 335 #define SCC_TODR_TOD            ((ushort)0x8000)
 336
 337 /* SCC Event and Mask register.
 338 */
 339 #define SCCM_TXE        ((unsigned char)0x10)
 340 #define SCCM_BSY        ((unsigned char)0x04)
 341 #define SCCM_TX         ((unsigned char)0x02)
 342 #define SCCM_RX         ((unsigned char)0x01)
 343
 344 typedef struct scc_param {
 345         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 346         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 347         u_char  scc_rfcr;       /* Rx function code */
 348         u_char  scc_tfcr;       /* Tx function code */
 349         ushort  scc_mrblr;      /* Max receive buffer length */
 350         uint    scc_rstate;     /* Internal */
 351         uint    scc_idp;        /* Internal */
 352         ushort  scc_rbptr;      /* Internal */
 353         ushort  scc_ibc;        /* Internal */
 354         uint    scc_rxtmp;      /* Internal */
 355         uint    scc_tstate;     /* Internal */
 356         uint    scc_tdp;        /* Internal */
 357         ushort  scc_tbptr;      /* Internal */
 358         ushort  scc_tbc;        /* Internal */
 359         uint    scc_txtmp;      /* Internal */
 360         uint    scc_rcrc;       /* Internal */
 361         uint    scc_tcrc;       /* Internal */
 362 } sccp_t;
 363
 364 /* Function code bits.
 365 */
 366 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 367
 368 /* CPM Ethernet through SCCx.
 369  */
 370 typedef struct scc_enet {
 371         sccp_t  sen_genscc;
 372         uint    sen_cpres;      /* Preset CRC */
 373         uint    sen_cmask;      /* Constant mask for CRC */
 374         uint    sen_crcec;      /* CRC Error counter */
 375         uint    sen_alec;       /* alignment error counter */
 376         uint    sen_disfc;      /* discard frame counter */
 377         ushort  sen_pads;       /* Tx short frame pad character */
 378         ushort  sen_retlim;     /* Retry limit threshold */
 379         ushort  sen_retcnt;     /* Retry limit counter */
 380         ushort  sen_maxflr;     /* maximum frame length register */
 381         ushort  sen_minflr;     /* minimum frame length register */
 382         ushort  sen_maxd1;      /* maximum DMA1 length */
 383         ushort  sen_maxd2;      /* maximum DMA2 length */
 384         ushort  sen_maxd;       /* Rx max DMA */
 385         ushort  sen_dmacnt;     /* Rx DMA counter */
 386         ushort  sen_maxb;       /* Max BD byte count */
 387         ushort  sen_gaddr1;     /* Group address filter */
 388         ushort  sen_gaddr2;
 389         ushort  sen_gaddr3;
 390         ushort  sen_gaddr4;
 391         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 392         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 393         uint    sen_tbuf0rba;   /* Internal */
 394         uint    sen_tbuf0crc;   /* Internal */
 395         ushort  sen_tbuf0bcnt;  /* Internal */
 396         ushort  sen_paddrh;     /* physical address (MSB) */
 397         ushort  sen_paddrm;
 398         ushort  sen_paddrl;     /* physical address (LSB) */
 399         ushort  sen_pper;       /* persistence */
 400         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 401         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 402         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 403         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 404         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 405         uint    sen_tbuf1rba;   /* Internal */
 406         uint    sen_tbuf1crc;   /* Internal */
 407         ushort  sen_tbuf1bcnt;  /* Internal */
 408         ushort  sen_txlen;      /* Tx Frame length counter */
 409         ushort  sen_iaddr1;     /* Individual address filter */
 410         ushort  sen_iaddr2;
 411         ushort  sen_iaddr3;
 412         ushort  sen_iaddr4;
 413         ushort  sen_boffcnt;    /* Backoff counter */
 414
 415         /* NOTE: Some versions of the manual have the following items
 416          * incorrectly documented.  Below is the proper order.
 417          */
 418         ushort  sen_taddrh;     /* temp address (MSB) */
 419         ushort  sen_taddrm;
 420         ushort  sen_taddrl;     /* temp address (LSB) */
 421 } scc_enet_t;
 422
 423 /**********************************************************************
 424  *
 425  * Board specific configuration settings.
 426  *
 427  * Please note that we use the presence of a #define SCC_ENET and/or
 428  * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
 429  **********************************************************************/
 430
 431
 432 /***  ADS  *************************************************************/
 433
 434 #if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
 435 /* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
 436  */
 437
 438 #define PROFF_ENET      PROFF_SCC1
 439 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 440 #define SCC_ENET        0
 441
 442 #define PA_ENET_RXD     ((ushort)0x0001)
 443 #define PA_ENET_TXD     ((ushort)0x0002)
 444 #define PA_ENET_TCLK    ((ushort)0x0100)
 445 #define PA_ENET_RCLK    ((ushort)0x0200)
 446
 447 #define PB_ENET_TENA    ((uint)0x00001000)
 448
 449 #define PC_ENET_CLSN    ((ushort)0x0010)
 450 #define PC_ENET_RENA    ((ushort)0x0020)
 451
 452 #define SICR_ENET_MASK  ((uint)0x000000ff)
 453 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 454
 455 /* 68160 PHY control */
 456
 457 #define PC_ENET_ETHLOOP ((ushort)0x0800)
 458 #define PC_ENET_TPFLDL  ((ushort)0x0400)
 459 #define PC_ENET_TPSQEL  ((ushort)0x0200)
 460
 461 #endif  /* MPC860ADS */
 462
 463 /***  AMX860  **********************************************/
 464
 465 #if defined(CONFIG_AMX860)
 466
 467 /* This ENET stuff is for the AMX860 with ethernet on SCC1.
 468  */
 469
 470 #define PROFF_ENET      PROFF_SCC1
 471 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 472 #define SCC_ENET        0
 473
 474 #define PA_ENET_RXD     ((ushort)0x0001)
 475 #define PA_ENET_TXD     ((ushort)0x0002)
 476 #define PA_ENET_TCLK    ((ushort)0x0400)
 477 #define PA_ENET_RCLK    ((ushort)0x0800)
 478
 479 #define PB_ENET_TENA    ((uint)0x00001000)
 480
 481 #define PC_ENET_CLSN    ((ushort)0x0010)
 482 #define PC_ENET_RENA    ((ushort)0x0020)
 483
 484 #define SICR_ENET_MASK  ((uint)0x000000ff)
 485 #define SICR_ENET_CLKRT ((uint)0x0000003e)
 486
 487 /* 68160 PHY control */
 488
 489 #define PB_ENET_ETHLOOP ((uint)0x00020000)
 490 #define PB_ENET_TPFLDL  ((uint)0x00010000)
 491 #define PB_ENET_TPSQEL  ((uint)0x00008000)
 492 #define PD_ENET_ETH_EN  ((ushort)0x0004)
 493
 494 #endif  /* CONFIG_AMX860 */
 495
 496 /***  BSEIP  **********************************************************/
 497
 498 #ifdef CONFIG_BSEIP
 499 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
 500  * This is unique to the BSE ip-Engine board.
 501  */
 502 #define PROFF_ENET      PROFF_SCC2
 503 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 504 #define SCC_ENET        1
 505 #define PA_ENET_RXD     ((ushort)0x0004)
 506 #define PA_ENET_TXD     ((ushort)0x0008)
 507 #define PA_ENET_TCLK    ((ushort)0x0100)
 508 #define PA_ENET_RCLK    ((ushort)0x0200)
 509 #define PB_ENET_TENA    ((uint)0x00002000)
 510 #define PC_ENET_CLSN    ((ushort)0x0040)
 511 #define PC_ENET_RENA    ((ushort)0x0080)
 512
 513 /* BSE uses port B and C bits for PHY control also.
 514 */
 515 #define PB_BSE_POWERUP  ((uint)0x00000004)
 516 #define PB_BSE_FDXDIS   ((uint)0x00008000)
 517 #define PC_BSE_LOOPBACK ((ushort)0x0800)
 518
 519 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 520 #define SICR_ENET_CLKRT ((uint)0x00002c00)
 521 #endif  /* CONFIG_BSEIP */
 522
 523 /***  BSEIP  **********************************************************/
 524
 525 #ifdef CONFIG_FLAGADM
 526 /* Enet configuration for the FLAGADM */
 527 /* Enet on SCC2 */
 528
 529 #define PROFF_ENET      PROFF_SCC2
 530 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 531 #define SCC_ENET        1
 532 #define PA_ENET_RXD     ((ushort)0x0004)
 533 #define PA_ENET_TXD     ((ushort)0x0008)
 534 #define PA_ENET_TCLK    ((ushort)0x0100)
 535 #define PA_ENET_RCLK    ((ushort)0x0400)
 536 #define PB_ENET_TENA    ((uint)0x00002000)
 537 #define PC_ENET_CLSN    ((ushort)0x0040)
 538 #define PC_ENET_RENA    ((ushort)0x0080)
 539
 540 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 541 #define SICR_ENET_CLKRT ((uint)0x00003400)
 542 #endif  /* CONFIG_FLAGADM */
 543
 544 /***  C2MON  **********************************************************/
 545
 546 #ifdef CONFIG_C2MON
 547
 548 # ifndef CONFIG_FEC_ENET        /* use SCC for 10Mbps Ethernet  */
 549 #  error "Ethernet on SCC not supported on C2MON Board!"
 550 # else                          /* Use FEC for Fast Ethernet */
 551
 552 #undef  SCC_ENET
 553 #define FEC_ENET
 554
 555 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 556 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 557 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 558 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 559 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 560 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 561 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 562 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 563 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 564 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 565 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 566 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 567 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 568
 569 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 570
 571 # endif /* CONFIG_FEC_ENET */
 572 #endif  /* CONFIG_C2MON */
 573
 574 /*********************************************************************/
 575
 576
 577 /***  CCM  and  PCU E  ***********************************************/
 578
 579 /* The PCU E  and  CCM  use the FEC on a MPC860T for Ethernet */
 580
 581 #if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
 582
 583 #define FEC_ENET        /* use FEC for EThernet */
 584 #undef  SCC_ENET
 585
 586 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 587 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 588 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 589 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 590 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 591 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 592 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 593 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 594 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 595 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 596 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 597 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 598 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 599
 600 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 601
 602 #endif  /* CONFIG_PCU_E, CONFIG_CCM */
 603
 604 /***  ELPT860 *********************************************************/
 605
 606 #ifdef CONFIG_ELPT860
 607 /* Bits in parallel I/O port registers that have to be set/cleared
 608  * to configure the pins for SCC1 use.
 609  */
 610 #  define PROFF_ENET        PROFF_SCC1
 611 #  define CPM_CR_ENET       CPM_CR_CH_SCC1
 612 #  define SCC_ENET          0
 613
 614 #  define PA_ENET_RXD       ((ushort)0x0001)    /* PA 15 */
 615 #  define PA_ENET_TXD       ((ushort)0x0002)    /* PA 14 */
 616 #  define PA_ENET_RCLK      ((ushort)0x0100)    /* PA  7 */
 617 #  define PA_ENET_TCLK      ((ushort)0x0200)    /* PA  6 */
 618
 619 #  define PC_ENET_TENA      ((ushort)0x0001)    /* PC 15 */
 620 #  define PC_ENET_CLSN      ((ushort)0x0010)    /* PC 11 */
 621 #  define PC_ENET_RENA      ((ushort)0x0020)    /* PC 10 */
 622
 623 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
 624  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 625  */
 626 #  define SICR_ENET_MASK    ((uint)0x000000FF)
 627 #  define SICR_ENET_CLKRT   ((uint)0x00000025)
 628 #endif  /* CONFIG_ELPT860 */
 629
 630 /***  ESTEEM 192E  **************************************************/
 631 #ifdef CONFIG_ESTEEM192E
 632 /* ESTEEM192E
 633  * This ENET stuff is for the MPC850 with ethernet on SCC2. This
 634  * is very similar to the RPX-Lite configuration.
 635  * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
 636  */
 637
 638 #define PROFF_ENET      PROFF_SCC2
 639 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 640 #define SCC_ENET        1
 641
 642 #define PA_ENET_RXD     ((ushort)0x0004)
 643 #define PA_ENET_TXD     ((ushort)0x0008)
 644 #define PA_ENET_TCLK    ((ushort)0x0200)
 645 #define PA_ENET_RCLK    ((ushort)0x0800)
 646 #define PB_ENET_TENA    ((uint)0x00002000)
 647 #define PC_ENET_CLSN    ((ushort)0x0040)
 648 #define PC_ENET_RENA    ((ushort)0x0080)
 649
 650 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 651 #define SICR_ENET_CLKRT ((uint)0x00003d00)
 652
 653 #define PB_ENET_LOOPBACK ((uint)0x00004000)
 654 #define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
 655
 656 #endif
 657
 658 /***  FADS823  ********************************************************/
 659
 660 #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
 661 /* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
 662  */
 663 #ifdef CONFIG_SCC2_ENET
 664 #define PROFF_ENET      PROFF_SCC2
 665 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 666 #define SCC_ENET        1
 667 #define CPMVEC_ENET     CPMVEC_SCC2
 668 #endif
 669
 670 #ifdef CONFIG_SCC1_ENET
 671 #define PROFF_ENET      PROFF_SCC1
 672 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 673 #define SCC_ENET        0
 674 #define CPMVEC_ENET     CPMVEC_SCC1
 675 #endif
 676
 677 #define PA_ENET_RXD     ((ushort)0x0004)
 678 #define PA_ENET_TXD     ((ushort)0x0008)
 679 #define PA_ENET_TCLK    ((ushort)0x0400)
 680 #define PA_ENET_RCLK    ((ushort)0x0200)
 681
 682 #define PB_ENET_TENA    ((uint)0x00002000)
 683
 684 #define PC_ENET_CLSN    ((ushort)0x0040)
 685 #define PC_ENET_RENA    ((ushort)0x0080)
 686
 687 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 688 #define SICR_ENET_CLKRT ((uint)0x00002e00)
 689
 690 #endif  /* CONFIG_FADS823FADS */
 691
 692 /***  FADS850SAR  ********************************************************/
 693
 694 #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
 695 /* This ENET stuff is for the MPC850SAR with ethernet on SCC2.  Some of
 696  * this may be unique to the FADS850SAR configuration.
 697  * Note TENA is on Port B.
 698  */
 699 #define PROFF_ENET      PROFF_SCC2
 700 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 701 #define SCC_ENET        1
 702 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 703 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 704 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA 6 */
 705 #define PA_ENET_TCLK    ((ushort)0x0800)        /* PA 4 */
 706 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 707 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC 9 */
 708 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC 8 */
 709
 710 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 711 #define SICR_ENET_CLKRT ((uint)0x00002f00)      /* RCLK-CLK2, TCLK-CLK4 */
 712 #endif  /* CONFIG_FADS850SAR */
 713
 714 /***  FADS860T********************************************************/
 715
 716 #if (defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al)) \
 717     && defined(CONFIG_FADS)
 718 /* This ENET stuff is for the MPC860TFADS/MPC8xxADS with ethernet on SCC1.
 719  */
 720 #ifdef CONFIG_SCC1_ENET
 721 #define SCC_ENET        0
 722 #endif  /* CONFIG_SCC1_ETHERNET */
 723 #define PROFF_ENET      PROFF_SCC1
 724 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 725
 726 #define PA_ENET_RXD     ((ushort)0x0001)
 727 #define PA_ENET_TXD     ((ushort)0x0002)
 728 #define PA_ENET_TCLK    ((ushort)0x0100)
 729 #define PA_ENET_RCLK    ((ushort)0x0200)
 730
 731 #define PB_ENET_TENA    ((uint)0x00001000)
 732
 733 #define PC_ENET_CLSN    ((ushort)0x0010)
 734 #define PC_ENET_RENA    ((ushort)0x0020)
 735
 736 #define SICR_ENET_MASK  ((uint)0x000000ff)
 737 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 738
 739 /* This ENET stuff is for the MPC860TFADS with ethernet on FEC.
 740  */
 741
 742 #ifdef CONFIG_FEC_ENET
 743 #define FEC_ENET        /* use FEC for EThernet */
 744 #endif  /* CONFIG_FEC_ETHERNET */
 745
 746 #endif  /* CONFIG_FADS860T */
 747
 748 /***  FPS850L, FPS860L  ************************************************/
 749
 750 #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
 751 /* Bits in parallel I/O port registers that have to be set/cleared
 752  * to configure the pins for SCC2 use.
 753  */
 754 #define PROFF_ENET      PROFF_SCC2
 755 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 756 #define SCC_ENET        1
 757 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 758 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 759 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 760 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 761
 762 #define PC_ENET_TENA    ((ushort)0x0002)        /* PC 14 */
 763 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 764 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 765
 766 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 767  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 768  */
 769 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 770 #define SICR_ENET_CLKRT ((uint)0x00002600)
 771 #endif  /* CONFIG_FPS850L, CONFIG_FPS860L */
 772
 773 /*** GEN860T **********************************************************/
 774 #if defined(CONFIG_GEN860T)
 775 #undef  SCC_ENET
 776 #define FEC_ENET
 777
 778 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3        */
 779 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4        */
 780 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5        */
 781 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6        */
 782 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7        */
 783 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8        */
 784 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9        */
 785 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10        */
 786 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11        */
 787 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12        */
 788 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13        */
 789 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14        */
 790 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15        */
 791 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3-15      */
 792 #endif  /* CONFIG_GEN860T */
 793
 794 /***  GENIETV  ********************************************************/
 795
 796 #if defined(CONFIG_GENIETV)
 797 /* Ethernet is only on SCC2 */
 798
 799 #define CONFIG_SCC2_ENET
 800 #define PROFF_ENET      PROFF_SCC2
 801 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 802 #define SCC_ENET        1
 803 #define CPMVEC_ENET     CPMVEC_SCC2
 804
 805 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 806 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 807 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 808 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 809
 810 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 811
 812 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 813 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 814
 815 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 816 #define SICR_ENET_CLKRT ((uint)0x00002e00)
 817
 818 #endif  /* CONFIG_GENIETV */
 819
 820 /*** GTH ******************************************************/
 821
 822 #ifdef CONFIG_GTH
 823 #ifdef CONFIG_FEC_ENET
 824 #define FEC_ENET        /* use FEC for EThernet */
 825 #endif  /* CONFIG_FEC_ETHERNET */
 826
 827 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */
 828 #define PROFF_ENET      PROFF_SCC1
 829 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 830 #define SCC_ENET        0
 831
 832 #define PA_ENET_RXD     ((ushort)0x0001) /* PA15 */
 833 #define PA_ENET_TXD     ((ushort)0x0002) /* PA14 */
 834 #define PA_ENET_TCLK    ((ushort)0x0800) /* PA4 */
 835 #define PA_ENET_RCLK    ((ushort)0x0400) /* PA5 */
 836
 837 #define PB_ENET_TENA    ((uint)0x00001000) /* PB19 */
 838
 839 #define PC_ENET_CLSN    ((ushort)0x0010) /* PC11 */
 840 #define PC_ENET_RENA    ((ushort)0x0020) /* PC10 */
 841
 842 /* NOTE. This is reset for 10Mbit port only */
 843 #define PC_ENET_RESET   ((ushort)0x0100)        /* PC 7 */
 844
 845 #define SICR_ENET_MASK  ((uint)0x000000ff)
 846
 847 /* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
 848 #define SICR_ENET_CLKRT ((uint)0x00000037)
 849
 850 #endif  /* CONFIG_GTH */
 851
 852 /*** HERMES-PRO ******************************************************/
 853
 854 /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
 855
 856 #ifdef CONFIG_HERMES
 857
 858 #define FEC_ENET        /* use FEC for EThernet */
 859 #undef  SCC_ENET
 860
 861
 862 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 863 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 864 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 865 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 866 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 867 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 868 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 869 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 870 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 871 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 872 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 873 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 874 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 875
 876 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 877
 878 #endif  /* CONFIG_HERMES */
 879
 880 /***  IAD210  **********************************************************/
 881
 882 /* The IAD210 uses the FEC on a MPC860P for Ethernet */
 883
 884 #if defined(CONFIG_IAD210)
 885
 886 # define  FEC_ENET    /* use FEC for Ethernet */
 887 # undef   SCC_ENET
 888
 889 # define PD_MII_TXD1    ((ushort) 0x1000 )      /* PD  3 */
 890 # define PD_MII_TXD2    ((ushort) 0x0800 )      /* PD  4 */
 891 # define PD_MII_TXD3    ((ushort) 0x0400 )      /* PD  5 */
 892 # define PD_MII_RX_DV   ((ushort) 0x0200 )      /* PD  6 */
 893 # define PD_MII_RX_ERR  ((ushort) 0x0100 )      /* PD  7 */
 894 # define PD_MII_RX_CLK  ((ushort) 0x0080 )      /* PD  8 */
 895 # define PD_MII_TXD0    ((ushort) 0x0040 )      /* PD  9 */
 896 # define PD_MII_RXD0    ((ushort) 0x0020 )      /* PD 10 */
 897 # define PD_MII_TX_ERR  ((ushort) 0x0010 )      /* PD 11 */
 898 # define PD_MII_MDC     ((ushort) 0x0008 )      /* PD 12 */
 899 # define PD_MII_RXD1    ((ushort) 0x0004 )      /* PD 13 */
 900 # define PD_MII_RXD2    ((ushort) 0x0002 )      /* PD 14 */
 901 # define PD_MII_RXD3    ((ushort) 0x0001 )      /* PD 15 */
 902
 903 # define PD_MII_MASK    ((ushort) 0x1FFF )   /* PD 3...15 */
 904
 905 #endif  /* CONFIG_IAD210 */
 906
 907 /*** ICU862  **********************************************************/
 908
 909 #if defined(CONFIG_ICU862)
 910
 911 #ifdef CONFIG_FEC_ENET
 912 #define FEC_ENET        /* use FEC for EThernet */
 913 #endif  /* CONFIG_FEC_ETHERNET */
 914
 915 #endif /* CONFIG_ICU862 */
 916
 917 /***  IP860  **********************************************************/
 918
 919 #if defined(CONFIG_IP860)
 920 /* Bits in parallel I/O port registers that have to be set/cleared
 921  * to configure the pins for SCC1 use.
 922  */
 923 #define PROFF_ENET      PROFF_SCC1
 924 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 925 #define SCC_ENET        0
 926 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
 927 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
 928 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 929 #define PA_ENET_TCLK    ((ushort)0x0100)        /* PA  7 */
 930
 931 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
 932 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
 933 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
 934
 935 #define PB_ENET_RESET   (uint)0x00000008        /* PB 28 */
 936 #define PB_ENET_JABD    (uint)0x00000004        /* PB 29 */
 937
 938 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 939  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 940  */
 941 #define SICR_ENET_MASK  ((uint)0x000000ff)
 942 #define SICR_ENET_CLKRT ((uint)0x0000002C)
 943 #endif  /* CONFIG_IP860 */
 944
 945 /*** IVMS8  **********************************************************/
 946
 947 /* The IVMS8 uses the FEC on a MPC860T for Ethernet */
 948
 949 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
 950
 951 #define FEC_ENET        /* use FEC for EThernet */
 952 #undef  SCC_ENET
 953
 954 #define PB_ENET_POWER   ((uint)0x00010000)      /* PB 15 */
 955
 956 #define PC_ENET_RESET   ((ushort)0x0010)        /* PC 11 */
 957
 958 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 959 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 960 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 961 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 962 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 963 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 964 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 965 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 966 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 967 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 968 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 969 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 970 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 971
 972 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 973
 974 #endif  /* CONFIG_IVMS8, CONFIG_IVML24 */
 975
 976 /***  KUP4K  *********************************************************/
 977 /* The KUP4K uses the FEC on a MPC855T for Ethernet */
 978
 979 #if defined(CONFIG_KUP4K)
 980
 981 #define FEC_ENET        /* use FEC for EThernet */
 982 #undef  SCC_ENET
 983
 984 #define PB_ENET_POWER   ((uint)0x00010000)      /* PB 15 */
 985
 986 #define PC_ENET_RESET   ((ushort)0x0010)        /* PC 11 */
 987
 988 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 989 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 990 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 991 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 992 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 993 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 994 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 995 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 996 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 997 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 998 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 999 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
1000 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
1001
1002 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
1003
1004 #endif  /* CONFIG_KUP4K */
1005
1006
1007 /***  LANTEC  *********************************************************/
1008
1009 #if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
1010 /* Bits in parallel I/O port registers that have to be set/cleared
1011  * to configure the pins for SCC2 use.
1012  */
1013 #define PROFF_ENET      PROFF_SCC2
1014 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1015 #define SCC_ENET        1
1016 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1017 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1018 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
1019 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1020
1021 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1022
1023 #define PC_ENET_LBK     ((ushort)0x0010)        /* PC 11 */
1024 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1025 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1026
1027 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1028  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1029  */
1030 #define SICR_ENET_MASK  ((uint)0x0000FF00)
1031 #define SICR_ENET_CLKRT ((uint)0x00002E00)
1032 #endif  /* CONFIG_LANTEC v2 */
1033
1034 /***  LWMON  **********************************************************/
1035
1036 #if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
1037 /* Bits in parallel I/O port registers that have to be set/cleared
1038  * to configure the pins for SCC2 use.
1039  */
1040 #define PROFF_ENET      PROFF_SCC2
1041 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1042 #define SCC_ENET        1
1043 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1044 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1045 #define PA_ENET_RCLK    ((ushort)0x0800)        /* PA  4 */
1046 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1047
1048 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1049
1050 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1051 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1052
1053 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
1054  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1055  */
1056 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1057 #define SICR_ENET_CLKRT ((uint)0x00003E00)
1058 #endif  /* CONFIG_LWMON */
1059
1060 /***  NX823  ***********************************************/
1061
1062 #if defined(CONFIG_NX823)
1063 /* Bits in parallel I/O port registers that have to be set/cleared
1064  * to configure the pins for SCC1 use.
1065  */
1066 #define PROFF_ENET      PROFF_SCC2
1067 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1068 #define SCC_ENET        1
1069 #define PA_ENET_RXD     ((ushort)0x0004)  /* PA 13 */
1070 #define PA_ENET_TXD     ((ushort)0x0008)  /* PA 12 */
1071 #define PA_ENET_RCLK    ((ushort)0x0200)  /* PA  6 */
1072 #define PA_ENET_TCLK    ((ushort)0x0800)  /* PA  4 */
1073
1074 #define PB_ENET_TENA    ((uint)0x00002000)   /* PB 18 */
1075
1076 #define PC_ENET_CLSN    ((ushort)0x0040)  /* PC  9 */
1077 #define PC_ENET_RENA    ((ushort)0x0080)  /* PC  8 */
1078
1079 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1080  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1081  */
1082 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1083 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1084
1085 #endif   /* CONFIG_NX823 */
1086
1087 /***  MBX  ************************************************************/
1088
1089 #ifdef CONFIG_MBX
1090 /* Bits in parallel I/O port registers that have to be set/cleared
1091  * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
1092  * to the MBX860 board.  Any two of the four available clocks could be
1093  * used, and the MPC860 cookbook manual has an example using different
1094  * clock pins.
1095  */
1096 #define PROFF_ENET      PROFF_SCC1
1097 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1098 #define SCC_ENET        0
1099 #define PA_ENET_RXD     ((ushort)0x0001)
1100 #define PA_ENET_TXD     ((ushort)0x0002)
1101 #define PA_ENET_TCLK    ((ushort)0x0200)
1102 #define PA_ENET_RCLK    ((ushort)0x0800)
1103 #define PC_ENET_TENA    ((ushort)0x0001)
1104 #define PC_ENET_CLSN    ((ushort)0x0010)
1105 #define PC_ENET_RENA    ((ushort)0x0020)
1106
1107 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1108  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1109  */
1110 #define SICR_ENET_MASK  ((uint)0x000000ff)
1111 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1112 #endif  /* CONFIG_MBX */
1113
1114 /***  MHPC  ********************************************************/
1115
1116 #if defined(CONFIG_MHPC)
1117 /* This ENET stuff is for the MHPC with ethernet on SCC2.
1118  * Note TENA is on Port B.
1119  */
1120 #define PROFF_ENET      PROFF_SCC2
1121 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1122 #define SCC_ENET        1
1123 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1124 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1125 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA 6 */
1126 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA 5 */
1127 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1128 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC 9 */
1129 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC 8 */
1130
1131 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1132 #define SICR_ENET_CLKRT ((uint)0x00002e00)      /* RCLK-CLK2, TCLK-CLK3 */
1133 #endif  /* CONFIG_MHPC */
1134
1135 /***  NETVIA  *******************************************************/
1136
1137 /* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
1138 #if ( defined CONFIG_SVM_SC8xx )
1139 # ifndef CONFIG_FEC_ENET
1140
1141 #define PROFF_ENET      PROFF_SCC2
1142 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1143 #define SCC_ENET        1
1144
1145         /* Bits in parallel I/O port registers that have to be set/cleared
1146          *  *  *  * to configure the pins for SCC2 use.
1147          *   *   *   */
1148 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1149 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1150 #define PA_ENET_RCLK    ((ushort)0x0400)        /* PA  5 */
1151 #define PA_ENET_TCLK    ((ushort)0x0800)        /* PA  4 */
1152
1153 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1154
1155 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1156 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1157 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1158  *  *  *  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1159  *   *   *   */
1160 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1161 #define SICR_ENET_CLKRT ((uint)0x00003700)
1162
1163 # else                          /* Use FEC for Fast Ethernet */
1164
1165 #undef  SCC_ENET
1166 #define FEC_ENET
1167
1168 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
1169 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
1170 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
1171 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
1172 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
1173 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
1174 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
1175 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
1176 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
1177 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
1178 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
1179 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
1180 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
1181
1182 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
1183
1184 # endif /* CONFIG_FEC_ENET */
1185 #endif  /* CONFIG_SVM_SC8xx */
1186
1187
1188 #if defined(CONFIG_NETVIA)
1189 /* Bits in parallel I/O port registers that have to be set/cleared
1190  * to configure the pins for SCC2 use.
1191  */
1192 #define PROFF_ENET      PROFF_SCC2
1193 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1194 #define SCC_ENET        1
1195 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1196 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1197 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
1198 #define PA_ENET_TCLK    ((ushort)0x0800)        /* PA  4 */
1199
1200 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
1201 # define PB_ENET_PDN    ((ushort)0x4000)        /* PB 17 */
1202 #elif CONFIG_NETVIA_VERSION >= 2
1203 # define PC_ENET_PDN    ((ushort)0x0008)        /* PC 12 */
1204 #endif
1205
1206 #define PB_ENET_TENA    ((ushort)0x2000)        /* PB 18 */
1207
1208 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1209 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1210
1211 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1212  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1213  */
1214 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1215 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1216
1217 #endif  /* CONFIG_NETVIA */
1218
1219 /***  RPXCLASSIC  *****************************************************/
1220
1221 #ifdef CONFIG_RPXCLASSIC
1222
1223 #ifdef CONFIG_FEC_ENET
1224
1225 # define FEC_ENET                               /* use FEC for EThernet */
1226 # undef SCC_ENET
1227
1228 #else   /* ! CONFIG_FEC_ENET */
1229
1230 /* Bits in parallel I/O port registers that have to be set/cleared
1231  * to configure the pins for SCC1 use.
1232  */
1233 #define PROFF_ENET      PROFF_SCC1
1234 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1235 #define SCC_ENET        0
1236 #define PA_ENET_RXD     ((ushort)0x0001)
1237 #define PA_ENET_TXD     ((ushort)0x0002)
1238 #define PA_ENET_TCLK    ((ushort)0x0200)
1239 #define PA_ENET_RCLK    ((ushort)0x0800)
1240 #define PB_ENET_TENA    ((uint)0x00001000)
1241 #define PC_ENET_CLSN    ((ushort)0x0010)
1242 #define PC_ENET_RENA    ((ushort)0x0020)
1243
1244 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1245  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1246  */
1247 #define SICR_ENET_MASK  ((uint)0x000000ff)
1248 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1249
1250 #endif  /* CONFIG_FEC_ENET */
1251
1252 #endif  /* CONFIG_RPXCLASSIC */
1253
1254 /***  RPXLITE  ********************************************************/
1255
1256 #ifdef CONFIG_RPXLITE
1257 /* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
1258  * this may be unique to the RPX-Lite configuration.
1259  * Note TENA is on Port B.
1260  */
1261 #define PROFF_ENET      PROFF_SCC2
1262 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1263 #define SCC_ENET        1
1264 #define PA_ENET_RXD     ((ushort)0x0004)
1265 #define PA_ENET_TXD     ((ushort)0x0008)
1266 #define PA_ENET_TCLK    ((ushort)0x0200)
1267 #define PA_ENET_RCLK    ((ushort)0x0800)
1268 #if defined(CONFIG_RMU)
1269 #define PC_ENET_TENA    ((uint)0x00000002)      /* PC14 */
1270 #else
1271 #define PB_ENET_TENA    ((uint)0x00002000)
1272 #endif
1273 #define PC_ENET_CLSN    ((ushort)0x0040)
1274 #define PC_ENET_RENA    ((ushort)0x0080)
1275
1276 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1277 #define SICR_ENET_CLKRT ((uint)0x00003d00)
1278 #endif  /* CONFIG_RPXLITE */
1279
1280 /***  SM850  *********************************************************/
1281
1282 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
1283
1284 #ifdef CONFIG_SM850
1285 #define PROFF_ENET      PROFF_SCC3              /* Ethernet on SCC3 */
1286 #define CPM_CR_ENET     CPM_CR_CH_SCC3
1287 #define SCC_ENET        2
1288 #define PB_ENET_RXD     ((uint)0x00000004)      /* PB 29 */
1289 #define PB_ENET_TXD     ((uint)0x00000002)      /* PB 30 */
1290 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1291 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1292
1293 #define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
1294 #define PC_ENET_TENA    ((ushort)0x0004)        /* PC 13 */
1295
1296 #define PC_ENET_RENA    ((ushort)0x0800)        /* PC  4 */
1297 #define PC_ENET_CLSN    ((ushort)0x0400)        /* PC  5 */
1298
1299 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1300  * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1301  */
1302 #define SICR_ENET_MASK  ((uint)0x00FF0000)
1303 #define SICR_ENET_CLKRT ((uint)0x00260000)
1304 #endif  /* CONFIG_SM850 */
1305
1306 /***  SPD823TS  ******************************************************/
1307
1308 #ifdef CONFIG_SPD823TS
1309 /* Bits in parallel I/O port registers that have to be set/cleared
1310  * to configure the pins for SCC2 use.
1311  */
1312 #define PROFF_ENET      PROFF_SCC2              /* Ethernet on SCC2 */
1313 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1314 #define SCC_ENET        1
1315 #define PA_ENET_MDC     ((ushort)0x0001)        /* PA 15 !!! */
1316 #define PA_ENET_MDIO    ((ushort)0x0002)        /* PA 14 !!! */
1317 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1318 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1319 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
1320 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1321
1322 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1323
1324 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1325 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1326 #define PC_ENET_RESET   ((ushort)0x0100)        /* PC  7 !!! */
1327
1328 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1329  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1330  */
1331 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1332 #define SICR_ENET_CLKRT ((uint)0x00002E00)
1333 #endif  /* CONFIG_SPD823TS */
1334
1335 /***  SXNI855T  ******************************************************/
1336
1337 #if defined(CONFIG_SXNI855T)
1338
1339 #ifdef CONFIG_FEC_ENET
1340 #define FEC_ENET        /* use FEC for Ethernet */
1341 #endif  /* CONFIG_FEC_ETHERNET */
1342
1343 #endif  /* CONFIG_SXNI855T */
1344
1345 /***  MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI  *******************/
1346
1347 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
1348     defined(CONFIG_R360MPI) || defined(CONFIG_RBC823)  || \
1349     defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
1350     defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
1351     defined(CONFIG_ETX094)  || defined(CONFIG_RRVISION)|| \
1352    (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
1353 /* Bits in parallel I/O port registers that have to be set/cleared
1354  * to configure the pins for SCC2 use.
1355  */
1356 #define PROFF_ENET      PROFF_SCC2
1357 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1358 #define SCC_ENET        1
1359 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1360 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1361 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1362 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1363
1364 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1365
1366 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1367 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1368 #if defined(CONFIG_R360MPI)
1369 #define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
1370 #endif   /* CONFIG_R360MPI */
1371
1372 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1373  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1374  */
1375 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1376 #define SICR_ENET_CLKRT ((uint)0x00002600)
1377 #endif  /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
1378
1379 /***  TQM855L/M, TQM860L/M, TQM862L/M  ********************************/
1380
1381 #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
1382     defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
1383     defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M)
1384
1385 # ifdef CONFIG_SCC1_ENET        /* use SCC for 10Mbps Ethernet  */
1386
1387 /* Bits in parallel I/O port registers that have to be set/cleared
1388  * to configure the pins for SCC1 use.
1389  */
1390 #define PROFF_ENET      PROFF_SCC1
1391 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1392 #define SCC_ENET        0
1393 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
1394 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
1395 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1396 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1397
1398 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
1399 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
1400 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
1401
1402 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1403  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1404  */
1405 #define SICR_ENET_MASK  ((uint)0x000000ff)
1406 #define SICR_ENET_CLKRT ((uint)0x00000026)
1407
1408 # endif /* CONFIG_SCC1_ENET */
1409
1410 # ifdef CONFIG_FEC_ENET         /* Use FEC for Fast Ethernet */
1411
1412 #define FEC_ENET
1413
1414 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
1415 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
1416 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
1417 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
1418 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
1419 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
1420 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
1421 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
1422 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
1423 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
1424 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
1425 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
1426 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
1427
1428 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
1429
1430 # endif /* CONFIG_FEC_ENET */
1431 #endif  /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
1432
1433 /***  V37  **********************************************************/
1434
1435 #ifdef CONFIG_V37
1436 /* This ENET stuff is for the MPC823 with ethernet on SCC2.  Some of
1437  * this may be unique to the Marel V37 configuration.
1438  * Note TENA is on Port B.
1439  */
1440 #define PROFF_ENET      PROFF_SCC2
1441 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1442 #define SCC_ENET        1
1443 #define PA_ENET_RXD     ((ushort)0x0004)
1444 #define PA_ENET_TXD     ((ushort)0x0008)
1445 #define PA_ENET_TCLK    ((ushort)0x0400)
1446 #define PA_ENET_RCLK    ((ushort)0x0200)
1447 #define PB_ENET_TENA    ((uint)0x00002000)
1448 #define PC_ENET_CLSN    ((ushort)0x0040)
1449 #define PC_ENET_RENA    ((ushort)0x0080)
1450
1451 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1452 #define SICR_ENET_CLKRT ((uint)0x00002e00)
1453 #endif  /* CONFIG_V37 */
1454
1455 /*********************************************************************/
1456
1457 /* SCC Event register as used by Ethernet.
1458 */
1459 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
1460 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
1461 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
1462 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
1463 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
1464 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
1465
1466 /* SCC Mode Register (PSMR) as used by Ethernet.
1467 */
1468 #define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
1469 #define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
1470 #define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
1471 #define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
1472 #define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
1473 #define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
1474 #define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
1475 #define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
1476 #define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
1477 #define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
1478 #define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
1479 #define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
1480 #define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
1481
1482 /* Buffer descriptor control/status used by Ethernet receive.
1483 */
1484 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
1485 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
1486 #define BD_ENET_RX_INTR         ((ushort)0x1000)
1487 #define BD_ENET_RX_LAST         ((ushort)0x0800)
1488 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
1489 #define BD_ENET_RX_MISS         ((ushort)0x0100)
1490 #define BD_ENET_RX_LG           ((ushort)0x0020)
1491 #define BD_ENET_RX_NO           ((ushort)0x0010)
1492 #define BD_ENET_RX_SH           ((ushort)0x0008)
1493 #define BD_ENET_RX_CR           ((ushort)0x0004)
1494 #define BD_ENET_RX_OV           ((ushort)0x0002)
1495 #define BD_ENET_RX_CL           ((ushort)0x0001)
1496 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
1497
1498 /* Buffer descriptor control/status used by Ethernet transmit.
1499 */
1500 #define BD_ENET_TX_READY        ((ushort)0x8000)
1501 #define BD_ENET_TX_PAD          ((ushort)0x4000)
1502 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
1503 #define BD_ENET_TX_INTR         ((ushort)0x1000)
1504 #define BD_ENET_TX_LAST         ((ushort)0x0800)
1505 #define BD_ENET_TX_TC           ((ushort)0x0400)
1506 #define BD_ENET_TX_DEF          ((ushort)0x0200)
1507 #define BD_ENET_TX_HB           ((ushort)0x0100)
1508 #define BD_ENET_TX_LC           ((ushort)0x0080)
1509 #define BD_ENET_TX_RL           ((ushort)0x0040)
1510 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
1511 #define BD_ENET_TX_UN           ((ushort)0x0002)
1512 #define BD_ENET_TX_CSL          ((ushort)0x0001)
1513 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
1514
1515 /* SCC as UART
1516 */
1517 typedef struct scc_uart {
1518         sccp_t  scc_genscc;
1519         uint    scc_res1;       /* Reserved */
1520         uint    scc_res2;       /* Reserved */
1521         ushort  scc_maxidl;     /* Maximum idle chars */
1522         ushort  scc_idlc;       /* temp idle counter */
1523         ushort  scc_brkcr;      /* Break count register */
1524         ushort  scc_parec;      /* receive parity error counter */
1525         ushort  scc_frmec;      /* receive framing error counter */
1526         ushort  scc_nosec;      /* receive noise counter */
1527         ushort  scc_brkec;      /* receive break condition counter */
1528         ushort  scc_brkln;      /* last received break length */
1529         ushort  scc_uaddr1;     /* UART address character 1 */
1530         ushort  scc_uaddr2;     /* UART address character 2 */
1531         ushort  scc_rtemp;      /* Temp storage */
1532         ushort  scc_toseq;      /* Transmit out of sequence char */
1533         ushort  scc_char1;      /* control character 1 */
1534         ushort  scc_char2;      /* control character 2 */
1535         ushort  scc_char3;      /* control character 3 */
1536         ushort  scc_char4;      /* control character 4 */
1537         ushort  scc_char5;      /* control character 5 */
1538         ushort  scc_char6;      /* control character 6 */
1539         ushort  scc_char7;      /* control character 7 */
1540         ushort  scc_char8;      /* control character 8 */
1541         ushort  scc_rccm;       /* receive control character mask */
1542         ushort  scc_rccr;       /* receive control character register */
1543         ushort  scc_rlbc;       /* receive last break character */
1544 } scc_uart_t;
1545
1546 /* SCC Event and Mask registers when it is used as a UART.
1547 */
1548 #define UART_SCCM_GLR           ((ushort)0x1000)
1549 #define UART_SCCM_GLT           ((ushort)0x0800)
1550 #define UART_SCCM_AB            ((ushort)0x0200)
1551 #define UART_SCCM_IDL           ((ushort)0x0100)
1552 #define UART_SCCM_GRA           ((ushort)0x0080)
1553 #define UART_SCCM_BRKE          ((ushort)0x0040)
1554 #define UART_SCCM_BRKS          ((ushort)0x0020)
1555 #define UART_SCCM_CCR           ((ushort)0x0008)
1556 #define UART_SCCM_BSY           ((ushort)0x0004)
1557 #define UART_SCCM_TX            ((ushort)0x0002)
1558 #define UART_SCCM_RX            ((ushort)0x0001)
1559
1560 /* The SCC PSMR when used as a UART.
1561 */
1562 #define SCU_PSMR_FLC            ((ushort)0x8000)
1563 #define SCU_PSMR_SL             ((ushort)0x4000)
1564 #define SCU_PSMR_CL             ((ushort)0x3000)
1565 #define SCU_PSMR_UM             ((ushort)0x0c00)
1566 #define SCU_PSMR_FRZ            ((ushort)0x0200)
1567 #define SCU_PSMR_RZS            ((ushort)0x0100)
1568 #define SCU_PSMR_SYN            ((ushort)0x0080)
1569 #define SCU_PSMR_DRT            ((ushort)0x0040)
1570 #define SCU_PSMR_PEN            ((ushort)0x0010)
1571 #define SCU_PSMR_RPM            ((ushort)0x000c)
1572 #define SCU_PSMR_REVP           ((ushort)0x0008)
1573 #define SCU_PSMR_TPM            ((ushort)0x0003)
1574 #define SCU_PSMR_TEVP           ((ushort)0x0003)
1575
1576 /* CPM Transparent mode SCC.
1577  */
1578 typedef struct scc_trans {
1579         sccp_t  st_genscc;
1580         uint    st_cpres;       /* Preset CRC */
1581         uint    st_cmask;       /* Constant mask for CRC */
1582 } scc_trans_t;
1583
1584 #define BD_SCC_TX_LAST          ((ushort)0x0800)
1585
1586 /* IIC parameter RAM.
1587 */
1588 typedef struct iic {
1589         ushort  iic_rbase;      /* Rx Buffer descriptor base address */
1590         ushort  iic_tbase;      /* Tx Buffer descriptor base address */
1591         u_char  iic_rfcr;       /* Rx function code */
1592         u_char  iic_tfcr;       /* Tx function code */
1593         ushort  iic_mrblr;      /* Max receive buffer length */
1594         uint    iic_rstate;     /* Internal */
1595         uint    iic_rdp;        /* Internal */
1596         ushort  iic_rbptr;      /* Internal */
1597         ushort  iic_rbc;        /* Internal */
1598         uint    iic_rxtmp;      /* Internal */
1599         uint    iic_tstate;     /* Internal */
1600         uint    iic_tdp;        /* Internal */
1601         ushort  iic_tbptr;      /* Internal */
1602         ushort  iic_tbc;        /* Internal */
1603         uint    iic_txtmp;      /* Internal */
1604         uint    iic_res;        /* reserved */
1605         ushort  iic_rpbase;     /* Relocation pointer */
1606         ushort  iic_res2;       /* reserved */
1607 } iic_t;
1608
1609 /* SPI parameter RAM.
1610 */
1611 typedef struct spi {
1612         ushort  spi_rbase;      /* Rx Buffer descriptor base address */
1613         ushort  spi_tbase;      /* Tx Buffer descriptor base address */
1614         u_char  spi_rfcr;       /* Rx function code */
1615         u_char  spi_tfcr;       /* Tx function code */
1616         ushort  spi_mrblr;      /* Max receive buffer length */
1617         uint    spi_rstate;     /* Internal */
1618         uint    spi_rdp;        /* Internal */
1619         ushort  spi_rbptr;      /* Internal */
1620         ushort  spi_rbc;        /* Internal */
1621         uint    spi_rxtmp;      /* Internal */
1622         uint    spi_tstate;     /* Internal */
1623         uint    spi_tdp;        /* Internal */
1624         ushort  spi_tbptr;      /* Internal */
1625         ushort  spi_tbc;        /* Internal */
1626         uint    spi_txtmp;      /* Internal */
1627         uint    spi_res;
1628         ushort  spi_rpbase;     /* Relocation pointer */
1629         ushort  spi_res2;
1630 } spi_t;
1631
1632 /* SPI Mode register.
1633 */
1634 #define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
1635 #define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
1636 #define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
1637 #define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
1638 #define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
1639 #define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
1640 #define SPMODE_EN       ((ushort)0x0100)        /* Enable */
1641 #define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
1642 #define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
1643
1644 #define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
1645 #define SPMODE_PM(x)    ((x) &0xF)
1646
1647 /* HDLC parameter RAM.
1648 */
1649
1650 typedef struct hdlc_pram_s {
1651         /*
1652          * SCC parameter RAM
1653          */
1654         ushort  rbase;          /* Rx Buffer descriptor base address */
1655         ushort  tbase;          /* Tx Buffer descriptor base address */
1656         uchar   rfcr;           /* Rx function code */
1657         uchar   tfcr;           /* Tx function code */
1658         ushort  mrblr;          /* Rx buffer length */
1659         ulong   rstate;         /* Rx internal state */
1660         ulong   rptr;           /* Rx internal data pointer */
1661         ushort  rbptr;          /* rb BD Pointer */
1662         ushort  rcount;         /* Rx internal byte count */
1663         ulong   rtemp;          /* Rx temp */
1664         ulong   tstate;         /* Tx internal state */
1665         ulong   tptr;           /* Tx internal data pointer */
1666         ushort  tbptr;          /* Tx BD pointer */
1667         ushort  tcount;         /* Tx byte count */
1668         ulong   ttemp;          /* Tx temp */
1669         ulong   rcrc;           /* temp receive CRC */
1670         ulong   tcrc;           /* temp transmit CRC */
1671         /*
1672          * HDLC specific parameter RAM
1673          */
1674         uchar   res[4];         /* reserved */
1675         ulong   c_mask;         /* CRC constant */
1676         ulong   c_pres;         /* CRC preset */
1677         ushort  disfc;          /* discarded frame counter */
1678         ushort  crcec;          /* CRC error counter */
1679         ushort  abtsc;          /* abort sequence counter */
1680         ushort  nmarc;          /* nonmatching address rx cnt */
1681         ushort  retrc;          /* frame retransmission cnt */
1682         ushort  mflr;           /* maximum frame length reg */
1683         ushort  max_cnt;        /* maximum length counter */
1684         ushort  rfthr;          /* received frames threshold */
1685         ushort  rfcnt;          /* received frames count */
1686         ushort  hmask;          /* user defined frm addr mask */
1687         ushort  haddr1;         /* user defined frm address 1 */
1688         ushort  haddr2;         /* user defined frm address 2 */
1689         ushort  haddr3;         /* user defined frm address 3 */
1690         ushort  haddr4;         /* user defined frm address 4 */
1691         ushort  tmp;            /* temp */
1692         ushort  tmp_mb;         /* temp */
1693 } hdlc_pram_t;
1694
1695 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
1696  * channels or devices.  All of these are presented to the PPC core
1697  * as a single interrupt.  The CPM interrupt handler dispatches its
1698  * own handlers, in a similar fashion to the PPC core handler.  We
1699  * use the table as defined in the manuals (i.e. no special high
1700  * priority and SCC1 == SCCa, etc...).
1701  */
1702 #define CPMVEC_NR               32
1703 #define CPMVEC_OFFSET           0x00010000
1704 #define CPMVEC_PIO_PC15         ((ushort)0x1f | CPMVEC_OFFSET)
1705 #define CPMVEC_SCC1             ((ushort)0x1e | CPMVEC_OFFSET)
1706 #define CPMVEC_SCC2             ((ushort)0x1d | CPMVEC_OFFSET)
1707 #define CPMVEC_SCC3             ((ushort)0x1c | CPMVEC_OFFSET)
1708 #define CPMVEC_SCC4             ((ushort)0x1b | CPMVEC_OFFSET)
1709 #define CPMVEC_PIO_PC14         ((ushort)0x1a | CPMVEC_OFFSET)
1710 #define CPMVEC_TIMER1           ((ushort)0x19 | CPMVEC_OFFSET)
1711 #define CPMVEC_PIO_PC13         ((ushort)0x18 | CPMVEC_OFFSET)
1712 #define CPMVEC_PIO_PC12         ((ushort)0x17 | CPMVEC_OFFSET)
1713 #define CPMVEC_SDMA_CB_ERR      ((ushort)0x16 | CPMVEC_OFFSET)
1714 #define CPMVEC_IDMA1            ((ushort)0x15 | CPMVEC_OFFSET)
1715 #define CPMVEC_IDMA2            ((ushort)0x14 | CPMVEC_OFFSET)
1716 #define CPMVEC_TIMER2           ((ushort)0x12 | CPMVEC_OFFSET)
1717 #define CPMVEC_RISCTIMER        ((ushort)0x11 | CPMVEC_OFFSET)
1718 #define CPMVEC_I2C              ((ushort)0x10 | CPMVEC_OFFSET)
1719 #define CPMVEC_PIO_PC11         ((ushort)0x0f | CPMVEC_OFFSET)
1720 #define CPMVEC_PIO_PC10         ((ushort)0x0e | CPMVEC_OFFSET)
1721 #define CPMVEC_TIMER3           ((ushort)0x0c | CPMVEC_OFFSET)
1722 #define CPMVEC_PIO_PC9          ((ushort)0x0b | CPMVEC_OFFSET)
1723 #define CPMVEC_PIO_PC8          ((ushort)0x0a | CPMVEC_OFFSET)
1724 #define CPMVEC_PIO_PC7          ((ushort)0x09 | CPMVEC_OFFSET)
1725 #define CPMVEC_TIMER4           ((ushort)0x07 | CPMVEC_OFFSET)
1726 #define CPMVEC_PIO_PC6          ((ushort)0x06 | CPMVEC_OFFSET)
1727 #define CPMVEC_SPI              ((ushort)0x05 | CPMVEC_OFFSET)
1728 #define CPMVEC_SMC1             ((ushort)0x04 | CPMVEC_OFFSET)
1729 #define CPMVEC_SMC2             ((ushort)0x03 | CPMVEC_OFFSET)
1730 #define CPMVEC_PIO_PC5          ((ushort)0x02 | CPMVEC_OFFSET)
1731 #define CPMVEC_PIO_PC4          ((ushort)0x01 | CPMVEC_OFFSET)
1732 #define CPMVEC_ERROR            ((ushort)0x00 | CPMVEC_OFFSET)
1733
1734 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1735
1736 /* CPM interrupt configuration vector.
1737 */
1738 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
1739 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
1740 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
1741 #define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
1742 #define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrrupt */
1743 #define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
1744 #define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
1745 #define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
1746 #endif /* __CPM_8XX__ */