include/commproc.h

   1 /*
   2  * MPC8xx Communication Processor Module.
   3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   4  *
   5  * This file contains structures and information for the communication
   6  * processor channels.  Some CPM control and status is available
   7  * throught the MPC8xx internal memory map.  See immap.h for details.
   8  * This file only contains what I need for the moment, not the total
   9  * CPM capabilities.  I (or someone else) will add definitions as they
  10  * are needed.  -- Dan
  11  *
  12  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  13  * bytes of the DP RAM and relocates the I2C parameter area to the
  14  * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  15  * or other use.
  16  */
  17 #ifndef __CPM_8XX__
  18 #define __CPM_8XX__
  19
  20 #include <linux/config.h>
  21 #include <asm/8xx_immap.h>
  22
  23 /* CPM Command register.
  24 */
  25 #define CPM_CR_RST              ((ushort)0x8000)
  26 #define CPM_CR_OPCODE           ((ushort)0x0f00)
  27 #define CPM_CR_CHAN             ((ushort)0x00f0)
  28 #define CPM_CR_FLG              ((ushort)0x0001)
  29
  30 /* Some commands (there are more...later)
  31 */
  32 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
  33 #define CPM_CR_INIT_RX          ((ushort)0x0001)
  34 #define CPM_CR_INIT_TX          ((ushort)0x0002)
  35 #define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  36 #define CPM_CR_STOP_TX          ((ushort)0x0004)
  37 #define CPM_CR_RESTART_TX       ((ushort)0x0006)
  38 #define CPM_CR_SET_GADDR        ((ushort)0x0008)
  39
  40 /* Channel numbers.
  41 */
  42 #define CPM_CR_CH_SCC1          ((ushort)0x0000)
  43 #define CPM_CR_CH_I2C           ((ushort)0x0001)    /* I2C and IDMA1 */
  44 #define CPM_CR_CH_SCC2          ((ushort)0x0004)
  45 #define CPM_CR_CH_SPI           ((ushort)0x0005)    /* SPI/IDMA2/Timers */
  46 #define CPM_CR_CH_SCC3          ((ushort)0x0008)
  47 #define CPM_CR_CH_SMC1          ((ushort)0x0009)    /* SMC1 / DSP1 */
  48 #define CPM_CR_CH_SCC4          ((ushort)0x000c)
  49 #define CPM_CR_CH_SMC2          ((ushort)0x000d)    /* SMC2 / DSP2 */
  50
  51 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  52
  53 /*
  54  * DPRAM defines and allocation functions
  55  */
  56
  57 /* The dual ported RAM is multi-functional.  Some areas can be (and are
  58  * being) used for microcode.  There is an area that can only be used
  59  * as data ram for buffer descriptors, which is all we use right now.
  60  * Currently the first 512 and last 256 bytes are used for microcode.
  61  */
  62 #ifdef  CFG_ALLOC_DPRAM
  63
  64 #define CPM_DATAONLY_BASE       ((uint)0x0800)
  65 #define CPM_DATAONLY_SIZE       ((uint)0x0700)
  66 #define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  67
  68 #else
  69
  70 #define CPM_SERIAL_BASE         0x0800
  71 #define CPM_I2C_BASE            0x0820
  72 #define CPM_SPI_BASE            0x0840
  73 #define CPM_FEC_BASE            0x0860
  74 #define CPM_WLKBD_BASE          0x0880
  75 #define CPM_SCC_BASE            0x0900
  76 #define CPM_POST_BASE           0x0980
  77
  78 #endif
  79
  80 #ifndef CFG_CPM_POST_WORD_ADDR
  81 #define CPM_POST_WORD_ADDR      0x07FC
  82 #else
  83 #define CPM_POST_WORD_ADDR      CFG_CPM_POST_WORD_ADDR
  84 #endif
  85
  86 #define BD_IIC_START    ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
  87
  88 /* Export the base address of the communication processor registers
  89  * and dual port ram.
  90  */
  91 extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
  92
  93 /* Buffer descriptors used by many of the CPM protocols.
  94 */
  95 typedef struct cpm_buf_desc {
  96         ushort  cbd_sc;         /* Status and Control */
  97         ushort  cbd_datlen;     /* Data length in buffer */
  98         uint    cbd_bufaddr;    /* Buffer address in host memory */
  99 } cbd_t;
 100
 101 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Recieve is empty */
 102 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
 103 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
 104 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
 105 #define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
 106 #define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
 107 #define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
 108 #define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
 109 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
 110 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
 111 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
 112 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
 113 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
 114 #define BD_SC_CD        ((ushort)0x0001)        /* Carrier Detect lost */
 115
 116 /* Parameter RAM offsets.
 117 */
 118 #define PROFF_SCC1      ((uint)0x0000)
 119 #define PROFF_IIC       ((uint)0x0080)
 120 #define PROFF_SCC2      ((uint)0x0100)
 121 #define PROFF_SPI       ((uint)0x0180)
 122 #define PROFF_SCC3      ((uint)0x0200)
 123 #define PROFF_SMC1      ((uint)0x0280)
 124 #define PROFF_SCC4      ((uint)0x0300)
 125 #define PROFF_SMC2      ((uint)0x0380)
 126
 127 /* Define enough so I can at least use the serial port as a UART.
 128  * The MBX uses SMC1 as the host serial port.
 129  */
 130 typedef struct smc_uart {
 131         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 132         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 133         u_char  smc_rfcr;       /* Rx function code */
 134         u_char  smc_tfcr;       /* Tx function code */
 135         ushort  smc_mrblr;      /* Max receive buffer length */
 136         uint    smc_rstate;     /* Internal */
 137         uint    smc_idp;        /* Internal */
 138         ushort  smc_rbptr;      /* Internal */
 139         ushort  smc_ibc;        /* Internal */
 140         uint    smc_rxtmp;      /* Internal */
 141         uint    smc_tstate;     /* Internal */
 142         uint    smc_tdp;        /* Internal */
 143         ushort  smc_tbptr;      /* Internal */
 144         ushort  smc_tbc;        /* Internal */
 145         uint    smc_txtmp;      /* Internal */
 146         ushort  smc_maxidl;     /* Maximum idle characters */
 147         ushort  smc_tmpidl;     /* Temporary idle counter */
 148         ushort  smc_brklen;     /* Last received break length */
 149         ushort  smc_brkec;      /* rcv'd break condition counter */
 150         ushort  smc_brkcr;      /* xmt break count register */
 151         ushort  smc_rmask;      /* Temporary bit mask */
 152 } smc_uart_t;
 153
 154 /* Function code bits.
 155 */
 156 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 157
 158 /* SMC uart mode register.
 159 */
 160 #define SMCMR_REN       ((ushort)0x0001)
 161 #define SMCMR_TEN       ((ushort)0x0002)
 162 #define SMCMR_DM        ((ushort)0x000c)
 163 #define SMCMR_SM_GCI    ((ushort)0x0000)
 164 #define SMCMR_SM_UART   ((ushort)0x0020)
 165 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 166 #define SMCMR_SM_MASK   ((ushort)0x0030)
 167 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 168 #define SMCMR_REVD      SMCMR_PM_EVEN
 169 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 170 #define SMCMR_BS        SMCMR_PEN
 171 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 172 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 173 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 174
 175 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
 176  * it can only receive or transmit.  The parameter ram values for
 177  * each direction are either unique or properly overlap, so we can
 178  * include them in one structure.
 179  */
 180 typedef struct smc_centronics {
 181         ushort  scent_rbase;
 182         ushort  scent_tbase;
 183         u_char  scent_cfcr;
 184         u_char  scent_smask;
 185         ushort  scent_mrblr;
 186         uint    scent_rstate;
 187         uint    scent_r_ptr;
 188         ushort  scent_rbptr;
 189         ushort  scent_r_cnt;
 190         uint    scent_rtemp;
 191         uint    scent_tstate;
 192         uint    scent_t_ptr;
 193         ushort  scent_tbptr;
 194         ushort  scent_t_cnt;
 195         uint    scent_ttemp;
 196         ushort  scent_max_sl;
 197         ushort  scent_sl_cnt;
 198         ushort  scent_character1;
 199         ushort  scent_character2;
 200         ushort  scent_character3;
 201         ushort  scent_character4;
 202         ushort  scent_character5;
 203         ushort  scent_character6;
 204         ushort  scent_character7;
 205         ushort  scent_character8;
 206         ushort  scent_rccm;
 207         ushort  scent_rccr;
 208 } smc_cent_t;
 209
 210 /* Centronics Status Mask Register.
 211 */
 212 #define SMC_CENT_F      ((u_char)0x08)
 213 #define SMC_CENT_PE     ((u_char)0x04)
 214 #define SMC_CENT_S      ((u_char)0x02)
 215
 216 /* SMC Event and Mask register.
 217 */
 218 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 219 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 220 #define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 221 #define SMCM_BSY        ((unsigned char)0x04)
 222 #define SMCM_TX         ((unsigned char)0x02)
 223 #define SMCM_RX         ((unsigned char)0x01)
 224
 225 /* Baud rate generators.
 226 */
 227 #define CPM_BRG_RST             ((uint)0x00020000)
 228 #define CPM_BRG_EN              ((uint)0x00010000)
 229 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 230 #define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 231 #define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 232 #define CPM_BRG_ATB             ((uint)0x00002000)
 233 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 234 #define CPM_BRG_DIV16           ((uint)0x00000001)
 235
 236 /* SI Clock Route Register
 237 */
 238 #define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 239 #define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 240 #define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 241 #define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 242 #define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 243 #define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 244 #define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 245 #define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 246
 247 /* SCCs.
 248 */
 249 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 250 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 251 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 252 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 253 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 254 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 255 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 256 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 257 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 258 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 259 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 260 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 261 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 262 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 263 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 264 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 265 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 266 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 267 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 268 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 269
 270 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 271 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 272 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 273 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 274 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 275 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 276 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 277 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 278 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 279 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 280 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 281 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 282 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 283 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 284 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 285 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 286 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 287 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 288 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 289 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 290 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 291 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 292 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 293 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 294 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 295 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 296 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 297 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 298 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 299 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 300 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 301 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 302 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 303 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 304 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 305 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 306 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 307 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 308 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 309 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 310 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 311 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 312 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 313 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 314 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 315 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 316 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 317 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 318 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 319 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 320 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 321 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 322 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 323 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 324 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 325 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 326 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 327 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 328
 329 #define SCC_TODR_TOD            ((ushort)0x8000)
 330
 331 /* SCC Event and Mask register.
 332 */
 333 #define SCCM_TXE        ((unsigned char)0x10)
 334 #define SCCM_BSY        ((unsigned char)0x04)
 335 #define SCCM_TX         ((unsigned char)0x02)
 336 #define SCCM_RX         ((unsigned char)0x01)
 337
 338 typedef struct scc_param {
 339         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 340         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 341         u_char  scc_rfcr;       /* Rx function code */
 342         u_char  scc_tfcr;       /* Tx function code */
 343         ushort  scc_mrblr;      /* Max receive buffer length */
 344         uint    scc_rstate;     /* Internal */
 345         uint    scc_idp;        /* Internal */
 346         ushort  scc_rbptr;      /* Internal */
 347         ushort  scc_ibc;        /* Internal */
 348         uint    scc_rxtmp;      /* Internal */
 349         uint    scc_tstate;     /* Internal */
 350         uint    scc_tdp;        /* Internal */
 351         ushort  scc_tbptr;      /* Internal */
 352         ushort  scc_tbc;        /* Internal */
 353         uint    scc_txtmp;      /* Internal */
 354         uint    scc_rcrc;       /* Internal */
 355         uint    scc_tcrc;       /* Internal */
 356 } sccp_t;
 357
 358 /* Function code bits.
 359 */
 360 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 361
 362 /* CPM Ethernet through SCCx.
 363  */
 364 typedef struct scc_enet {
 365         sccp_t  sen_genscc;
 366         uint    sen_cpres;      /* Preset CRC */
 367         uint    sen_cmask;      /* Constant mask for CRC */
 368         uint    sen_crcec;      /* CRC Error counter */
 369         uint    sen_alec;       /* alignment error counter */
 370         uint    sen_disfc;      /* discard frame counter */
 371         ushort  sen_pads;       /* Tx short frame pad character */
 372         ushort  sen_retlim;     /* Retry limit threshold */
 373         ushort  sen_retcnt;     /* Retry limit counter */
 374         ushort  sen_maxflr;     /* maximum frame length register */
 375         ushort  sen_minflr;     /* minimum frame length register */
 376         ushort  sen_maxd1;      /* maximum DMA1 length */
 377         ushort  sen_maxd2;      /* maximum DMA2 length */
 378         ushort  sen_maxd;       /* Rx max DMA */
 379         ushort  sen_dmacnt;     /* Rx DMA counter */
 380         ushort  sen_maxb;       /* Max BD byte count */
 381         ushort  sen_gaddr1;     /* Group address filter */
 382         ushort  sen_gaddr2;
 383         ushort  sen_gaddr3;
 384         ushort  sen_gaddr4;
 385         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 386         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 387         uint    sen_tbuf0rba;   /* Internal */
 388         uint    sen_tbuf0crc;   /* Internal */
 389         ushort  sen_tbuf0bcnt;  /* Internal */
 390         ushort  sen_paddrh;     /* physical address (MSB) */
 391         ushort  sen_paddrm;
 392         ushort  sen_paddrl;     /* physical address (LSB) */
 393         ushort  sen_pper;       /* persistence */
 394         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 395         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 396         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 397         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 398         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 399         uint    sen_tbuf1rba;   /* Internal */
 400         uint    sen_tbuf1crc;   /* Internal */
 401         ushort  sen_tbuf1bcnt;  /* Internal */
 402         ushort  sen_txlen;      /* Tx Frame length counter */
 403         ushort  sen_iaddr1;     /* Individual address filter */
 404         ushort  sen_iaddr2;
 405         ushort  sen_iaddr3;
 406         ushort  sen_iaddr4;
 407         ushort  sen_boffcnt;    /* Backoff counter */
 408
 409         /* NOTE: Some versions of the manual have the following items
 410          * incorrectly documented.  Below is the proper order.
 411          */
 412         ushort  sen_taddrh;     /* temp address (MSB) */
 413         ushort  sen_taddrm;
 414         ushort  sen_taddrl;     /* temp address (LSB) */
 415 } scc_enet_t;
 416
 417 /**********************************************************************
 418  *
 419  * Board specific configuration settings.
 420  *
 421  * Please note that we use the presence of a #define SCC_ENET and/or
 422  * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
 423  **********************************************************************/
 424
 425
 426 /***  ADS  *************************************************************/
 427
 428 #if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
 429 /* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
 430  */
 431
 432 #define PROFF_ENET      PROFF_SCC1
 433 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 434 #define SCC_ENET        0
 435
 436 #define PA_ENET_RXD     ((ushort)0x0001)
 437 #define PA_ENET_TXD     ((ushort)0x0002)
 438 #define PA_ENET_TCLK    ((ushort)0x0100)
 439 #define PA_ENET_RCLK    ((ushort)0x0200)
 440
 441 #define PB_ENET_TENA    ((uint)0x00001000)
 442
 443 #define PC_ENET_CLSN    ((ushort)0x0010)
 444 #define PC_ENET_RENA    ((ushort)0x0020)
 445
 446 #define SICR_ENET_MASK  ((uint)0x000000ff)
 447 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 448
 449 /* 68160 PHY control */
 450
 451 #define PC_ENET_ETHLOOP ((ushort)0x0800)
 452 #define PC_ENET_TPFLDL  ((ushort)0x0400)
 453 #define PC_ENET_TPSQEL  ((ushort)0x0200)
 454
 455 #endif  /* MPC860ADS */
 456
 457 /***  AMX860  **********************************************/
 458
 459 #if defined(CONFIG_AMX860)
 460
 461 /* This ENET stuff is for the AMX860 with ethernet on SCC1.
 462  */
 463
 464 #define PROFF_ENET      PROFF_SCC1
 465 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 466 #define SCC_ENET        0
 467
 468 #define PA_ENET_RXD     ((ushort)0x0001)
 469 #define PA_ENET_TXD     ((ushort)0x0002)
 470 #define PA_ENET_TCLK    ((ushort)0x0400)
 471 #define PA_ENET_RCLK    ((ushort)0x0800)
 472
 473 #define PB_ENET_TENA    ((uint)0x00001000)
 474
 475 #define PC_ENET_CLSN    ((ushort)0x0010)
 476 #define PC_ENET_RENA    ((ushort)0x0020)
 477
 478 #define SICR_ENET_MASK  ((uint)0x000000ff)
 479 #define SICR_ENET_CLKRT ((uint)0x0000003e)
 480
 481 /* 68160 PHY control */
 482
 483 #define PB_ENET_ETHLOOP ((uint)0x00020000)
 484 #define PB_ENET_TPFLDL  ((uint)0x00010000)
 485 #define PB_ENET_TPSQEL  ((uint)0x00008000)
 486 #define PD_ENET_ETH_EN  ((ushort)0x0004)
 487
 488 #endif  /* CONFIG_AMX860 */
 489
 490 /***  BSEIP  **********************************************************/
 491
 492 #ifdef CONFIG_BSEIP
 493 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
 494  * This is unique to the BSE ip-Engine board.
 495  */
 496 #define PROFF_ENET      PROFF_SCC2
 497 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 498 #define SCC_ENET        1
 499 #define PA_ENET_RXD     ((ushort)0x0004)
 500 #define PA_ENET_TXD     ((ushort)0x0008)
 501 #define PA_ENET_TCLK    ((ushort)0x0100)
 502 #define PA_ENET_RCLK    ((ushort)0x0200)
 503 #define PB_ENET_TENA    ((uint)0x00002000)
 504 #define PC_ENET_CLSN    ((ushort)0x0040)
 505 #define PC_ENET_RENA    ((ushort)0x0080)
 506
 507 /* BSE uses port B and C bits for PHY control also.
 508 */
 509 #define PB_BSE_POWERUP  ((uint)0x00000004)
 510 #define PB_BSE_FDXDIS   ((uint)0x00008000)
 511 #define PC_BSE_LOOPBACK ((ushort)0x0800)
 512
 513 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 514 #define SICR_ENET_CLKRT ((uint)0x00002c00)
 515 #endif  /* CONFIG_BSEIP */
 516
 517 /***  BSEIP  **********************************************************/
 518
 519 #ifdef CONFIG_FLAGADM
 520 /* Enet configuration for the FLAGADM */
 521 /* Enet on SCC2 */
 522
 523 #define PROFF_ENET      PROFF_SCC2
 524 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 525 #define SCC_ENET        1
 526 #define PA_ENET_RXD     ((ushort)0x0004)
 527 #define PA_ENET_TXD     ((ushort)0x0008)
 528 #define PA_ENET_TCLK    ((ushort)0x0100)
 529 #define PA_ENET_RCLK    ((ushort)0x0400)
 530 #define PB_ENET_TENA    ((uint)0x00002000)
 531 #define PC_ENET_CLSN    ((ushort)0x0040)
 532 #define PC_ENET_RENA    ((ushort)0x0080)
 533
 534 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 535 #define SICR_ENET_CLKRT ((uint)0x00003400)
 536 #endif  /* CONFIG_FLAGADM */
 537
 538 /***  C2MON  **********************************************************/
 539
 540 #ifdef CONFIG_C2MON
 541
 542 # ifndef CONFIG_FEC_ENET        /* use SCC for 10Mbps Ethernet  */
 543 #  error "Ethernet on SCC not supported on C2MON Board!"
 544 # else                          /* Use FEC for Fast Ethernet */
 545
 546 #undef  SCC_ENET
 547 #define FEC_ENET
 548
 549 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 550 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 551 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 552 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 553 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 554 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 555 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 556 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 557 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 558 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 559 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 560 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 561 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 562
 563 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 564
 565 # endif /* CONFIG_FEC_ENET */
 566 #endif  /* CONFIG_C2MON */
 567
 568 /*********************************************************************/
 569
 570
 571 /***  CCM  and  PCU E  ***********************************************/
 572
 573 /* The PCU E  and  CCM  use the FEC on a MPC860T for Ethernet */
 574
 575 #if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
 576
 577 #define FEC_ENET        /* use FEC for EThernet */
 578 #undef  SCC_ENET
 579
 580 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 581 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 582 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 583 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 584 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 585 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 586 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 587 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 588 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 589 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 590 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 591 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 592 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 593
 594 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 595
 596 #endif  /* CONFIG_PCU_E, CONFIG_CCM */
 597
 598 /***  ELPT860 *********************************************************/
 599
 600 #ifdef CONFIG_ELPT860
 601 /* Bits in parallel I/O port registers that have to be set/cleared
 602  * to configure the pins for SCC1 use.
 603  */
 604 #  define PROFF_ENET        PROFF_SCC1
 605 #  define CPM_CR_ENET       CPM_CR_CH_SCC1
 606 #  define SCC_ENET          0
 607
 608 #  define PA_ENET_RXD       ((ushort)0x0001)    /* PA 15 */
 609 #  define PA_ENET_TXD       ((ushort)0x0002)    /* PA 14 */
 610 #  define PA_ENET_RCLK      ((ushort)0x0100)    /* PA  7 */
 611 #  define PA_ENET_TCLK      ((ushort)0x0200)    /* PA  6 */
 612
 613 #  define PC_ENET_TENA      ((ushort)0x0001)    /* PC 15 */
 614 #  define PC_ENET_CLSN      ((ushort)0x0010)    /* PC 11 */
 615 #  define PC_ENET_RENA      ((ushort)0x0020)    /* PC 10 */
 616
 617 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
 618  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 619  */
 620 #  define SICR_ENET_MASK    ((uint)0x000000FF)
 621 #  define SICR_ENET_CLKRT   ((uint)0x00000025)
 622 #endif  /* CONFIG_ELPT860 */
 623
 624 /***  ESTEEM 192E  **************************************************/
 625 #ifdef CONFIG_ESTEEM192E
 626 /* ESTEEM192E
 627  * This ENET stuff is for the MPC850 with ethernet on SCC2. This
 628  * is very similar to the RPX-Lite configuration.
 629  * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
 630  */
 631
 632 #define PROFF_ENET      PROFF_SCC2
 633 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 634 #define SCC_ENET        1
 635
 636 #define PA_ENET_RXD     ((ushort)0x0004)
 637 #define PA_ENET_TXD     ((ushort)0x0008)
 638 #define PA_ENET_TCLK    ((ushort)0x0200)
 639 #define PA_ENET_RCLK    ((ushort)0x0800)
 640 #define PB_ENET_TENA    ((uint)0x00002000)
 641 #define PC_ENET_CLSN    ((ushort)0x0040)
 642 #define PC_ENET_RENA    ((ushort)0x0080)
 643
 644 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 645 #define SICR_ENET_CLKRT ((uint)0x00003d00)
 646
 647 #define PB_ENET_LOOPBACK ((uint)0x00004000)
 648 #define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
 649
 650 #endif
 651
 652 /***  FADS823  ********************************************************/
 653
 654 #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
 655 /* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
 656  */
 657 #ifdef CONFIG_SCC2_ENET
 658 #define PROFF_ENET      PROFF_SCC2
 659 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 660 #define SCC_ENET        1
 661 #define CPMVEC_ENET     CPMVEC_SCC2
 662 #endif
 663
 664 #ifdef CONFIG_SCC1_ENET
 665 #define PROFF_ENET      PROFF_SCC1
 666 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 667 #define SCC_ENET        0
 668 #define CPMVEC_ENET     CPMVEC_SCC1
 669 #endif
 670
 671 #define PA_ENET_RXD     ((ushort)0x0004)
 672 #define PA_ENET_TXD     ((ushort)0x0008)
 673 #define PA_ENET_TCLK    ((ushort)0x0400)
 674 #define PA_ENET_RCLK    ((ushort)0x0200)
 675
 676 #define PB_ENET_TENA    ((uint)0x00002000)
 677
 678 #define PC_ENET_CLSN    ((ushort)0x0040)
 679 #define PC_ENET_RENA    ((ushort)0x0080)
 680
 681 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 682 #define SICR_ENET_CLKRT ((uint)0x00002e00)
 683
 684 #endif  /* CONFIG_FADS823FADS */
 685
 686 /***  FADS850SAR  ********************************************************/
 687
 688 #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
 689 /* This ENET stuff is for the MPC850SAR with ethernet on SCC2.  Some of
 690  * this may be unique to the FADS850SAR configuration.
 691  * Note TENA is on Port B.
 692  */
 693 #define PROFF_ENET      PROFF_SCC2
 694 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 695 #define SCC_ENET        1
 696 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 697 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 698 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA 6 */
 699 #define PA_ENET_TCLK    ((ushort)0x0800)        /* PA 4 */
 700 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 701 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC 9 */
 702 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC 8 */
 703
 704 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 705 #define SICR_ENET_CLKRT ((uint)0x00002f00)      /* RCLK-CLK2, TCLK-CLK4 */
 706 #endif  /* CONFIG_FADS850SAR */
 707
 708 /***  FADS860T********************************************************/
 709
 710 #if defined(CONFIG_MPC860T) && defined(CONFIG_FADS)
 711 /* This ENET stuff is for the MPC860TFADS with ethernet on SCC1.
 712  */
 713
 714 #ifdef CONFIG_SCC1_ENET
 715 #define SCC_ENET        0
 716 #endif  /* CONFIG_SCC1_ETHERNET */
 717 #define PROFF_ENET      PROFF_SCC1
 718 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 719
 720 #define PA_ENET_RXD     ((ushort)0x0001)
 721 #define PA_ENET_TXD     ((ushort)0x0002)
 722 #define PA_ENET_TCLK    ((ushort)0x0100)
 723 #define PA_ENET_RCLK    ((ushort)0x0200)
 724
 725 #define PB_ENET_TENA    ((uint)0x00001000)
 726
 727 #define PC_ENET_CLSN    ((ushort)0x0010)
 728 #define PC_ENET_RENA    ((ushort)0x0020)
 729
 730 #define SICR_ENET_MASK  ((uint)0x000000ff)
 731 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 732
 733 /* This ENET stuff is for the MPC860TFADS with ethernet on FEC.
 734  */
 735
 736 #ifdef CONFIG_FEC_ENET
 737 #define FEC_ENET        /* use FEC for EThernet */
 738 #endif  /* CONFIG_FEC_ETHERNET */
 739
 740 #endif  /* CONFIG_FADS860T */
 741
 742 /***  FPS850L, FPS860L  ************************************************/
 743
 744 #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
 745 /* Bits in parallel I/O port registers that have to be set/cleared
 746  * to configure the pins for SCC2 use.
 747  */
 748 #define PROFF_ENET      PROFF_SCC2
 749 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 750 #define SCC_ENET        1
 751 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 752 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 753 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 754 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 755
 756 #define PC_ENET_TENA    ((ushort)0x0002)        /* PC 14 */
 757 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 758 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 759
 760 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 761  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 762  */
 763 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 764 #define SICR_ENET_CLKRT ((uint)0x00002600)
 765 #endif  /* CONFIG_FPS850L, CONFIG_FPS860L */
 766
 767 /*** GEN860T **********************************************************/
 768 #if defined(CONFIG_GEN860T)
 769 #undef  SCC_ENET
 770 #define FEC_ENET
 771
 772 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3        */
 773 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4        */
 774 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5        */
 775 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6        */
 776 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7        */
 777 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8        */
 778 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9        */
 779 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10        */
 780 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11        */
 781 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12        */
 782 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13        */
 783 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14        */
 784 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15        */
 785 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3-15      */
 786 #endif  /* CONFIG_GEN860T */
 787
 788 /***  GENIETV  ********************************************************/
 789
 790 #if defined(CONFIG_GENIETV)
 791 /* Ethernet is only on SCC2 */
 792
 793 #define CONFIG_SCC2_ENET
 794 #define PROFF_ENET      PROFF_SCC2
 795 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 796 #define SCC_ENET        1
 797 #define CPMVEC_ENET     CPMVEC_SCC2
 798
 799 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 800 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 801 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 802 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 803
 804 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 805
 806 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 807 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 808
 809 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 810 #define SICR_ENET_CLKRT ((uint)0x00002e00)
 811
 812 #endif  /* CONFIG_GENIETV */
 813
 814 /*** GTH ******************************************************/
 815
 816 #ifdef CONFIG_GTH
 817 #ifdef CONFIG_FEC_ENET
 818 #define FEC_ENET        /* use FEC for EThernet */
 819 #endif  /* CONFIG_FEC_ETHERNET */
 820
 821 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */
 822 #define PROFF_ENET      PROFF_SCC1
 823 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 824 #define SCC_ENET        0
 825
 826 #define PA_ENET_RXD     ((ushort)0x0001) /* PA15 */
 827 #define PA_ENET_TXD     ((ushort)0x0002) /* PA14 */
 828 #define PA_ENET_TCLK    ((ushort)0x0800) /* PA4 */
 829 #define PA_ENET_RCLK    ((ushort)0x0400) /* PA5 */
 830
 831 #define PB_ENET_TENA    ((uint)0x00001000) /* PB19 */
 832
 833 #define PC_ENET_CLSN    ((ushort)0x0010) /* PC11 */
 834 #define PC_ENET_RENA    ((ushort)0x0020) /* PC10 */
 835
 836 /* NOTE. This is reset for 10Mbit port only */
 837 #define PC_ENET_RESET   ((ushort)0x0100)        /* PC 7 */
 838
 839 #define SICR_ENET_MASK  ((uint)0x000000ff)
 840
 841 /* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
 842 #define SICR_ENET_CLKRT ((uint)0x00000037)
 843
 844 #endif  /* CONFIG_GTH */
 845
 846 /*** HERMES-PRO ******************************************************/
 847
 848 /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
 849
 850 #ifdef CONFIG_HERMES
 851
 852 #define FEC_ENET        /* use FEC for EThernet */
 853 #undef  SCC_ENET
 854
 855
 856 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 857 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 858 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 859 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 860 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 861 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 862 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 863 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 864 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 865 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 866 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 867 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 868 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 869
 870 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 871
 872 #endif  /* CONFIG_HERMES */
 873
 874 /***  IAD210  **********************************************************/
 875
 876 /* The IAD210 uses the FEC on a MPC860P for Ethernet */
 877
 878 #if defined(CONFIG_IAD210)
 879
 880 # define  FEC_ENET    /* use FEC for Ethernet */
 881 # undef   SCC_ENET
 882
 883 # define PD_MII_TXD1    ((ushort) 0x1000 )      /* PD  3 */
 884 # define PD_MII_TXD2    ((ushort) 0x0800 )      /* PD  4 */
 885 # define PD_MII_TXD3    ((ushort) 0x0400 )      /* PD  5 */
 886 # define PD_MII_RX_DV   ((ushort) 0x0200 )      /* PD  6 */
 887 # define PD_MII_RX_ERR  ((ushort) 0x0100 )      /* PD  7 */
 888 # define PD_MII_RX_CLK  ((ushort) 0x0080 )      /* PD  8 */
 889 # define PD_MII_TXD0    ((ushort) 0x0040 )      /* PD  9 */
 890 # define PD_MII_RXD0    ((ushort) 0x0020 )      /* PD 10 */
 891 # define PD_MII_TX_ERR  ((ushort) 0x0010 )      /* PD 11 */
 892 # define PD_MII_MDC     ((ushort) 0x0008 )      /* PD 12 */
 893 # define PD_MII_RXD1    ((ushort) 0x0004 )      /* PD 13 */
 894 # define PD_MII_RXD2    ((ushort) 0x0002 )      /* PD 14 */
 895 # define PD_MII_RXD3    ((ushort) 0x0001 )      /* PD 15 */
 896
 897 # define PD_MII_MASK    ((ushort) 0x1FFF )   /* PD 3...15 */
 898
 899 #endif  /* CONFIG_IAD210 */
 900
 901 /*** ICU862  **********************************************************/
 902
 903 #if defined(CONFIG_ICU862)
 904
 905 #ifdef CONFIG_FEC_ENET
 906 #define FEC_ENET        /* use FEC for EThernet */
 907 #endif  /* CONFIG_FEC_ETHERNET */
 908
 909 #endif /* CONFIG_ICU862 */
 910
 911 /***  IP860  **********************************************************/
 912
 913 #if defined(CONFIG_IP860)
 914 /* Bits in parallel I/O port registers that have to be set/cleared
 915  * to configure the pins for SCC1 use.
 916  */
 917 #define PROFF_ENET      PROFF_SCC1
 918 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 919 #define SCC_ENET        0
 920 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
 921 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
 922 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 923 #define PA_ENET_TCLK    ((ushort)0x0100)        /* PA  7 */
 924
 925 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
 926 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
 927 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
 928
 929 #define PB_ENET_RESET   (uint)0x00000008        /* PB 28 */
 930 #define PB_ENET_JABD    (uint)0x00000004        /* PB 29 */
 931
 932 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 933  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 934  */
 935 #define SICR_ENET_MASK  ((uint)0x000000ff)
 936 #define SICR_ENET_CLKRT ((uint)0x0000002C)
 937 #endif  /* CONFIG_IP860 */
 938
 939 /*** IVMS8  **********************************************************/
 940
 941 /* The IVMS8 uses the FEC on a MPC860T for Ethernet */
 942
 943 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
 944
 945 #define FEC_ENET        /* use FEC for EThernet */
 946 #undef  SCC_ENET
 947
 948 #define PB_ENET_POWER   ((uint)0x00010000)      /* PB 15 */
 949
 950 #define PC_ENET_RESET   ((ushort)0x0010)        /* PC 11 */
 951
 952 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 953 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 954 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 955 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 956 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 957 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 958 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 959 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 960 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 961 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 962 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 963 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 964 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 965
 966 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 967
 968 #endif  /* CONFIG_IVMS8, CONFIG_IVML24 */
 969
 970 /***  KUP4K  *********************************************************/
 971 /* The KUP4K uses the FEC on a MPC855T for Ethernet */
 972
 973 #if defined(CONFIG_KUP4K)
 974
 975 #define FEC_ENET        /* use FEC for EThernet */
 976 #undef  SCC_ENET
 977
 978 #define PB_ENET_POWER   ((uint)0x00010000)      /* PB 15 */
 979
 980 #define PC_ENET_RESET   ((ushort)0x0010)        /* PC 11 */
 981
 982 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 983 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 984 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 985 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 986 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 987 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 988 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 989 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 990 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 991 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 992 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 993 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 994 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 995
 996 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 997
 998 #endif  /* CONFIG_KUP4K */
 999
1000
1001 /***  LANTEC  *********************************************************/
1002
1003 #if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
1004 /* Bits in parallel I/O port registers that have to be set/cleared
1005  * to configure the pins for SCC2 use.
1006  */
1007 #define PROFF_ENET      PROFF_SCC2
1008 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1009 #define SCC_ENET        1
1010 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1011 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1012 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
1013 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1014
1015 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1016
1017 #define PC_ENET_LBK     ((ushort)0x0010)        /* PC 11 */
1018 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1019 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1020
1021 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1022  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1023  */
1024 #define SICR_ENET_MASK  ((uint)0x0000FF00)
1025 #define SICR_ENET_CLKRT ((uint)0x00002E00)
1026 #endif  /* CONFIG_LANTEC v2 */
1027
1028 /***  LWMON  **********************************************************/
1029
1030 #if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
1031 /* Bits in parallel I/O port registers that have to be set/cleared
1032  * to configure the pins for SCC2 use.
1033  */
1034 #define PROFF_ENET      PROFF_SCC2
1035 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1036 #define SCC_ENET        1
1037 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1038 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1039 #define PA_ENET_RCLK    ((ushort)0x0800)        /* PA  4 */
1040 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1041
1042 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1043
1044 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1045 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1046
1047 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
1048  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1049  */
1050 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1051 #define SICR_ENET_CLKRT ((uint)0x00003E00)
1052 #endif  /* CONFIG_LWMON */
1053
1054 /***  NX823  ***********************************************/
1055
1056 #if defined(CONFIG_NX823)
1057 /* Bits in parallel I/O port registers that have to be set/cleared
1058  * to configure the pins for SCC1 use.
1059  */
1060 #define PROFF_ENET      PROFF_SCC2
1061 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1062 #define SCC_ENET        1
1063 #define PA_ENET_RXD     ((ushort)0x0004)  /* PA 13 */
1064 #define PA_ENET_TXD     ((ushort)0x0008)  /* PA 12 */
1065 #define PA_ENET_RCLK    ((ushort)0x0200)  /* PA  6 */
1066 #define PA_ENET_TCLK    ((ushort)0x0800)  /* PA  4 */
1067
1068 #define PB_ENET_TENA    ((uint)0x00002000)   /* PB 18 */
1069
1070 #define PC_ENET_CLSN    ((ushort)0x0040)  /* PC  9 */
1071 #define PC_ENET_RENA    ((ushort)0x0080)  /* PC  8 */
1072
1073 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1074  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1075  */
1076 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1077 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1078
1079 #endif   /* CONFIG_NX823 */
1080
1081 /***  MBX  ************************************************************/
1082
1083 #ifdef CONFIG_MBX
1084 /* Bits in parallel I/O port registers that have to be set/cleared
1085  * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
1086  * to the MBX860 board.  Any two of the four available clocks could be
1087  * used, and the MPC860 cookbook manual has an example using different
1088  * clock pins.
1089  */
1090 #define PROFF_ENET      PROFF_SCC1
1091 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1092 #define SCC_ENET        0
1093 #define PA_ENET_RXD     ((ushort)0x0001)
1094 #define PA_ENET_TXD     ((ushort)0x0002)
1095 #define PA_ENET_TCLK    ((ushort)0x0200)
1096 #define PA_ENET_RCLK    ((ushort)0x0800)
1097 #define PC_ENET_TENA    ((ushort)0x0001)
1098 #define PC_ENET_CLSN    ((ushort)0x0010)
1099 #define PC_ENET_RENA    ((ushort)0x0020)
1100
1101 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1102  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1103  */
1104 #define SICR_ENET_MASK  ((uint)0x000000ff)
1105 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1106 #endif  /* CONFIG_MBX */
1107
1108 /***  MHPC  ********************************************************/
1109
1110 #if defined(CONFIG_MHPC)
1111 /* This ENET stuff is for the MHPC with ethernet on SCC2.
1112  * Note TENA is on Port B.
1113  */
1114 #define PROFF_ENET      PROFF_SCC2
1115 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1116 #define SCC_ENET        1
1117 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1118 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1119 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA 6 */
1120 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA 5 */
1121 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1122 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC 9 */
1123 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC 8 */
1124
1125 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1126 #define SICR_ENET_CLKRT ((uint)0x00002e00)      /* RCLK-CLK2, TCLK-CLK3 */
1127 #endif  /* CONFIG_MHPC */
1128
1129 /***  NETVIA  *******************************************************/
1130
1131 #if defined(CONFIG_NETVIA)
1132 /* Bits in parallel I/O port registers that have to be set/cleared
1133  * to configure the pins for SCC2 use.
1134  */
1135 #define PROFF_ENET      PROFF_SCC2
1136 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1137 #define SCC_ENET        1
1138 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1139 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1140 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
1141 #define PA_ENET_TCLK    ((ushort)0x0800)        /* PA  4 */
1142
1143 #define PB_ENET_PDN     ((ushort)0x4000)        /* PB 17 */
1144 #define PB_ENET_TENA    ((ushort)0x2000)        /* PB 18 */
1145
1146 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1147 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1148
1149 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1150  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1151  */
1152 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1153 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1154
1155 #endif  /* CONFIG_NETVIA */
1156
1157 /***  RPXCLASSIC  *****************************************************/
1158
1159 #ifdef CONFIG_RPXCLASSIC
1160
1161 #ifdef CONFIG_FEC_ENET
1162
1163 # define FEC_ENET                               /* use FEC for EThernet */
1164 # undef SCC_ENET
1165
1166 #else   /* ! CONFIG_FEC_ENET */
1167
1168 /* Bits in parallel I/O port registers that have to be set/cleared
1169  * to configure the pins for SCC1 use.
1170  */
1171 #define PROFF_ENET      PROFF_SCC1
1172 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1173 #define SCC_ENET        0
1174 #define PA_ENET_RXD     ((ushort)0x0001)
1175 #define PA_ENET_TXD     ((ushort)0x0002)
1176 #define PA_ENET_TCLK    ((ushort)0x0200)
1177 #define PA_ENET_RCLK    ((ushort)0x0800)
1178 #define PB_ENET_TENA    ((uint)0x00001000)
1179 #define PC_ENET_CLSN    ((ushort)0x0010)
1180 #define PC_ENET_RENA    ((ushort)0x0020)
1181
1182 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1183  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1184  */
1185 #define SICR_ENET_MASK  ((uint)0x000000ff)
1186 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1187
1188 #endif  /* CONFIG_FEC_ENET */
1189
1190 #endif  /* CONFIG_RPXCLASSIC */
1191
1192 /***  RPXLITE  ********************************************************/
1193
1194 #ifdef CONFIG_RPXLITE
1195 /* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
1196  * this may be unique to the RPX-Lite configuration.
1197  * Note TENA is on Port B.
1198  */
1199 #define PROFF_ENET      PROFF_SCC2
1200 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1201 #define SCC_ENET        1
1202 #define PA_ENET_RXD     ((ushort)0x0004)
1203 #define PA_ENET_TXD     ((ushort)0x0008)
1204 #define PA_ENET_TCLK    ((ushort)0x0200)
1205 #define PA_ENET_RCLK    ((ushort)0x0800)
1206 #define PB_ENET_TENA    ((uint)0x00002000)
1207 #define PC_ENET_CLSN    ((ushort)0x0040)
1208 #define PC_ENET_RENA    ((ushort)0x0080)
1209
1210 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1211 #define SICR_ENET_CLKRT ((uint)0x00003d00)
1212 #endif  /* CONFIG_RPXLITE */
1213
1214 /***  SM850  *********************************************************/
1215
1216 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
1217
1218 #ifdef CONFIG_SM850
1219 #define PROFF_ENET      PROFF_SCC3              /* Ethernet on SCC3 */
1220 #define CPM_CR_ENET     CPM_CR_CH_SCC3
1221 #define SCC_ENET        2
1222 #define PB_ENET_RXD     ((uint)0x00000004)      /* PB 29 */
1223 #define PB_ENET_TXD     ((uint)0x00000002)      /* PB 30 */
1224 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1225 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1226
1227 #define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
1228 #define PC_ENET_TENA    ((ushort)0x0004)        /* PC 13 */
1229
1230 #define PC_ENET_RENA    ((ushort)0x0800)        /* PC  4 */
1231 #define PC_ENET_CLSN    ((ushort)0x0400)        /* PC  5 */
1232
1233 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1234  * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1235  */
1236 #define SICR_ENET_MASK  ((uint)0x00FF0000)
1237 #define SICR_ENET_CLKRT ((uint)0x00260000)
1238 #endif  /* CONFIG_SM850 */
1239
1240 /***  SPD823TS  ******************************************************/
1241
1242 #ifdef CONFIG_SPD823TS
1243 /* Bits in parallel I/O port registers that have to be set/cleared
1244  * to configure the pins for SCC2 use.
1245  */
1246 #define PROFF_ENET      PROFF_SCC2              /* Ethernet on SCC2 */
1247 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1248 #define SCC_ENET        1
1249 #define PA_ENET_MDC     ((ushort)0x0001)        /* PA 15 !!! */
1250 #define PA_ENET_MDIO    ((ushort)0x0002)        /* PA 14 !!! */
1251 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1252 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1253 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
1254 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1255
1256 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1257
1258 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1259 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1260 #define PC_ENET_RESET   ((ushort)0x0100)        /* PC  7 !!! */
1261
1262 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1263  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1264  */
1265 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1266 #define SICR_ENET_CLKRT ((uint)0x00002E00)
1267 #endif  /* CONFIG_SPD823TS */
1268
1269 /***  SXNI855T  ******************************************************/
1270
1271 #if defined(CONFIG_SXNI855T)
1272
1273 #ifdef CONFIG_FEC_ENET
1274 #define FEC_ENET        /* use FEC for Ethernet */
1275 #endif  /* CONFIG_FEC_ETHERNET */
1276
1277 #endif  /* CONFIG_SXNI855T */
1278
1279 /***  MVS1, TQM823L, TQM850L, ETX094, R360MPI  ***********************/
1280
1281 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
1282     defined(CONFIG_R360MPI) || \
1283     defined(CONFIG_TQM823L) || \
1284     defined(CONFIG_TQM850L) || \
1285     defined(CONFIG_ETX094)  || \
1286     defined(CONFIG_RRVISION)|| \
1287    (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
1288 /* Bits in parallel I/O port registers that have to be set/cleared
1289  * to configure the pins for SCC2 use.
1290  */
1291 #define PROFF_ENET      PROFF_SCC2
1292 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1293 #define SCC_ENET        1
1294 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1295 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1296 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1297 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1298
1299 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1300
1301 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1302 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1303 #if defined(CONFIG_R360MPI)
1304 #define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
1305 #endif   /* CONFIG_R360MPI */
1306
1307 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1308  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1309  */
1310 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1311 #define SICR_ENET_CLKRT ((uint)0x00002600)
1312 #endif  /* CONFIG_MVS v1, CONFIG_TQM823L, CONFIG_TQM850L, etc. */
1313
1314 /***  TQM860L, TQM855L ************************************************/
1315
1316 #if (defined(CONFIG_TQM860L) || defined(CONFIG_TQM855L))
1317
1318 # ifdef CONFIG_SCC1_ENET        /* use SCC for 10Mbps Ethernet  */
1319
1320 /* Bits in parallel I/O port registers that have to be set/cleared
1321  * to configure the pins for SCC1 use.
1322  */
1323 #define PROFF_ENET      PROFF_SCC1
1324 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1325 #define SCC_ENET        0
1326 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
1327 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
1328 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1329 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1330
1331 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
1332 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
1333 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
1334
1335 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1336  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1337  */
1338 #define SICR_ENET_MASK  ((uint)0x000000ff)
1339 #define SICR_ENET_CLKRT ((uint)0x00000026)
1340
1341 # endif /* CONFIG_SCC1_ENET */
1342
1343 # ifdef CONFIG_FEC_ENET         /* Use FEC for Fast Ethernet */
1344
1345 #define FEC_ENET
1346
1347 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
1348 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
1349 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
1350 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
1351 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
1352 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
1353 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
1354 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
1355 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
1356 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
1357 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
1358 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
1359 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
1360
1361 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
1362
1363 # endif /* CONFIG_FEC_ENET */
1364 #endif  /* CONFIG_TQM860L, CONFIG_TQM855L */
1365
1366 /***  V37  **********************************************************/
1367
1368 #ifdef CONFIG_V37
1369 /* This ENET stuff is for the MPC823 with ethernet on SCC2.  Some of
1370  * this may be unique to the Marel V37 configuration.
1371  * Note TENA is on Port B.
1372  */
1373 #define PROFF_ENET      PROFF_SCC2
1374 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1375 #define SCC_ENET        1
1376 #define PA_ENET_RXD     ((ushort)0x0004)
1377 #define PA_ENET_TXD     ((ushort)0x0008)
1378 #define PA_ENET_TCLK    ((ushort)0x0400)
1379 #define PA_ENET_RCLK    ((ushort)0x0200)
1380 #define PB_ENET_TENA    ((uint)0x00002000)
1381 #define PC_ENET_CLSN    ((ushort)0x0040)
1382 #define PC_ENET_RENA    ((ushort)0x0080)
1383
1384 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1385 #define SICR_ENET_CLKRT ((uint)0x00002e00)
1386 #endif  /* CONFIG_V37 */
1387
1388 /*********************************************************************/
1389
1390 /* SCC Event register as used by Ethernet.
1391 */
1392 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
1393 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
1394 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
1395 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
1396 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
1397 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
1398
1399 /* SCC Mode Register (PSMR) as used by Ethernet.
1400 */
1401 #define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
1402 #define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
1403 #define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
1404 #define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
1405 #define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
1406 #define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
1407 #define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
1408 #define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
1409 #define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
1410 #define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
1411 #define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
1412 #define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
1413 #define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
1414
1415 /* Buffer descriptor control/status used by Ethernet receive.
1416 */
1417 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
1418 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
1419 #define BD_ENET_RX_INTR         ((ushort)0x1000)
1420 #define BD_ENET_RX_LAST         ((ushort)0x0800)
1421 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
1422 #define BD_ENET_RX_MISS         ((ushort)0x0100)
1423 #define BD_ENET_RX_LG           ((ushort)0x0020)
1424 #define BD_ENET_RX_NO           ((ushort)0x0010)
1425 #define BD_ENET_RX_SH           ((ushort)0x0008)
1426 #define BD_ENET_RX_CR           ((ushort)0x0004)
1427 #define BD_ENET_RX_OV           ((ushort)0x0002)
1428 #define BD_ENET_RX_CL           ((ushort)0x0001)
1429 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
1430
1431 /* Buffer descriptor control/status used by Ethernet transmit.
1432 */
1433 #define BD_ENET_TX_READY        ((ushort)0x8000)
1434 #define BD_ENET_TX_PAD          ((ushort)0x4000)
1435 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
1436 #define BD_ENET_TX_INTR         ((ushort)0x1000)
1437 #define BD_ENET_TX_LAST         ((ushort)0x0800)
1438 #define BD_ENET_TX_TC           ((ushort)0x0400)
1439 #define BD_ENET_TX_DEF          ((ushort)0x0200)
1440 #define BD_ENET_TX_HB           ((ushort)0x0100)
1441 #define BD_ENET_TX_LC           ((ushort)0x0080)
1442 #define BD_ENET_TX_RL           ((ushort)0x0040)
1443 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
1444 #define BD_ENET_TX_UN           ((ushort)0x0002)
1445 #define BD_ENET_TX_CSL          ((ushort)0x0001)
1446 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
1447
1448 /* SCC as UART
1449 */
1450 typedef struct scc_uart {
1451         sccp_t  scc_genscc;
1452         uint    scc_res1;       /* Reserved */
1453         uint    scc_res2;       /* Reserved */
1454         ushort  scc_maxidl;     /* Maximum idle chars */
1455         ushort  scc_idlc;       /* temp idle counter */
1456         ushort  scc_brkcr;      /* Break count register */
1457         ushort  scc_parec;      /* receive parity error counter */
1458         ushort  scc_frmec;      /* receive framing error counter */
1459         ushort  scc_nosec;      /* receive noise counter */
1460         ushort  scc_brkec;      /* receive break condition counter */
1461         ushort  scc_brkln;      /* last received break length */
1462         ushort  scc_uaddr1;     /* UART address character 1 */
1463         ushort  scc_uaddr2;     /* UART address character 2 */
1464         ushort  scc_rtemp;      /* Temp storage */
1465         ushort  scc_toseq;      /* Transmit out of sequence char */
1466         ushort  scc_char1;      /* control character 1 */
1467         ushort  scc_char2;      /* control character 2 */
1468         ushort  scc_char3;      /* control character 3 */
1469         ushort  scc_char4;      /* control character 4 */
1470         ushort  scc_char5;      /* control character 5 */
1471         ushort  scc_char6;      /* control character 6 */
1472         ushort  scc_char7;      /* control character 7 */
1473         ushort  scc_char8;      /* control character 8 */
1474         ushort  scc_rccm;       /* receive control character mask */
1475         ushort  scc_rccr;       /* receive control character register */
1476         ushort  scc_rlbc;       /* receive last break character */
1477 } scc_uart_t;
1478
1479 /* SCC Event and Mask registers when it is used as a UART.
1480 */
1481 #define UART_SCCM_GLR           ((ushort)0x1000)
1482 #define UART_SCCM_GLT           ((ushort)0x0800)
1483 #define UART_SCCM_AB            ((ushort)0x0200)
1484 #define UART_SCCM_IDL           ((ushort)0x0100)
1485 #define UART_SCCM_GRA           ((ushort)0x0080)
1486 #define UART_SCCM_BRKE          ((ushort)0x0040)
1487 #define UART_SCCM_BRKS          ((ushort)0x0020)
1488 #define UART_SCCM_CCR           ((ushort)0x0008)
1489 #define UART_SCCM_BSY           ((ushort)0x0004)
1490 #define UART_SCCM_TX            ((ushort)0x0002)
1491 #define UART_SCCM_RX            ((ushort)0x0001)
1492
1493 /* The SCC PSMR when used as a UART.
1494 */
1495 #define SCU_PSMR_FLC            ((ushort)0x8000)
1496 #define SCU_PSMR_SL             ((ushort)0x4000)
1497 #define SCU_PSMR_CL             ((ushort)0x3000)
1498 #define SCU_PSMR_UM             ((ushort)0x0c00)
1499 #define SCU_PSMR_FRZ            ((ushort)0x0200)
1500 #define SCU_PSMR_RZS            ((ushort)0x0100)
1501 #define SCU_PSMR_SYN            ((ushort)0x0080)
1502 #define SCU_PSMR_DRT            ((ushort)0x0040)
1503 #define SCU_PSMR_PEN            ((ushort)0x0010)
1504 #define SCU_PSMR_RPM            ((ushort)0x000c)
1505 #define SCU_PSMR_REVP           ((ushort)0x0008)
1506 #define SCU_PSMR_TPM            ((ushort)0x0003)
1507 #define SCU_PSMR_TEVP           ((ushort)0x0003)
1508
1509 /* CPM Transparent mode SCC.
1510  */
1511 typedef struct scc_trans {
1512         sccp_t  st_genscc;
1513         uint    st_cpres;       /* Preset CRC */
1514         uint    st_cmask;       /* Constant mask for CRC */
1515 } scc_trans_t;
1516
1517 #define BD_SCC_TX_LAST          ((ushort)0x0800)
1518
1519 /* IIC parameter RAM.
1520 */
1521 typedef struct iic {
1522         ushort  iic_rbase;      /* Rx Buffer descriptor base address */
1523         ushort  iic_tbase;      /* Tx Buffer descriptor base address */
1524         u_char  iic_rfcr;       /* Rx function code */
1525         u_char  iic_tfcr;       /* Tx function code */
1526         ushort  iic_mrblr;      /* Max receive buffer length */
1527         uint    iic_rstate;     /* Internal */
1528         uint    iic_rdp;        /* Internal */
1529         ushort  iic_rbptr;      /* Internal */
1530         ushort  iic_rbc;        /* Internal */
1531         uint    iic_rxtmp;      /* Internal */
1532         uint    iic_tstate;     /* Internal */
1533         uint    iic_tdp;        /* Internal */
1534         ushort  iic_tbptr;      /* Internal */
1535         ushort  iic_tbc;        /* Internal */
1536         uint    iic_txtmp;      /* Internal */
1537         uint    iic_res;        /* reserved */
1538         ushort  iic_rpbase;     /* Relocation pointer */
1539         ushort  iic_res2;       /* reserved */
1540 } iic_t;
1541
1542 /* SPI parameter RAM.
1543 */
1544 typedef struct spi {
1545         ushort  spi_rbase;      /* Rx Buffer descriptor base address */
1546         ushort  spi_tbase;      /* Tx Buffer descriptor base address */
1547         u_char  spi_rfcr;       /* Rx function code */
1548         u_char  spi_tfcr;       /* Tx function code */
1549         ushort  spi_mrblr;      /* Max receive buffer length */
1550         uint    spi_rstate;     /* Internal */
1551         uint    spi_rdp;        /* Internal */
1552         ushort  spi_rbptr;      /* Internal */
1553         ushort  spi_rbc;        /* Internal */
1554         uint    spi_rxtmp;      /* Internal */
1555         uint    spi_tstate;     /* Internal */
1556         uint    spi_tdp;        /* Internal */
1557         ushort  spi_tbptr;      /* Internal */
1558         ushort  spi_tbc;        /* Internal */
1559         uint    spi_txtmp;      /* Internal */
1560         uint    spi_res;
1561         ushort  spi_rpbase;     /* Relocation pointer */
1562         ushort  spi_res2;
1563 } spi_t;
1564
1565 /* SPI Mode register.
1566 */
1567 #define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
1568 #define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
1569 #define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
1570 #define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
1571 #define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
1572 #define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
1573 #define SPMODE_EN       ((ushort)0x0100)        /* Enable */
1574 #define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
1575 #define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
1576
1577 #define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
1578 #define SPMODE_PM(x)    ((x) &0xF)
1579
1580 /* HDLC parameter RAM.
1581 */
1582
1583 typedef struct hdlc_pram_s {
1584         /*
1585          * SCC parameter RAM
1586          */
1587         ushort  rbase;          /* Rx Buffer descriptor base address */
1588         ushort  tbase;          /* Tx Buffer descriptor base address */
1589         uchar   rfcr;           /* Rx function code */
1590         uchar   tfcr;           /* Tx function code */
1591         ushort  mrblr;          /* Rx buffer length */
1592         ulong   rstate;         /* Rx internal state */
1593         ulong   rptr;           /* Rx internal data pointer */
1594         ushort  rbptr;          /* rb BD Pointer */
1595         ushort  rcount;         /* Rx internal byte count */
1596         ulong   rtemp;          /* Rx temp */
1597         ulong   tstate;         /* Tx internal state */
1598         ulong   tptr;           /* Tx internal data pointer */
1599         ushort  tbptr;          /* Tx BD pointer */
1600         ushort  tcount;         /* Tx byte count */
1601         ulong   ttemp;          /* Tx temp */
1602         ulong   rcrc;           /* temp receive CRC */
1603         ulong   tcrc;           /* temp transmit CRC */
1604         /*
1605          * HDLC specific parameter RAM
1606          */
1607         uchar   res[4];         /* reserved */
1608         ulong   c_mask;         /* CRC constant */
1609         ulong   c_pres;         /* CRC preset */
1610         ushort  disfc;          /* discarded frame counter */
1611         ushort  crcec;          /* CRC error counter */
1612         ushort  abtsc;          /* abort sequence counter */
1613         ushort  nmarc;          /* nonmatching address rx cnt */
1614         ushort  retrc;          /* frame retransmission cnt */
1615         ushort  mflr;           /* maximum frame length reg */
1616         ushort  max_cnt;        /* maximum length counter */
1617         ushort  rfthr;          /* received frames threshold */
1618         ushort  rfcnt;          /* received frames count */
1619         ushort  hmask;          /* user defined frm addr mask */
1620         ushort  haddr1;         /* user defined frm address 1 */
1621         ushort  haddr2;         /* user defined frm address 2 */
1622         ushort  haddr3;         /* user defined frm address 3 */
1623         ushort  haddr4;         /* user defined frm address 4 */
1624         ushort  tmp;            /* temp */
1625         ushort  tmp_mb;         /* temp */
1626 } hdlc_pram_t;
1627
1628 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
1629  * channels or devices.  All of these are presented to the PPC core
1630  * as a single interrupt.  The CPM interrupt handler dispatches its
1631  * own handlers, in a similar fashion to the PPC core handler.  We
1632  * use the table as defined in the manuals (i.e. no special high
1633  * priority and SCC1 == SCCa, etc...).
1634  */
1635 #define CPMVEC_NR               32
1636 #define CPMVEC_OFFSET           0x00010000
1637 #define CPMVEC_PIO_PC15         ((ushort)0x1f | CPMVEC_OFFSET)
1638 #define CPMVEC_SCC1             ((ushort)0x1e | CPMVEC_OFFSET)
1639 #define CPMVEC_SCC2             ((ushort)0x1d | CPMVEC_OFFSET)
1640 #define CPMVEC_SCC3             ((ushort)0x1c | CPMVEC_OFFSET)
1641 #define CPMVEC_SCC4             ((ushort)0x1b | CPMVEC_OFFSET)
1642 #define CPMVEC_PIO_PC14         ((ushort)0x1a | CPMVEC_OFFSET)
1643 #define CPMVEC_TIMER1           ((ushort)0x19 | CPMVEC_OFFSET)
1644 #define CPMVEC_PIO_PC13         ((ushort)0x18 | CPMVEC_OFFSET)
1645 #define CPMVEC_PIO_PC12         ((ushort)0x17 | CPMVEC_OFFSET)
1646 #define CPMVEC_SDMA_CB_ERR      ((ushort)0x16 | CPMVEC_OFFSET)
1647 #define CPMVEC_IDMA1            ((ushort)0x15 | CPMVEC_OFFSET)
1648 #define CPMVEC_IDMA2            ((ushort)0x14 | CPMVEC_OFFSET)
1649 #define CPMVEC_TIMER2           ((ushort)0x12 | CPMVEC_OFFSET)
1650 #define CPMVEC_RISCTIMER        ((ushort)0x11 | CPMVEC_OFFSET)
1651 #define CPMVEC_I2C              ((ushort)0x10 | CPMVEC_OFFSET)
1652 #define CPMVEC_PIO_PC11         ((ushort)0x0f | CPMVEC_OFFSET)
1653 #define CPMVEC_PIO_PC10         ((ushort)0x0e | CPMVEC_OFFSET)
1654 #define CPMVEC_TIMER3           ((ushort)0x0c | CPMVEC_OFFSET)
1655 #define CPMVEC_PIO_PC9          ((ushort)0x0b | CPMVEC_OFFSET)
1656 #define CPMVEC_PIO_PC8          ((ushort)0x0a | CPMVEC_OFFSET)
1657 #define CPMVEC_PIO_PC7          ((ushort)0x09 | CPMVEC_OFFSET)
1658 #define CPMVEC_TIMER4           ((ushort)0x07 | CPMVEC_OFFSET)
1659 #define CPMVEC_PIO_PC6          ((ushort)0x06 | CPMVEC_OFFSET)
1660 #define CPMVEC_SPI              ((ushort)0x05 | CPMVEC_OFFSET)
1661 #define CPMVEC_SMC1             ((ushort)0x04 | CPMVEC_OFFSET)
1662 #define CPMVEC_SMC2             ((ushort)0x03 | CPMVEC_OFFSET)
1663 #define CPMVEC_PIO_PC5          ((ushort)0x02 | CPMVEC_OFFSET)
1664 #define CPMVEC_PIO_PC4          ((ushort)0x01 | CPMVEC_OFFSET)
1665 #define CPMVEC_ERROR            ((ushort)0x00 | CPMVEC_OFFSET)
1666
1667 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1668
1669 /* CPM interrupt configuration vector.
1670 */
1671 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
1672 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
1673 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
1674 #define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
1675 #define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrrupt */
1676 #define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
1677 #define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
1678 #define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
1679 #endif /* __CPM_8XX__ */