include/commproc.h

   1 /*
   2  * MPC8xx Communication Processor Module.
   3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   4  *
   5  * (C) Copyright 2000-2006
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * This file contains structures and information for the communication
   9  * processor channels.  Some CPM control and status is available
  10  * throught the MPC8xx internal memory map.  See immap.h for details.
  11  * This file only contains what I need for the moment, not the total
  12  * CPM capabilities.  I (or someone else) will add definitions as they
  13  * are needed.  -- Dan
  14  *
  15  */
  16 #ifndef __CPM_8XX__
  17 #define __CPM_8XX__
  18
  19 #include <asm/8xx_immap.h>
  20
  21 /* CPM Command register.
  22 */
  23 #define CPM_CR_RST              ((ushort)0x8000)
  24 #define CPM_CR_OPCODE           ((ushort)0x0f00)
  25 #define CPM_CR_CHAN             ((ushort)0x00f0)
  26 #define CPM_CR_FLG              ((ushort)0x0001)
  27
  28 /* Some commands (there are more...later)
  29 */
  30 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
  31 #define CPM_CR_INIT_RX          ((ushort)0x0001)
  32 #define CPM_CR_INIT_TX          ((ushort)0x0002)
  33 #define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  34 #define CPM_CR_STOP_TX          ((ushort)0x0004)
  35 #define CPM_CR_RESTART_TX       ((ushort)0x0006)
  36 #define CPM_CR_SET_GADDR        ((ushort)0x0008)
  37
  38 /* Channel numbers.
  39 */
  40 #define CPM_CR_CH_SCC1          ((ushort)0x0000)
  41 #define CPM_CR_CH_I2C           ((ushort)0x0001)    /* I2C and IDMA1 */
  42 #define CPM_CR_CH_SCC2          ((ushort)0x0004)
  43 #define CPM_CR_CH_SPI           ((ushort)0x0005)    /* SPI/IDMA2/Timers */
  44 #define CPM_CR_CH_SCC3          ((ushort)0x0008)
  45 #define CPM_CR_CH_SMC1          ((ushort)0x0009)    /* SMC1 / DSP1 */
  46 #define CPM_CR_CH_SCC4          ((ushort)0x000c)
  47 #define CPM_CR_CH_SMC2          ((ushort)0x000d)    /* SMC2 / DSP2 */
  48
  49 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  50
  51 /*
  52  * DPRAM defines and allocation functions
  53  */
  54
  55 /* The dual ported RAM is multi-functional.  Some areas can be (and are
  56  * being) used for microcode.  There is an area that can only be used
  57  * as data ram for buffer descriptors, which is all we use right now.
  58  * Currently the first 512 and last 256 bytes are used for microcode.
  59  */
  60 #ifdef  CONFIG_SYS_ALLOC_DPRAM
  61
  62 #define CPM_DATAONLY_BASE       ((uint)0x0800)
  63 #define CPM_DATAONLY_SIZE       ((uint)0x0700)
  64 #define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  65
  66 #else
  67
  68 #define CPM_SERIAL_BASE         0x0800
  69 #define CPM_I2C_BASE            0x0820
  70 #define CPM_SPI_BASE            0x0840
  71 #define CPM_FEC_BASE            0x0860
  72 #define CPM_SERIAL2_BASE        0x08E0
  73 #define CPM_SCC_BASE            0x0900
  74 #define CPM_POST_BASE           0x0980
  75 #define CPM_WLKBD_BASE          0x0a00
  76
  77 #endif
  78
  79 #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
  80 #define CPM_POST_WORD_ADDR      0x07FC
  81 #else
  82 #define CPM_POST_WORD_ADDR      CONFIG_SYS_CPM_POST_WORD_ADDR
  83 #endif
  84
  85 #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
  86 #define CPM_BOOTCOUNT_ADDR      (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
  87 #else
  88 #define CPM_BOOTCOUNT_ADDR      CONFIG_SYS_CPM_BOOTCOUNT_ADDR
  89 #endif
  90
  91 #define BD_IIC_START    ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
  92
  93 /* Export the base address of the communication processor registers
  94  * and dual port ram.
  95  */
  96 extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
  97
  98 /* Buffer descriptors used by many of the CPM protocols.
  99 */
 100 typedef struct cpm_buf_desc {
 101         ushort  cbd_sc;         /* Status and Control */
 102         ushort  cbd_datlen;     /* Data length in buffer */
 103         uint    cbd_bufaddr;    /* Buffer address in host memory */
 104 } cbd_t;
 105
 106 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
 107 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
 108 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
 109 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
 110 #define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
 111 #define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
 112 #define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
 113 #define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
 114 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
 115 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
 116 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
 117 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
 118 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
 119 #define BD_SC_CD        ((ushort)0x0001)        /* Carrier Detect lost */
 120
 121 /* Parameter RAM offsets.
 122 */
 123 #define PROFF_SCC1      ((uint)0x0000)
 124 #define PROFF_IIC       ((uint)0x0080)
 125 #define PROFF_REVNUM    ((uint)0x00b0)
 126 #define PROFF_SCC2      ((uint)0x0100)
 127 #define PROFF_SPI       ((uint)0x0180)
 128 #define PROFF_SCC3      ((uint)0x0200)
 129 #define PROFF_SMC1      ((uint)0x0280)
 130 #define PROFF_SCC4      ((uint)0x0300)
 131 #define PROFF_SMC2      ((uint)0x0380)
 132
 133 /* Define enough so I can at least use the serial port as a UART.
 134  */
 135 typedef struct smc_uart {
 136         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 137         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 138         u_char  smc_rfcr;       /* Rx function code */
 139         u_char  smc_tfcr;       /* Tx function code */
 140         ushort  smc_mrblr;      /* Max receive buffer length */
 141         uint    smc_rstate;     /* Internal */
 142         uint    smc_idp;        /* Internal */
 143         ushort  smc_rbptr;      /* Internal */
 144         ushort  smc_ibc;        /* Internal */
 145         uint    smc_rxtmp;      /* Internal */
 146         uint    smc_tstate;     /* Internal */
 147         uint    smc_tdp;        /* Internal */
 148         ushort  smc_tbptr;      /* Internal */
 149         ushort  smc_tbc;        /* Internal */
 150         uint    smc_txtmp;      /* Internal */
 151         ushort  smc_maxidl;     /* Maximum idle characters */
 152         ushort  smc_tmpidl;     /* Temporary idle counter */
 153         ushort  smc_brklen;     /* Last received break length */
 154         ushort  smc_brkec;      /* rcv'd break condition counter */
 155         ushort  smc_brkcr;      /* xmt break count register */
 156         ushort  smc_rmask;      /* Temporary bit mask */
 157         u_char  res1[8];
 158         ushort  smc_rpbase;     /* Relocation pointer */
 159 } smc_uart_t;
 160
 161 /* Function code bits.
 162 */
 163 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 164
 165 /* SMC uart mode register.
 166 */
 167 #define SMCMR_REN       ((ushort)0x0001)
 168 #define SMCMR_TEN       ((ushort)0x0002)
 169 #define SMCMR_DM        ((ushort)0x000c)
 170 #define SMCMR_SM_GCI    ((ushort)0x0000)
 171 #define SMCMR_SM_UART   ((ushort)0x0020)
 172 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 173 #define SMCMR_SM_MASK   ((ushort)0x0030)
 174 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 175 #define SMCMR_REVD      SMCMR_PM_EVEN
 176 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 177 #define SMCMR_BS        SMCMR_PEN
 178 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 179 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 180 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 181
 182 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
 183  * it can only receive or transmit.  The parameter ram values for
 184  * each direction are either unique or properly overlap, so we can
 185  * include them in one structure.
 186  */
 187 typedef struct smc_centronics {
 188         ushort  scent_rbase;
 189         ushort  scent_tbase;
 190         u_char  scent_cfcr;
 191         u_char  scent_smask;
 192         ushort  scent_mrblr;
 193         uint    scent_rstate;
 194         uint    scent_r_ptr;
 195         ushort  scent_rbptr;
 196         ushort  scent_r_cnt;
 197         uint    scent_rtemp;
 198         uint    scent_tstate;
 199         uint    scent_t_ptr;
 200         ushort  scent_tbptr;
 201         ushort  scent_t_cnt;
 202         uint    scent_ttemp;
 203         ushort  scent_max_sl;
 204         ushort  scent_sl_cnt;
 205         ushort  scent_character1;
 206         ushort  scent_character2;
 207         ushort  scent_character3;
 208         ushort  scent_character4;
 209         ushort  scent_character5;
 210         ushort  scent_character6;
 211         ushort  scent_character7;
 212         ushort  scent_character8;
 213         ushort  scent_rccm;
 214         ushort  scent_rccr;
 215 } smc_cent_t;
 216
 217 /* Centronics Status Mask Register.
 218 */
 219 #define SMC_CENT_F      ((u_char)0x08)
 220 #define SMC_CENT_PE     ((u_char)0x04)
 221 #define SMC_CENT_S      ((u_char)0x02)
 222
 223 /* SMC Event and Mask register.
 224 */
 225 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 226 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 227 #define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 228 #define SMCM_BSY        ((unsigned char)0x04)
 229 #define SMCM_TX         ((unsigned char)0x02)
 230 #define SMCM_RX         ((unsigned char)0x01)
 231
 232 /* Baud rate generators.
 233 */
 234 #define CPM_BRG_RST             ((uint)0x00020000)
 235 #define CPM_BRG_EN              ((uint)0x00010000)
 236 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 237 #define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 238 #define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 239 #define CPM_BRG_ATB             ((uint)0x00002000)
 240 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 241 #define CPM_BRG_DIV16           ((uint)0x00000001)
 242
 243 /* SI Clock Route Register
 244 */
 245 #define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 246 #define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 247 #define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 248 #define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 249 #define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 250 #define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 251 #define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 252 #define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 253
 254 /* SCCs.
 255 */
 256 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 257 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 258 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 259 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 260 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 261 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 262 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 263 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 264 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 265 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 266 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 267 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 268 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 269 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 270 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 271 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 272 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 273 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 274 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 275 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 276
 277 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 278 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 279 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 280 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 281 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 282 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 283 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 284 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 285 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 286 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 287 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 288 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 289 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 290 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 291 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 292 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 293 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 294 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 295 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 296 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 297 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 298 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 299 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 300 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 301 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 302 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 303 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 304 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 305 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 306 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 307 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 308 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 309 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 310 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 311 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 312 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 313 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 314 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 315 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 316 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 317 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 318 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 319 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 320 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 321 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 322 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 323 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 324 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 325 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 326 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 327 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 328 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 329 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 330 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 331 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 332 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 333 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 334 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 335
 336 #define SCC_TODR_TOD            ((ushort)0x8000)
 337
 338 /* SCC Event and Mask register.
 339 */
 340 #define SCCM_TXE        ((unsigned char)0x10)
 341 #define SCCM_BSY        ((unsigned char)0x04)
 342 #define SCCM_TX         ((unsigned char)0x02)
 343 #define SCCM_RX         ((unsigned char)0x01)
 344
 345 typedef struct scc_param {
 346         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 347         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 348         u_char  scc_rfcr;       /* Rx function code */
 349         u_char  scc_tfcr;       /* Tx function code */
 350         ushort  scc_mrblr;      /* Max receive buffer length */
 351         uint    scc_rstate;     /* Internal */
 352         uint    scc_idp;        /* Internal */
 353         ushort  scc_rbptr;      /* Internal */
 354         ushort  scc_ibc;        /* Internal */
 355         uint    scc_rxtmp;      /* Internal */
 356         uint    scc_tstate;     /* Internal */
 357         uint    scc_tdp;        /* Internal */
 358         ushort  scc_tbptr;      /* Internal */
 359         ushort  scc_tbc;        /* Internal */
 360         uint    scc_txtmp;      /* Internal */
 361         uint    scc_rcrc;       /* Internal */
 362         uint    scc_tcrc;       /* Internal */
 363 } sccp_t;
 364
 365 /* Function code bits.
 366 */
 367 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 368
 369 /* CPM Ethernet through SCCx.
 370  */
 371 typedef struct scc_enet {
 372         sccp_t  sen_genscc;
 373         uint    sen_cpres;      /* Preset CRC */
 374         uint    sen_cmask;      /* Constant mask for CRC */
 375         uint    sen_crcec;      /* CRC Error counter */
 376         uint    sen_alec;       /* alignment error counter */
 377         uint    sen_disfc;      /* discard frame counter */
 378         ushort  sen_pads;       /* Tx short frame pad character */
 379         ushort  sen_retlim;     /* Retry limit threshold */
 380         ushort  sen_retcnt;     /* Retry limit counter */
 381         ushort  sen_maxflr;     /* maximum frame length register */
 382         ushort  sen_minflr;     /* minimum frame length register */
 383         ushort  sen_maxd1;      /* maximum DMA1 length */
 384         ushort  sen_maxd2;      /* maximum DMA2 length */
 385         ushort  sen_maxd;       /* Rx max DMA */
 386         ushort  sen_dmacnt;     /* Rx DMA counter */
 387         ushort  sen_maxb;       /* Max BD byte count */
 388         ushort  sen_gaddr1;     /* Group address filter */
 389         ushort  sen_gaddr2;
 390         ushort  sen_gaddr3;
 391         ushort  sen_gaddr4;
 392         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 393         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 394         uint    sen_tbuf0rba;   /* Internal */
 395         uint    sen_tbuf0crc;   /* Internal */
 396         ushort  sen_tbuf0bcnt;  /* Internal */
 397         ushort  sen_paddrh;     /* physical address (MSB) */
 398         ushort  sen_paddrm;
 399         ushort  sen_paddrl;     /* physical address (LSB) */
 400         ushort  sen_pper;       /* persistence */
 401         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 402         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 403         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 404         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 405         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 406         uint    sen_tbuf1rba;   /* Internal */
 407         uint    sen_tbuf1crc;   /* Internal */
 408         ushort  sen_tbuf1bcnt;  /* Internal */
 409         ushort  sen_txlen;      /* Tx Frame length counter */
 410         ushort  sen_iaddr1;     /* Individual address filter */
 411         ushort  sen_iaddr2;
 412         ushort  sen_iaddr3;
 413         ushort  sen_iaddr4;
 414         ushort  sen_boffcnt;    /* Backoff counter */
 415
 416         /* NOTE: Some versions of the manual have the following items
 417          * incorrectly documented.  Below is the proper order.
 418          */
 419         ushort  sen_taddrh;     /* temp address (MSB) */
 420         ushort  sen_taddrm;
 421         ushort  sen_taddrl;     /* temp address (LSB) */
 422 } scc_enet_t;
 423
 424 /**********************************************************************
 425  *
 426  * Board specific configuration settings.
 427  *
 428  * Please note that we use the presence of a #define SCC_ENET and/or
 429  * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
 430  **********************************************************************/
 431
 432 /***  BSEIP  **********************************************************/
 433
 434 #ifdef CONFIG_BSEIP
 435 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
 436  * This is unique to the BSE ip-Engine board.
 437  */
 438 #define PROFF_ENET      PROFF_SCC2
 439 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 440 #define SCC_ENET        1
 441 #define PA_ENET_RXD     ((ushort)0x0004)
 442 #define PA_ENET_TXD     ((ushort)0x0008)
 443 #define PA_ENET_TCLK    ((ushort)0x0100)
 444 #define PA_ENET_RCLK    ((ushort)0x0200)
 445 #define PB_ENET_TENA    ((uint)0x00002000)
 446 #define PC_ENET_CLSN    ((ushort)0x0040)
 447 #define PC_ENET_RENA    ((ushort)0x0080)
 448
 449 /* BSE uses port B and C bits for PHY control also.
 450 */
 451 #define PB_BSE_POWERUP  ((uint)0x00000004)
 452 #define PB_BSE_FDXDIS   ((uint)0x00008000)
 453 #define PC_BSE_LOOPBACK ((ushort)0x0800)
 454
 455 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 456 #define SICR_ENET_CLKRT ((uint)0x00002c00)
 457 #endif  /* CONFIG_BSEIP */
 458
 459 /***  BSEIP  **********************************************************/
 460
 461 #ifdef CONFIG_FLAGADM
 462 /* Enet configuration for the FLAGADM */
 463 /* Enet on SCC2 */
 464
 465 #define PROFF_ENET      PROFF_SCC2
 466 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 467 #define SCC_ENET        1
 468 #define PA_ENET_RXD     ((ushort)0x0004)
 469 #define PA_ENET_TXD     ((ushort)0x0008)
 470 #define PA_ENET_TCLK    ((ushort)0x0100)
 471 #define PA_ENET_RCLK    ((ushort)0x0400)
 472 #define PB_ENET_TENA    ((uint)0x00002000)
 473 #define PC_ENET_CLSN    ((ushort)0x0040)
 474 #define PC_ENET_RENA    ((ushort)0x0080)
 475
 476 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 477 #define SICR_ENET_CLKRT ((uint)0x00003400)
 478 #endif  /* CONFIG_FLAGADM */
 479
 480 /***  ELPT860 *********************************************************/
 481
 482 #ifdef CONFIG_ELPT860
 483 /* Bits in parallel I/O port registers that have to be set/cleared
 484  * to configure the pins for SCC1 use.
 485  */
 486 #  define PROFF_ENET        PROFF_SCC1
 487 #  define CPM_CR_ENET       CPM_CR_CH_SCC1
 488 #  define SCC_ENET          0
 489
 490 #  define PA_ENET_RXD       ((ushort)0x0001)    /* PA 15 */
 491 #  define PA_ENET_TXD       ((ushort)0x0002)    /* PA 14 */
 492 #  define PA_ENET_RCLK      ((ushort)0x0100)    /* PA  7 */
 493 #  define PA_ENET_TCLK      ((ushort)0x0200)    /* PA  6 */
 494
 495 #  define PC_ENET_TENA      ((ushort)0x0001)    /* PC 15 */
 496 #  define PC_ENET_CLSN      ((ushort)0x0010)    /* PC 11 */
 497 #  define PC_ENET_RENA      ((ushort)0x0020)    /* PC 10 */
 498
 499 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
 500  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 501  */
 502 #  define SICR_ENET_MASK    ((uint)0x000000FF)
 503 #  define SICR_ENET_CLKRT   ((uint)0x00000025)
 504 #endif  /* CONFIG_ELPT860 */
 505
 506 /***  ESTEEM 192E  **************************************************/
 507 #ifdef CONFIG_ESTEEM192E
 508 /* ESTEEM192E
 509  * This ENET stuff is for the MPC850 with ethernet on SCC2. This
 510  * is very similar to the RPX-Lite configuration.
 511  * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
 512  */
 513
 514 #define PROFF_ENET      PROFF_SCC2
 515 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 516 #define SCC_ENET        1
 517
 518 #define PA_ENET_RXD     ((ushort)0x0004)
 519 #define PA_ENET_TXD     ((ushort)0x0008)
 520 #define PA_ENET_TCLK    ((ushort)0x0200)
 521 #define PA_ENET_RCLK    ((ushort)0x0800)
 522 #define PB_ENET_TENA    ((uint)0x00002000)
 523 #define PC_ENET_CLSN    ((ushort)0x0040)
 524 #define PC_ENET_RENA    ((ushort)0x0080)
 525
 526 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 527 #define SICR_ENET_CLKRT ((uint)0x00003d00)
 528
 529 #define PB_ENET_LOOPBACK ((uint)0x00004000)
 530 #define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
 531
 532 #endif
 533
 534 /***  FPS850L, FPS860L  ************************************************/
 535
 536 #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
 537 /* Bits in parallel I/O port registers that have to be set/cleared
 538  * to configure the pins for SCC2 use.
 539  */
 540 #define PROFF_ENET      PROFF_SCC2
 541 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 542 #define SCC_ENET        1
 543 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 544 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 545 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 546 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 547
 548 #define PC_ENET_TENA    ((ushort)0x0002)        /* PC 14 */
 549 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 550 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 551
 552 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 553  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 554  */
 555 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 556 #define SICR_ENET_CLKRT ((uint)0x00002600)
 557 #endif  /* CONFIG_FPS850L, CONFIG_FPS860L */
 558
 559 /*** GEN860T **********************************************************/
 560 #if defined(CONFIG_GEN860T)
 561 #undef  SCC_ENET
 562 #define FEC_ENET
 563
 564 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3        */
 565 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4        */
 566 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5        */
 567 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6        */
 568 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7        */
 569 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8        */
 570 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9        */
 571 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10        */
 572 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11        */
 573 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12        */
 574 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13        */
 575 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14        */
 576 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15        */
 577 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3-15      */
 578 #endif  /* CONFIG_GEN860T */
 579
 580 /*** HERMES-PRO ******************************************************/
 581
 582 /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
 583
 584 #ifdef CONFIG_HERMES
 585
 586 #define FEC_ENET        /* use FEC for EThernet */
 587 #undef  SCC_ENET
 588
 589
 590 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 591 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 592 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 593 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 594 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 595 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 596 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 597 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 598 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 599 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 600 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 601 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 602 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 603
 604 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 605
 606 #endif  /* CONFIG_HERMES */
 607
 608 /*** ICU862  **********************************************************/
 609
 610 #if defined(CONFIG_ICU862)
 611
 612 #ifdef CONFIG_FEC_ENET
 613 #define FEC_ENET        /* use FEC for EThernet */
 614 #endif  /* CONFIG_FEC_ETHERNET */
 615
 616 #endif /* CONFIG_ICU862 */
 617
 618 /***  IP860  **********************************************************/
 619
 620 #if defined(CONFIG_IP860)
 621 /* Bits in parallel I/O port registers that have to be set/cleared
 622  * to configure the pins for SCC1 use.
 623  */
 624 #define PROFF_ENET      PROFF_SCC1
 625 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 626 #define SCC_ENET        0
 627 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
 628 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
 629 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 630 #define PA_ENET_TCLK    ((ushort)0x0100)        /* PA  7 */
 631
 632 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
 633 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
 634 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
 635
 636 #define PB_ENET_RESET   (uint)0x00000008        /* PB 28 */
 637 #define PB_ENET_JABD    (uint)0x00000004        /* PB 29 */
 638
 639 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 640  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 641  */
 642 #define SICR_ENET_MASK  ((uint)0x000000ff)
 643 #define SICR_ENET_CLKRT ((uint)0x0000002C)
 644 #endif  /* CONFIG_IP860 */
 645
 646 /*** IVMS8  **********************************************************/
 647
 648 /* The IVMS8 uses the FEC on a MPC860T for Ethernet */
 649
 650 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
 651
 652 #define FEC_ENET        /* use FEC for EThernet */
 653 #undef  SCC_ENET
 654
 655 #define PB_ENET_POWER   ((uint)0x00010000)      /* PB 15 */
 656
 657 #define PC_ENET_RESET   ((ushort)0x0010)        /* PC 11 */
 658
 659 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 660 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 661 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 662 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 663 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 664 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 665 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 666 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 667 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 668 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 669 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 670 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 671 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 672
 673 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 674
 675 #endif  /* CONFIG_IVMS8, CONFIG_IVML24 */
 676
 677 /***  KUP4K, KUP4X ****************************************************/
 678 /* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
 679
 680 #if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
 681
 682 #define FEC_ENET        /* use FEC for EThernet */
 683 #undef  SCC_ENET
 684
 685 #define PB_ENET_POWER   ((uint)0x00010000)      /* PB 15 */
 686
 687 #define PC_ENET_RESET   ((ushort)0x0010)        /* PC 11 */
 688
 689 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 690 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 691 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 692 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 693 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 694 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 695 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 696 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 697 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 698 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 699 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 700 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 701 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 702
 703 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 704
 705 #endif  /* CONFIG_KUP4K */
 706
 707 /***  LWMON  **********************************************************/
 708
 709 #if defined(CONFIG_LWMON)
 710 /* Bits in parallel I/O port registers that have to be set/cleared
 711  * to configure the pins for SCC2 use.
 712  */
 713 #define PROFF_ENET      PROFF_SCC2
 714 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 715 #define SCC_ENET        1
 716 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 717 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 718 #define PA_ENET_RCLK    ((ushort)0x0800)        /* PA  4 */
 719 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 720
 721 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 722
 723 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 724 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 725
 726 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
 727  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 728  */
 729 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 730 #define SICR_ENET_CLKRT ((uint)0x00003E00)
 731 #endif  /* CONFIG_LWMON */
 732
 733 /***  KM8XX  *********************************************************/
 734
 735 /* The KM8XX Service Module uses SCC3 for Ethernet */
 736
 737 #ifdef CONFIG_KM8XX
 738 #define PROFF_ENET      PROFF_SCC3              /* Ethernet on SCC3 */
 739 #define CPM_CR_ENET     CPM_CR_CH_SCC3
 740 #define SCC_ENET        2
 741 #define PA_ENET_RXD     ((ushort)0x0010)        /* PA 11 */
 742 #define PA_ENET_TXD     ((ushort)0x0020)        /* PA 10 */
 743 #define PA_ENET_RCLK    ((ushort)0x1000)        /* PA  3 CLK 5 */
 744 #define PA_ENET_TCLK    ((ushort)0x2000)        /* PA  2 CLK 6 */
 745
 746 #define PC_ENET_TENA    ((ushort)0x0004)        /* PC 13 */
 747
 748 #define PC_ENET_RENA    ((ushort)0x0200)        /* PC  6 */
 749 #define PC_ENET_CLSN    ((ushort)0x0100)        /* PC  7 */
 750
 751 /* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
 752  * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
 753  */
 754 #define SICR_ENET_MASK  ((uint)0x00FF0000)
 755 #define SICR_ENET_CLKRT ((uint)0x00250000)
 756 #endif  /* CONFIG_KM8XX */
 757
 758
 759 /***  MHPC  ********************************************************/
 760
 761 #if defined(CONFIG_MHPC)
 762 /* This ENET stuff is for the MHPC with ethernet on SCC2.
 763  * Note TENA is on Port B.
 764  */
 765 #define PROFF_ENET      PROFF_SCC2
 766 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 767 #define SCC_ENET        1
 768 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 769 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 770 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA 6 */
 771 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA 5 */
 772 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 773 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC 9 */
 774 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC 8 */
 775
 776 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 777 #define SICR_ENET_CLKRT ((uint)0x00002e00)      /* RCLK-CLK2, TCLK-CLK3 */
 778 #endif  /* CONFIG_MHPC */
 779
 780 /***  NETVIA  *******************************************************/
 781
 782 #if defined(CONFIG_NETVIA)
 783 /* Bits in parallel I/O port registers that have to be set/cleared
 784  * to configure the pins for SCC2 use.
 785  */
 786 #define PROFF_ENET      PROFF_SCC2
 787 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 788 #define SCC_ENET        1
 789 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 790 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 791 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 792 #define PA_ENET_TCLK    ((ushort)0x0800)        /* PA  4 */
 793
 794 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
 795 # define PB_ENET_PDN    ((ushort)0x4000)        /* PB 17 */
 796 #elif CONFIG_NETVIA_VERSION >= 2
 797 # define PC_ENET_PDN    ((ushort)0x0008)        /* PC 12 */
 798 #endif
 799
 800 #define PB_ENET_TENA    ((ushort)0x2000)        /* PB 18 */
 801
 802 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 803 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 804
 805 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 806  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 807  */
 808 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 809 #define SICR_ENET_CLKRT ((uint)0x00002f00)
 810
 811 #endif  /* CONFIG_NETVIA */
 812
 813 /***  SM850  *********************************************************/
 814
 815 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
 816
 817 #ifdef CONFIG_SM850
 818 #define PROFF_ENET      PROFF_SCC3              /* Ethernet on SCC3 */
 819 #define CPM_CR_ENET     CPM_CR_CH_SCC3
 820 #define SCC_ENET        2
 821 #define PB_ENET_RXD     ((uint)0x00000004)      /* PB 29 */
 822 #define PB_ENET_TXD     ((uint)0x00000002)      /* PB 30 */
 823 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 824 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 825
 826 #define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
 827 #define PC_ENET_TENA    ((ushort)0x0004)        /* PC 13 */
 828
 829 #define PC_ENET_RENA    ((ushort)0x0800)        /* PC  4 */
 830 #define PC_ENET_CLSN    ((ushort)0x0400)        /* PC  5 */
 831
 832 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 833  * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
 834  */
 835 #define SICR_ENET_MASK  ((uint)0x00FF0000)
 836 #define SICR_ENET_CLKRT ((uint)0x00260000)
 837 #endif  /* CONFIG_SM850 */
 838
 839 /***  SPD823TS  ******************************************************/
 840
 841 #ifdef CONFIG_SPD823TS
 842 /* Bits in parallel I/O port registers that have to be set/cleared
 843  * to configure the pins for SCC2 use.
 844  */
 845 #define PROFF_ENET      PROFF_SCC2              /* Ethernet on SCC2 */
 846 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 847 #define SCC_ENET        1
 848 #define PA_ENET_MDC     ((ushort)0x0001)        /* PA 15 !!! */
 849 #define PA_ENET_MDIO    ((ushort)0x0002)        /* PA 14 !!! */
 850 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 851 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 852 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 853 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 854
 855 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 856
 857 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 858 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 859 #define PC_ENET_RESET   ((ushort)0x0100)        /* PC  7 !!! */
 860
 861 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
 862  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 863  */
 864 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 865 #define SICR_ENET_CLKRT ((uint)0x00002E00)
 866 #endif  /* CONFIG_SPD823TS */
 867
 868 /***  MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI  **********/
 869
 870 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
 871     defined(CONFIG_R360MPI) || \
 872     defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
 873     defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
 874     defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
 875     defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
 876
 877 /* Bits in parallel I/O port registers that have to be set/cleared
 878  * to configure the pins for SCC2 use.
 879  */
 880 #define PROFF_ENET      PROFF_SCC2
 881 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 882 #if (!defined(CONFIG_TK885D))   /* TK885D does not use SCC Ethernet */
 883 #define SCC_ENET        1
 884 #endif
 885 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 886 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 887 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 888 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 889
 890 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 891
 892 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 893 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 894 #if defined(CONFIG_R360MPI)
 895 #define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
 896 #endif   /* CONFIG_R360MPI */
 897
 898 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 899  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 900  */
 901 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 902 #define SICR_ENET_CLKRT ((uint)0x00002600)
 903
 904 # ifdef CONFIG_FEC_ENET         /* Use FEC for Fast Ethernet */
 905 #define FEC_ENET
 906 # endif /* CONFIG_FEC_ENET */
 907
 908 #endif  /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
 909
 910 /***  TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M  *********************/
 911
 912 #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
 913     defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
 914     defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
 915     defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
 916
 917 # ifdef CONFIG_SCC1_ENET        /* use SCC for 10Mbps Ethernet  */
 918
 919 /* Bits in parallel I/O port registers that have to be set/cleared
 920  * to configure the pins for SCC1 use.
 921  */
 922 #define PROFF_ENET      PROFF_SCC1
 923 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 924 #define SCC_ENET        0
 925 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
 926 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
 927 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 928 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 929
 930 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
 931 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
 932 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
 933
 934 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 935  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 936  */
 937 #define SICR_ENET_MASK  ((uint)0x000000ff)
 938 #define SICR_ENET_CLKRT ((uint)0x00000026)
 939
 940 # endif /* CONFIG_SCC1_ENET */
 941
 942 # ifdef CONFIG_FEC_ENET         /* Use FEC for Fast Ethernet */
 943
 944 #define FEC_ENET
 945
 946 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 947 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 948 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 949 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 950 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 951 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 952 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 953 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 954 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 955 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 956 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 957 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 958 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 959
 960 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 961
 962 # endif /* CONFIG_FEC_ENET */
 963 #endif  /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
 964
 965 /*********************************************************************/
 966
 967 /* SCC Event register as used by Ethernet.
 968 */
 969 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 970 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 971 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 972 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 973 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 974 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 975
 976 /* SCC Mode Register (PSMR) as used by Ethernet.
 977 */
 978 #define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 979 #define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
 980 #define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
 981 #define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
 982 #define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 983 #define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 984 #define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 985 #define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 986 #define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 987 #define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 988 #define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
 989 #define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
 990 #define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 991
 992 /* Buffer descriptor control/status used by Ethernet receive.
 993 */
 994 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
 995 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
 996 #define BD_ENET_RX_INTR         ((ushort)0x1000)
 997 #define BD_ENET_RX_LAST         ((ushort)0x0800)
 998 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
 999 #define BD_ENET_RX_MISS         ((ushort)0x0100)
1000 #define BD_ENET_RX_LG           ((ushort)0x0020)
1001 #define BD_ENET_RX_NO           ((ushort)0x0010)
1002 #define BD_ENET_RX_SH           ((ushort)0x0008)
1003 #define BD_ENET_RX_CR           ((ushort)0x0004)
1004 #define BD_ENET_RX_OV           ((ushort)0x0002)
1005 #define BD_ENET_RX_CL           ((ushort)0x0001)
1006 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
1007
1008 /* Buffer descriptor control/status used by Ethernet transmit.
1009 */
1010 #define BD_ENET_TX_READY        ((ushort)0x8000)
1011 #define BD_ENET_TX_PAD          ((ushort)0x4000)
1012 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
1013 #define BD_ENET_TX_INTR         ((ushort)0x1000)
1014 #define BD_ENET_TX_LAST         ((ushort)0x0800)
1015 #define BD_ENET_TX_TC           ((ushort)0x0400)
1016 #define BD_ENET_TX_DEF          ((ushort)0x0200)
1017 #define BD_ENET_TX_HB           ((ushort)0x0100)
1018 #define BD_ENET_TX_LC           ((ushort)0x0080)
1019 #define BD_ENET_TX_RL           ((ushort)0x0040)
1020 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
1021 #define BD_ENET_TX_UN           ((ushort)0x0002)
1022 #define BD_ENET_TX_CSL          ((ushort)0x0001)
1023 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
1024
1025 /* SCC as UART
1026 */
1027 typedef struct scc_uart {
1028         sccp_t  scc_genscc;
1029         uint    scc_res1;       /* Reserved */
1030         uint    scc_res2;       /* Reserved */
1031         ushort  scc_maxidl;     /* Maximum idle chars */
1032         ushort  scc_idlc;       /* temp idle counter */
1033         ushort  scc_brkcr;      /* Break count register */
1034         ushort  scc_parec;      /* receive parity error counter */
1035         ushort  scc_frmec;      /* receive framing error counter */
1036         ushort  scc_nosec;      /* receive noise counter */
1037         ushort  scc_brkec;      /* receive break condition counter */
1038         ushort  scc_brkln;      /* last received break length */
1039         ushort  scc_uaddr1;     /* UART address character 1 */
1040         ushort  scc_uaddr2;     /* UART address character 2 */
1041         ushort  scc_rtemp;      /* Temp storage */
1042         ushort  scc_toseq;      /* Transmit out of sequence char */
1043         ushort  scc_char1;      /* control character 1 */
1044         ushort  scc_char2;      /* control character 2 */
1045         ushort  scc_char3;      /* control character 3 */
1046         ushort  scc_char4;      /* control character 4 */
1047         ushort  scc_char5;      /* control character 5 */
1048         ushort  scc_char6;      /* control character 6 */
1049         ushort  scc_char7;      /* control character 7 */
1050         ushort  scc_char8;      /* control character 8 */
1051         ushort  scc_rccm;       /* receive control character mask */
1052         ushort  scc_rccr;       /* receive control character register */
1053         ushort  scc_rlbc;       /* receive last break character */
1054 } scc_uart_t;
1055
1056 /* SCC Event and Mask registers when it is used as a UART.
1057 */
1058 #define UART_SCCM_GLR           ((ushort)0x1000)
1059 #define UART_SCCM_GLT           ((ushort)0x0800)
1060 #define UART_SCCM_AB            ((ushort)0x0200)
1061 #define UART_SCCM_IDL           ((ushort)0x0100)
1062 #define UART_SCCM_GRA           ((ushort)0x0080)
1063 #define UART_SCCM_BRKE          ((ushort)0x0040)
1064 #define UART_SCCM_BRKS          ((ushort)0x0020)
1065 #define UART_SCCM_CCR           ((ushort)0x0008)
1066 #define UART_SCCM_BSY           ((ushort)0x0004)
1067 #define UART_SCCM_TX            ((ushort)0x0002)
1068 #define UART_SCCM_RX            ((ushort)0x0001)
1069
1070 /* The SCC PSMR when used as a UART.
1071 */
1072 #define SCU_PSMR_FLC            ((ushort)0x8000)
1073 #define SCU_PSMR_SL             ((ushort)0x4000)
1074 #define SCU_PSMR_CL             ((ushort)0x3000)
1075 #define SCU_PSMR_UM             ((ushort)0x0c00)
1076 #define SCU_PSMR_FRZ            ((ushort)0x0200)
1077 #define SCU_PSMR_RZS            ((ushort)0x0100)
1078 #define SCU_PSMR_SYN            ((ushort)0x0080)
1079 #define SCU_PSMR_DRT            ((ushort)0x0040)
1080 #define SCU_PSMR_PEN            ((ushort)0x0010)
1081 #define SCU_PSMR_RPM            ((ushort)0x000c)
1082 #define SCU_PSMR_REVP           ((ushort)0x0008)
1083 #define SCU_PSMR_TPM            ((ushort)0x0003)
1084 #define SCU_PSMR_TEVP           ((ushort)0x0003)
1085
1086 /* CPM Transparent mode SCC.
1087  */
1088 typedef struct scc_trans {
1089         sccp_t  st_genscc;
1090         uint    st_cpres;       /* Preset CRC */
1091         uint    st_cmask;       /* Constant mask for CRC */
1092 } scc_trans_t;
1093
1094 #define BD_SCC_TX_LAST          ((ushort)0x0800)
1095
1096 /* IIC parameter RAM.
1097 */
1098 typedef struct iic {
1099         ushort  iic_rbase;      /* Rx Buffer descriptor base address */
1100         ushort  iic_tbase;      /* Tx Buffer descriptor base address */
1101         u_char  iic_rfcr;       /* Rx function code */
1102         u_char  iic_tfcr;       /* Tx function code */
1103         ushort  iic_mrblr;      /* Max receive buffer length */
1104         uint    iic_rstate;     /* Internal */
1105         uint    iic_rdp;        /* Internal */
1106         ushort  iic_rbptr;      /* Internal */
1107         ushort  iic_rbc;        /* Internal */
1108         uint    iic_rxtmp;      /* Internal */
1109         uint    iic_tstate;     /* Internal */
1110         uint    iic_tdp;        /* Internal */
1111         ushort  iic_tbptr;      /* Internal */
1112         ushort  iic_tbc;        /* Internal */
1113         uint    iic_txtmp;      /* Internal */
1114         uint    iic_res;        /* reserved */
1115         ushort  iic_rpbase;     /* Relocation pointer */
1116         ushort  iic_res2;       /* reserved */
1117 } iic_t;
1118
1119 /* SPI parameter RAM.
1120 */
1121 typedef struct spi {
1122         ushort  spi_rbase;      /* Rx Buffer descriptor base address */
1123         ushort  spi_tbase;      /* Tx Buffer descriptor base address */
1124         u_char  spi_rfcr;       /* Rx function code */
1125         u_char  spi_tfcr;       /* Tx function code */
1126         ushort  spi_mrblr;      /* Max receive buffer length */
1127         uint    spi_rstate;     /* Internal */
1128         uint    spi_rdp;        /* Internal */
1129         ushort  spi_rbptr;      /* Internal */
1130         ushort  spi_rbc;        /* Internal */
1131         uint    spi_rxtmp;      /* Internal */
1132         uint    spi_tstate;     /* Internal */
1133         uint    spi_tdp;        /* Internal */
1134         ushort  spi_tbptr;      /* Internal */
1135         ushort  spi_tbc;        /* Internal */
1136         uint    spi_txtmp;      /* Internal */
1137         uint    spi_res;
1138         ushort  spi_rpbase;     /* Relocation pointer */
1139         ushort  spi_res2;
1140 } spi_t;
1141
1142 /* SPI Mode register.
1143 */
1144 #define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
1145 #define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
1146 #define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
1147 #define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
1148 #define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
1149 #define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
1150 #define SPMODE_EN       ((ushort)0x0100)        /* Enable */
1151 #define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
1152 #define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
1153
1154 #define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
1155 #define SPMODE_PM(x)    ((x) &0xF)
1156
1157 /* HDLC parameter RAM.
1158 */
1159
1160 typedef struct hdlc_pram_s {
1161         /*
1162          * SCC parameter RAM
1163          */
1164         ushort  rbase;          /* Rx Buffer descriptor base address */
1165         ushort  tbase;          /* Tx Buffer descriptor base address */
1166         uchar   rfcr;           /* Rx function code */
1167         uchar   tfcr;           /* Tx function code */
1168         ushort  mrblr;          /* Rx buffer length */
1169         ulong   rstate;         /* Rx internal state */
1170         ulong   rptr;           /* Rx internal data pointer */
1171         ushort  rbptr;          /* rb BD Pointer */
1172         ushort  rcount;         /* Rx internal byte count */
1173         ulong   rtemp;          /* Rx temp */
1174         ulong   tstate;         /* Tx internal state */
1175         ulong   tptr;           /* Tx internal data pointer */
1176         ushort  tbptr;          /* Tx BD pointer */
1177         ushort  tcount;         /* Tx byte count */
1178         ulong   ttemp;          /* Tx temp */
1179         ulong   rcrc;           /* temp receive CRC */
1180         ulong   tcrc;           /* temp transmit CRC */
1181         /*
1182          * HDLC specific parameter RAM
1183          */
1184         uchar   res[4];         /* reserved */
1185         ulong   c_mask;         /* CRC constant */
1186         ulong   c_pres;         /* CRC preset */
1187         ushort  disfc;          /* discarded frame counter */
1188         ushort  crcec;          /* CRC error counter */
1189         ushort  abtsc;          /* abort sequence counter */
1190         ushort  nmarc;          /* nonmatching address rx cnt */
1191         ushort  retrc;          /* frame retransmission cnt */
1192         ushort  mflr;           /* maximum frame length reg */
1193         ushort  max_cnt;        /* maximum length counter */
1194         ushort  rfthr;          /* received frames threshold */
1195         ushort  rfcnt;          /* received frames count */
1196         ushort  hmask;          /* user defined frm addr mask */
1197         ushort  haddr1;         /* user defined frm address 1 */
1198         ushort  haddr2;         /* user defined frm address 2 */
1199         ushort  haddr3;         /* user defined frm address 3 */
1200         ushort  haddr4;         /* user defined frm address 4 */
1201         ushort  tmp;            /* temp */
1202         ushort  tmp_mb;         /* temp */
1203 } hdlc_pram_t;
1204
1205 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
1206  * channels or devices.  All of these are presented to the PPC core
1207  * as a single interrupt.  The CPM interrupt handler dispatches its
1208  * own handlers, in a similar fashion to the PPC core handler.  We
1209  * use the table as defined in the manuals (i.e. no special high
1210  * priority and SCC1 == SCCa, etc...).
1211  */
1212 #define CPMVEC_NR               32
1213 #define CPMVEC_OFFSET           0x00010000
1214 #define CPMVEC_PIO_PC15         ((ushort)0x1f | CPMVEC_OFFSET)
1215 #define CPMVEC_SCC1             ((ushort)0x1e | CPMVEC_OFFSET)
1216 #define CPMVEC_SCC2             ((ushort)0x1d | CPMVEC_OFFSET)
1217 #define CPMVEC_SCC3             ((ushort)0x1c | CPMVEC_OFFSET)
1218 #define CPMVEC_SCC4             ((ushort)0x1b | CPMVEC_OFFSET)
1219 #define CPMVEC_PIO_PC14         ((ushort)0x1a | CPMVEC_OFFSET)
1220 #define CPMVEC_TIMER1           ((ushort)0x19 | CPMVEC_OFFSET)
1221 #define CPMVEC_PIO_PC13         ((ushort)0x18 | CPMVEC_OFFSET)
1222 #define CPMVEC_PIO_PC12         ((ushort)0x17 | CPMVEC_OFFSET)
1223 #define CPMVEC_SDMA_CB_ERR      ((ushort)0x16 | CPMVEC_OFFSET)
1224 #define CPMVEC_IDMA1            ((ushort)0x15 | CPMVEC_OFFSET)
1225 #define CPMVEC_IDMA2            ((ushort)0x14 | CPMVEC_OFFSET)
1226 #define CPMVEC_TIMER2           ((ushort)0x12 | CPMVEC_OFFSET)
1227 #define CPMVEC_RISCTIMER        ((ushort)0x11 | CPMVEC_OFFSET)
1228 #define CPMVEC_I2C              ((ushort)0x10 | CPMVEC_OFFSET)
1229 #define CPMVEC_PIO_PC11         ((ushort)0x0f | CPMVEC_OFFSET)
1230 #define CPMVEC_PIO_PC10         ((ushort)0x0e | CPMVEC_OFFSET)
1231 #define CPMVEC_TIMER3           ((ushort)0x0c | CPMVEC_OFFSET)
1232 #define CPMVEC_PIO_PC9          ((ushort)0x0b | CPMVEC_OFFSET)
1233 #define CPMVEC_PIO_PC8          ((ushort)0x0a | CPMVEC_OFFSET)
1234 #define CPMVEC_PIO_PC7          ((ushort)0x09 | CPMVEC_OFFSET)
1235 #define CPMVEC_TIMER4           ((ushort)0x07 | CPMVEC_OFFSET)
1236 #define CPMVEC_PIO_PC6          ((ushort)0x06 | CPMVEC_OFFSET)
1237 #define CPMVEC_SPI              ((ushort)0x05 | CPMVEC_OFFSET)
1238 #define CPMVEC_SMC1             ((ushort)0x04 | CPMVEC_OFFSET)
1239 #define CPMVEC_SMC2             ((ushort)0x03 | CPMVEC_OFFSET)
1240 #define CPMVEC_PIO_PC5          ((ushort)0x02 | CPMVEC_OFFSET)
1241 #define CPMVEC_PIO_PC4          ((ushort)0x01 | CPMVEC_OFFSET)
1242 #define CPMVEC_ERROR            ((ushort)0x00 | CPMVEC_OFFSET)
1243
1244 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1245
1246 /* CPM interrupt configuration vector.
1247 */
1248 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
1249 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
1250 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
1251 #define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
1252 #define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrrupt */
1253 #define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
1254 #define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
1255 #define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
1256 #endif /* __CPM_8XX__ */