include/configs/ADNPESC1.h

   1 /*
   2  * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
   3  * Stephan Linz <linz@li-pro.net>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /***********************************************************************
  28  * Include the whole NIOS CPU configuration.
  29  *
  30  * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
  31  *
  32  ***********************************************************************/
  33
  34 #if     defined(CONFIG_NIOS_BASE_32)
  35 #include <configs/ADNPESC1_base_32.h>
  36 #else
  37 #error *** CFG_ERROR: you have to setup right NIOS CPU configuration
  38 #endif
  39
  40 /*------------------------------------------------------------------------
  41  * BOARD/CPU -- TOP-LEVEL
  42  *----------------------------------------------------------------------*/
  43 #define CONFIG_NIOS             1               /* NIOS-32 core         */
  44 #define CONFIG_ADNPESC1         1               /* SSV ADNP/ESC1 board  */
  45 #define CONFIG_SYS_CLK_FREQ     CFG_NIOS_CPU_CLK/* 50 MHz core clock    */
  46 #define CFG_HZ                  1000            /* 1 msec time tick     */
  47 #undef  CFG_CLKS_IN_HZ
  48 #define CONFIG_BOARD_EARLY_INIT_F 1     /* enable early board-spec. init*/
  49
  50 /*------------------------------------------------------------------------
  51  * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
  52  *----------------------------------------------------------------------*/
  53 #if     (CFG_NIOS_CPU_SDRAM_SIZE != 0)
  54
  55 #define CFG_SDRAM_BASE          CFG_NIOS_CPU_SDRAM_BASE
  56 #define CFG_SDRAM_SIZE          CFG_NIOS_CPU_SDRAM_SIZE
  57
  58 #else
  59 #error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
  60 #endif
  61
  62 #if     defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
  63
  64 #define CFG_SRAM_BASE           CFG_NIOS_CPU_SRAM_BASE
  65 #define CFG_SRAM_SIZE           CFG_NIOS_CPU_SRAM_SIZE
  66
  67 #else
  68
  69 #undef  CFG_SRAM_BASE
  70 #undef  CFG_SRAM_SIZE
  71
  72 #endif
  73
  74 #define CFG_VECT_BASE           CFG_NIOS_CPU_VEC_BASE
  75
  76 /*------------------------------------------------------------------------
  77  * MEMORY ORGANIZATION - For the most part, you can put things pretty
  78  * much anywhere. This is pretty flexible for Nios. So here we make some
  79  * arbitrary choices & assume that the monitor is placed at the end of
  80  * a memory resource (so you must make sure TEXT_BASE is chosen
  81  * appropriately -- this is very important if you plan to move your
  82  * memory to another place as configured at this time !!!).
  83  *
  84  *      -The heap is placed below the monitor.
  85  *      -Global data is placed below the heap.
  86  *      -The stack is placed below global data (&grows down).
  87  *----------------------------------------------------------------------*/
  88 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256k         */
  89 #define CFG_GBL_DATA_SIZE       128             /* Global data size rsvd*/
  90 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
  91
  92 #define CFG_MONITOR_BASE        TEXT_BASE
  93 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
  94 #define CFG_GBL_DATA_OFFSET     (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
  95 #define CFG_INIT_SP             CFG_GBL_DATA_OFFSET
  96
  97 /*------------------------------------------------------------------------
  98  * FLASH (AM29LV065D)
  99  *----------------------------------------------------------------------*/
 100 #if     (CFG_NIOS_CPU_FLASH_SIZE != 0)
 101
 102 #define CFG_FLASH_BASE          CFG_NIOS_CPU_FLASH_BASE
 103 #define CFG_FLASH_SIZE          CFG_NIOS_CPU_FLASH_SIZE
 104 #define CFG_MAX_FLASH_SECT      128             /* Max # sects per bank */
 105 #define CFG_MAX_FLASH_BANKS     1               /* Max # of flash banks */
 106 #define CFG_FLASH_ERASE_TOUT    8000            /* Erase timeout (msec) */
 107 #define CFG_FLASH_WRITE_TOUT    100             /* Write timeout (msec) */
 108 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size      */
 109
 110 #else
 111 #error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
 112 #endif
 113
 114 /*------------------------------------------------------------------------
 115  * ENVIRONMENT
 116  *----------------------------------------------------------------------*/
 117 #if     (CFG_NIOS_CPU_FLASH_SIZE != 0)
 118
 119 #define CFG_ENV_IS_IN_FLASH     1               /* Environment in flash */
 120
 121 /* Mem addr of environment */
 122 #if     defined(CONFIG_NIOS_BASE_32)
 123 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + CFG_MONITOR_LEN)
 124 #else
 125 #error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
 126 #endif
 127
 128 #define CFG_ENV_SIZE            (64 * 1024)     /* 64 KByte (1 sector)  */
 129 #define CONFIG_ENV_OVERWRITE                    /* Serial/eth change Ok */
 130
 131 #else
 132 #define CFG_ENV_IS_NOWHERE      1               /* NO Environment       */
 133 #endif
 134
 135 /*------------------------------------------------------------------------
 136  * NIOS APPLICATION CODE BASE AREA
 137  *----------------------------------------------------------------------*/
 138 #if     ((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000)
 139 #define CFG_ADNPESC1_UPDATE_LOAD_ADDR   "0x2000100"
 140 #define CFG_ADNPESC1_NIOS_APPL_ENTRY    "0x1050000"
 141 #define CFG_ADNPESC1_NIOS_APPL_IDENT    "0x105000c"
 142 #define CFG_ADNPESC1_NIOS_APPL_END      "0x11fffff"
 143 #define CFG_ADNPESC1_FILESYSTEM_BASE    "0x1200000"
 144 #define CFG_ADNPESC1_FILESYSTEM_END     "0x17fffff"
 145 #else
 146 #error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
 147 #endif
 148 #define CFG_ADNPESC1_NIOS_IDENTIFIER    "Nios"
 149
 150 /*------------------------------------------------------------------------
 151  * BOOT ENVIRONMENT
 152  *----------------------------------------------------------------------*/
 153 #ifdef  CONFIG_DNPEVA2                  /* DNP/EVA2 base board */
 154 #define CFG_ADNPESC1_SLED_BOOT_OFF      "sled boot off; "
 155 #define CFG_ADNPESC1_SLED_RED_BLINK     "sled red blink; "
 156 #else
 157 #define CFG_ADNPESC1_SLED_BOOT_OFF
 158 #define CFG_ADNPESC1_SLED_RED_BLINK
 159 #endif
 160
 161 #define CONFIG_BOOTDELAY        5
 162 #define CONFIG_BOOTCOMMAND                                              \
 163         "if itest.s *$appl_ident_addr == \"$appl_ident_str\"; "         \
 164         "then "                                                         \
 165                 "wd off; "                                              \
 166                 CFG_ADNPESC1_SLED_BOOT_OFF                              \
 167                 "go $appl_entry_addr; "                                 \
 168         "else "                                                         \
 169                 CFG_ADNPESC1_SLED_RED_BLINK                             \
 170                 "echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
 171                 "echo *** invalid application at $appl_entry_addr; "    \
 172                 "echo *** stop bootup...; "                             \
 173         "fi"
 174
 175 /*------------------------------------------------------------------------
 176  * EXTRA ENVIRONMENT
 177  *----------------------------------------------------------------------*/
 178 #ifdef  CONFIG_DNPEVA2                  /* DNP/EVA2 base board */
 179 #define CFG_ADNPESC1_SLED_YELLO_ON      "sled yellow on; "
 180 #define CFG_ADNPESC1_SLED_YELLO_OFF     "sled yellow off; "
 181 #else
 182 #define CFG_ADNPESC1_SLED_YELLO_ON
 183 #define CFG_ADNPESC1_SLED_YELLO_OFF
 184 #endif
 185
 186 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 187         "update_allowed=0\0"                                            \
 188         "update_load_addr="     CFG_ADNPESC1_UPDATE_LOAD_ADDR   "\0"    \
 189         "appl_entry_addr="      CFG_ADNPESC1_NIOS_APPL_ENTRY    "\0"    \
 190         "appl_end_addr="        CFG_ADNPESC1_NIOS_APPL_END      "\0"    \
 191         "appl_ident_addr="      CFG_ADNPESC1_NIOS_APPL_IDENT    "\0"    \
 192         "appl_ident_str="       CFG_ADNPESC1_NIOS_IDENTIFIER    "\0"    \
 193         "appl_name=ADNPESC1/base32/linux.bin\0"                         \
 194         "appl_update="                                                  \
 195                 "if itest.b $update_allowed != 0; "                     \
 196                 "then "                                                 \
 197                         CFG_ADNPESC1_SLED_YELLO_ON                      \
 198                         "tftp $update_load_addr $appl_name; "           \
 199                         "protect off $appl_entry_addr $appl_end_addr; " \
 200                         "era $appl_entry_addr $appl_end_addr; "         \
 201                         "cp.b $update_load_addr $appl_entry_addr $filesize; "\
 202                         CFG_ADNPESC1_SLED_YELLO_OFF                     \
 203                 "else "                                                 \
 204                         "echo *** update not allowed (update_allowed=$update_allowed); "\
 205                 "fi\0"                                                  \
 206         "fs_base_addr="         CFG_ADNPESC1_FILESYSTEM_BASE    "\0"    \
 207         "fs_end_addr="          CFG_ADNPESC1_FILESYSTEM_END     "\0"    \
 208         "fs_name=ADNPESC1/base32/romfs.img\0"                           \
 209         "fs_update="                                                    \
 210                 "if itest.b $update_allowed != 0; "                     \
 211                 "then "                                                 \
 212                         CFG_ADNPESC1_SLED_YELLO_ON                      \
 213                         "tftp $update_load_addr $fs_name; "             \
 214                         "protect off $fs_base_addr $fs_end_addr; "      \
 215                         "era $fs_base_addr $fs_end_addr; "              \
 216                         "cp.b $update_load_addr $fs_base_addr $filesize; "\
 217                         CFG_ADNPESC1_SLED_YELLO_OFF                     \
 218                 "else "                                                 \
 219                         "echo *** update not allowed (update_allowed=$update_allowed); "\
 220                 "fi\0"                                                  \
 221         "uboot_name=ADNPESC1/base32/u-boot.bin\0"                       \
 222         "uboot_loadnrun="                                               \
 223                 "if ping $serverip; "                                   \
 224                 "then "                                                 \
 225                         CFG_ADNPESC1_SLED_YELLO_ON                      \
 226                         "tftp $update_load_addr $uboot_name; "          \
 227                         "wd off; "                                      \
 228                         "go $update_load_addr; "                        \
 229                 "else "                                                 \
 230                         "echo *** missing connection to $serverip; "    \
 231                         "echo *** check your network and try again...; "\
 232                 "fi\0"
 233
 234 /*------------------------------------------------------------------------
 235  * CONSOLE
 236  *----------------------------------------------------------------------*/
 237 #if     (CFG_NIOS_CPU_UART_NUMS != 0)
 238
 239 #define CFG_NIOS_CONSOLE        CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
 240
 241 #if     (CFG_NIOS_CPU_UART0_BR != 0)
 242 #define CFG_NIOS_FIXEDBAUD      1                  /* Baudrate is fixed */
 243 #define CONFIG_BAUDRATE         CFG_NIOS_CPU_UART0_BR
 244 #else
 245 #undef  CFG_NIOS_FIXEDBAUD
 246 #define CONFIG_BAUDRATE         115200
 247 #endif
 248
 249 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 250
 251 #else
 252 #error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
 253 #endif
 254
 255 /*------------------------------------------------------------------------
 256  * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
 257  * so an avalon bus timer is required.
 258  *----------------------------------------------------------------------*/
 259 #if     (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
 260
 261 #if     (CFG_NIOS_CPU_TICK_TIMER == 0)
 262
 263 #define CFG_NIOS_TMRBASE        CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick   */
 264 #define CFG_NIOS_TMRIRQ         CFG_NIOS_CPU_TIMER0_IRQ
 265
 266 #if     (CFG_NIOS_CPU_TIMER0_FP == 1)               /* fixed period */
 267
 268 #if     (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
 269 #define CFG_NIOS_TMRMS          (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
 270 #else
 271 #error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
 272 #endif
 273
 274 #undef  CFG_NIOS_TMRCNT /* no preloadable counter value */
 275
 276 #elif   (CFG_NIOS_CPU_TIMER0_FP == 0)               /* variable period */
 277
 278 #if     (CFG_HZ <= 1000)
 279 #define CFG_NIOS_TMRMS          (1000 / CFG_HZ)
 280 #else
 281 #error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
 282 #endif
 283
 284 #define CFG_NIOS_TMRCNT         (CONFIG_SYS_CLK_FREQ / CFG_HZ)
 285
 286 #else
 287 #error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
 288 #endif
 289
 290 #elif   (CFG_NIOS_CPU_TICK_TIMER == 1)
 291
 292 #define CFG_NIOS_TMRBASE        CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick   */
 293 #define CFG_NIOS_TMRIRQ         CFG_NIOS_CPU_TIMER1_IRQ
 294
 295 #if     (CFG_NIOS_CPU_TIMER1_FP == 1)               /* fixed period */
 296
 297 #if     (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
 298 #define CFG_NIOS_TMRMS          (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
 299 #else
 300 #error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
 301 #endif
 302
 303 #undef  CFG_NIOS_TMRCNT /* no preloadable counter value */
 304
 305 #elif   (CFG_NIOS_CPU_TIMER1_FP == 0)               /* variable period */
 306
 307 #if     (CFG_HZ <= 1000)
 308 #define CFG_NIOS_TMRMS          (1000 / CFG_HZ)
 309 #else
 310 #error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
 311 #endif
 312
 313 #define CFG_NIOS_TMRCNT         (CONFIG_SYS_CLK_FREQ / CFG_HZ)
 314
 315 #else
 316 #error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
 317 #endif
 318
 319 #endif  /* CFG_NIOS_CPU_TICK_TIMER */
 320
 321 #else
 322 #error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
 323 #endif
 324
 325 /*------------------------------------------------------------------------
 326  * WATCHDOG (or better MAX823 supervisory circuite access)
 327  *----------------------------------------------------------------------*/
 328 #define CONFIG_HW_WATCHDOG      1               /* board specific WD    */
 329
 330 #ifdef  CONFIG_HW_WATCHDOG
 331
 332 /* MAX823 supervisor -- watchdog enable port at: */
 333 #if     (CFG_NIOS_CPU_WDENA_PIO == 0)
 334 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO0       /* PIO0         */
 335 #elif   (CFG_NIOS_CPU_WDENA_PIO == 1)
 336 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO1       /* PIO1         */
 337 #elif   (CFG_NIOS_CPU_WDENA_PIO == 2)
 338 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO2       /* PIO2         */
 339 #elif   (CFG_NIOS_CPU_WDENA_PIO == 3)
 340 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO3       /* PIO3         */
 341 #elif   (CFG_NIOS_CPU_WDENA_PIO == 4)
 342 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO4       /* PIO4         */
 343 #elif   (CFG_NIOS_CPU_WDENA_PIO == 5)
 344 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO5       /* PIO5         */
 345 #elif   (CFG_NIOS_CPU_WDENA_PIO == 6)
 346 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO6       /* PIO6         */
 347 #elif   (CFG_NIOS_CPU_WDENA_PIO == 7)
 348 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO7       /* PIO7         */
 349 #elif   (CFG_NIOS_CPU_WDENA_PIO == 8)
 350 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO8       /* PIO8         */
 351 #elif   (CFG_NIOS_CPU_WDENA_PIO == 9)
 352 #define CONFIG_HW_WDENA_BASE    CFG_NIOS_CPU_PIO9       /* PIO9         */
 353 #else
 354 #error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
 355 #endif
 356
 357 /* MAX823 supervisor -- watchdog trigger port at: */
 358 #if     (CFG_NIOS_CPU_WDTOG_PIO == 0)
 359 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO0       /* PIO0         */
 360 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 1)
 361 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO1       /* PIO1         */
 362 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 2)
 363 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO2       /* PIO2         */
 364 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 3)
 365 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO3       /* PIO3         */
 366 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 4)
 367 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO4       /* PIO4         */
 368 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 5)
 369 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO5       /* PIO5         */
 370 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 6)
 371 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO6       /* PIO6         */
 372 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 7)
 373 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO7       /* PIO7         */
 374 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 8)
 375 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO8       /* PIO8         */
 376 #elif   (CFG_NIOS_CPU_WDTOG_PIO == 9)
 377 #define CONFIG_HW_WDTOG_BASE    CFG_NIOS_CPU_PIO9       /* PIO9         */
 378 #else
 379 #error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
 380 #endif
 381
 382 #if     defined(CONFIG_NIOS_BASE_32)            /* NIOS CPU specifics   */
 383 #define CONFIG_HW_WDENA_BIT             0       /* WD enable  @ Bit 0   */
 384 #define CONFIG_HW_WDTOG_BIT             0       /* WD trigger @ Bit 0   */
 385 #define CONFIG_HW_WDPORT_WRONLY 1       /* each WD port wr/only*/
 386 #else
 387 #error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h
 388 #endif
 389
 390 #endif  /* CONFIG_HW_WATCHDOG */
 391
 392 /*------------------------------------------------------------------------
 393  * SERIAL PERIPHAREL INTERFACE
 394  *----------------------------------------------------------------------*/
 395 #if     (CFG_NIOS_CPU_SPI_NUMS == 1)
 396
 397 #define CONFIG_NIOS_SPI         1               /* SPI support active   */
 398 #define CFG_NIOS_SPIBASE        CFG_NIOS_CPU_SPI0
 399 #define CFG_NIOS_SPIBITS        CFG_NIOS_CPU_SPI0_BITS
 400
 401 #define CONFIG_RTC_DS1306       1       /* Dallas 1306 real time clock  */
 402 #define CFG_SPI_RTC_DEVID       0       /*        as 1st SPI device     */
 403
 404 #else
 405 #undef  CONFIG_NIOS_SPI                         /* NO SPI support       */
 406 #endif
 407
 408 /*------------------------------------------------------------------------
 409  * Ethernet -- needs work!
 410  *----------------------------------------------------------------------*/
 411 #if     (CFG_NIOS_CPU_LAN_NUMS == 1)
 412
 413 #if     (CFG_NIOS_CPU_LAN0_TYPE == 0)           /* LAN91C111            */
 414
 415 #define CONFIG_DRIVER_SMC91111                  /* Using SMC91c111      */
 416 #undef  CONFIG_SMC91111_EXT_PHY                 /* Internal PHY         */
 417 #define CONFIG_SMC91111_BASE    (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
 418
 419 #if     (CFG_NIOS_CPU_LAN0_BUSW == 32)
 420 #define CONFIG_SMC_USE_32_BIT   1
 421 #else   /* no */
 422 #undef  CONFIG_SMC_USE_32_BIT
 423 #endif
 424
 425 #elif   (CFG_NIOS_CPU_LAN0_TYPE == 1)           /* CS8900A              */
 426
 427         /********************************************/
 428         /* !!! CS8900 is __not__ tested on NIOS !!! */
 429         /********************************************/
 430 #define CONFIG_DRIVER_CS8900                    /* Using CS8900         */
 431 #define CS8900_BASE             (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
 432
 433 #if     (CFG_NIOS_CPU_LAN0_BUSW == 32)
 434 #undef  CS8900_BUS16
 435 #define CS8900_BUS32            1
 436 #else   /* no */
 437 #define CS8900_BUS16            1
 438 #undef  CS8900_BUS32
 439 #endif
 440
 441 #else
 442 #error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
 443 #endif
 444
 445 #define CONFIG_ETHADDR          02:80:ae:20:60:6f
 446 #define CONFIG_NETMASK          255.255.255.248
 447 #define CONFIG_IPADDR           192.168.161.84
 448 #define CONFIG_SERVERIP         192.168.161.85
 449
 450 #else
 451 #error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
 452 #endif
 453
 454 /*------------------------------------------------------------------------
 455  * STATUS LEDs
 456  *----------------------------------------------------------------------*/
 457 #if     (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
 458
 459 #if     (CFG_NIOS_CPU_LED_PIO == 0)
 460
 461 #define STATUS_LED_BASE                 CFG_NIOS_CPU_PIO0
 462 #define STATUS_LED_BITS                 CFG_NIOS_CPU_PIO0_BITS
 463 #define STATUS_LED_ACTIVE               1 /* LED on for bit == 1 */
 464
 465 #if     (CFG_NIOS_CPU_PIO0_TYPE == 1)
 466 #define STATUS_LED_WRONLY               1
 467 #else
 468 #undef  STATUS_LED_WRONLY
 469 #endif
 470
 471 #elif   (CFG_NIOS_CPU_LED_PIO == 1)
 472
 473 #define STATUS_LED_BASE                 CFG_NIOS_CPU_PIO1
 474 #define STATUS_LED_BITS                 CFG_NIOS_CPU_PIO1_BITS
 475 #define STATUS_LED_ACTIVE               1 /* LED on for bit == 1 */
 476
 477 #if     (CFG_NIOS_CPU_PIO1_TYPE == 1)
 478 #define STATUS_LED_WRONLY               1
 479 #else
 480 #undef  STATUS_LED_WRONLY
 481 #endif
 482
 483 #elif   (CFG_NIOS_CPU_LED_PIO == 2)
 484
 485 #define STATUS_LED_BASE                 CFG_NIOS_CPU_PIO2
 486 #define STATUS_LED_BITS                 CFG_NIOS_CPU_PIO2_BITS
 487 #define STATUS_LED_ACTIVE               1 /* LED on for bit == 1 */
 488
 489 #if     (CFG_NIOS_CPU_PIO2_TYPE == 1)
 490 #define STATUS_LED_WRONLY               1
 491 #else
 492 #undef  STATUS_LED_WRONLY
 493 #endif
 494
 495 #elif   (CFG_NIOS_CPU_LED_PIO == 3)
 496
 497 #error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
 498
 499 #elif   (CFG_NIOS_CPU_LED_PIO == 4)
 500
 501 #error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
 502
 503 #elif   (CFG_NIOS_CPU_LED_PIO == 5)
 504
 505 #error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
 506
 507 #elif   (CFG_NIOS_CPU_LED_PIO == 6)
 508
 509 #error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
 510
 511 #elif   (CFG_NIOS_CPU_LED_PIO == 7)
 512
 513 #error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
 514
 515 #elif   (CFG_NIOS_CPU_LED_PIO == 8)
 516
 517 #error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
 518
 519 #elif   (CFG_NIOS_CPU_LED_PIO == 9)
 520
 521 #error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
 522
 523 #else
 524 #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
 525 #endif
 526
 527 #define CONFIG_STATUS_LED               1 /* enable status led driver */
 528
 529 #define STATUS_LED_BIT                  (1 << 0)        /* LED[0] */
 530 #define STATUS_LED_STATE                STATUS_LED_BLINKING
 531 #define STATUS_LED_BOOT_STATE           STATUS_LED_OFF
 532 #define STATUS_LED_PERIOD               (CFG_HZ / 2)    /* ca. 1 Hz */
 533 #define STATUS_LED_BOOT                 0               /* boot LED */
 534
 535 #if     (STATUS_LED_BITS > 1)
 536 #define STATUS_LED_BIT1                 (1 << 1)        /* LED[1] */
 537 #define STATUS_LED_STATE1               STATUS_LED_OFF
 538 #define STATUS_LED_PERIOD1              (CFG_HZ / 10)   /* ca. 5 Hz */
 539 #define STATUS_LED_RED                  1               /* fail LED */
 540 #endif
 541
 542 #if     (STATUS_LED_BITS > 2)
 543 #define STATUS_LED_BIT2                 (1 << 2)        /* LED[2] */
 544 #define STATUS_LED_STATE2               STATUS_LED_OFF
 545 #define STATUS_LED_PERIOD2              (CFG_HZ / 2)    /* ca. 1 Hz */
 546 #define STATUS_LED_YELLOW               2               /* info LED */
 547 #endif
 548
 549 #if     (STATUS_LED_BITS > 3)
 550 #define STATUS_LED_BIT3                 (1 << 3)        /* LED[3] */
 551 #define STATUS_LED_STATE3               STATUS_LED_OFF
 552 #define STATUS_LED_PERIOD3              (CFG_HZ / 2)    /* ca. 1 Hz */
 553 #define STATUS_LED_GREEN                3               /* info LED */
 554 #endif
 555
 556 #define STATUS_LED_PAR                  1 /* makes status_led.h happy */
 557
 558 #endif  /* CFG_NIOS_CPU_PIO_NUMS */
 559
 560 /*------------------------------------------------------------------------
 561  * Diagnostics / Power On Self Tests
 562  *----------------------------------------------------------------------*/
 563 #define CONFIG_POST                     CFG_POST_RTC
 564 #define CFG_NIOS_POST_WORD_ADDR         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 565
 566 /*
 567  * BOOTP options
 568  */
 569 #define CONFIG_BOOTP_BOOTFILESIZE
 570 #define CONFIG_BOOTP_BOOTPATH
 571 #define CONFIG_BOOTP_GATEWAY
 572 #define CONFIG_BOOTP_HOSTNAME
 573
 574 /*
 575  * Command line configuration.
 576  */
 577 #include <config_cmd_default.h>
 578
 579 #define CONFIG_CMD_BSP
 580 #define CONFIG_CMD_CDP
 581 #define CONFIG_CMD_DHCP
 582 #define CONFIG_CMD_DIAG
 583 #define CONFIG_CMD_DISPLAY
 584 #define CONFIG_CMD_EXT2
 585 #define CONFIG_CMD_IMMAP
 586 #define CONFIG_CMD_IRQ
 587 #define CONFIG_CMD_PING
 588 #define CONFIG_CMD_PORTIO
 589 #define CONFIG_CMD_REGINFO
 590 #define CONFIG_CMD_REISER
 591 #define CONFIG_CMD_SAVES
 592 #define CONFIG_CMD_SDRAM
 593 #define CONFIG_CMD_SNTP
 594
 595 #undef CONFIG_CMD_NFS
 596 #undef CONFIG_CMD_XIMG
 597
 598 #if (CFG_NIOS_CPU_SPI_NUMS == 1)
 599 #define CONFIG_CMD_DATE
 600 #define CONFIG_CMD_SPI
 601 #endif
 602
 603 /*------------------------------------------------------------------------
 604  * KGDB
 605  *----------------------------------------------------------------------*/
 606 #if defined(CONFIG_CMD_KGDB)
 607 #define CONFIG_KGDB_BAUDRATE    9600
 608 #endif
 609
 610 /*------------------------------------------------------------------------
 611  * MISC
 612  *----------------------------------------------------------------------*/
 613 #define CFG_LONGHELP                        /* undef to save memory     */
 614 #define CFG_HUSH_PARSER         1           /* use "hush" command parser
 615                                                undef to save memory     */
 616 #define CFG_PROMPT              "ADNPESC1 > " /* Monitor Command Prompt */
 617 #define CFG_CBSIZE              1024        /* Console I/O Buffer Size  */
 618 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 619 #define CFG_MAXARGS             64          /* max number of command args*/
 620 #define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size */
 621
 622 #ifdef  CFG_HUSH_PARSER
 623 #define CFG_PROMPT_HUSH_PS2     "[]> "
 624 #endif
 625
 626 /* Default load address */
 627 #if     (CFG_SRAM_SIZE != 0)
 628
 629 /* default in SRAM */
 630 #define CFG_LOAD_ADDR           CFG_SRAM_BASE
 631
 632 #elif   (CFG_SDRAM_SIZE != 0)
 633
 634 /* default in SDRAM */
 635 #if     (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
 636 #if 1
 637 #define CFG_LOAD_ADDR           (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
 638 #else
 639 #define CFG_LOAD_ADDR           (CFG_SDRAM_BASE + 0x400000)
 640 #endif
 641 #else
 642 #define CFG_LOAD_ADDR           CFG_SDRAM_BASE
 643 #endif
 644
 645 #else
 646 #undef  CFG_LOAD_ADDR           /* force error break */
 647 #endif
 648
 649 /* MEM test area */
 650 #if     (CFG_SDRAM_SIZE != 0)
 651
 652 /* SDRAM begin to stack area (1MB stack) */
 653 #if     (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
 654 #if 0
 655 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
 656 #else
 657 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE + 0x400000)
 658 #endif
 659 #else
 660 #define CFG_MEMTEST_START       CFG_SDRAM_BASE
 661 #endif
 662
 663 #define CFG_MEMTEST_END         (CFG_INIT_SP - (1024 * 1024))
 664 #define CFG_MEMTEST_END         (CFG_INIT_SP - (1024 * 1024))
 665
 666 #else
 667 #undef  CFG_MEMTEST_START       /* force error break */
 668 #undef  CFG_MEMTEST_END
 669 #endif
 670
 671 /*
 672  * JFFS2 partitions
 673  *
 674  */
 675 /* No command line, one static partition */
 676 #undef CONFIG_JFFS2_CMDLINE
 677 #define CONFIG_JFFS2_DEV                "nor"
 678 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 679 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 680
 681 /* mtdparts command line support */
 682 /*
 683 #define CONFIG_JFFS2_CMDLINE
 684 #define MTDIDS_DEFAULT          ""
 685 #define MTDPARTS_DEFAULT        ""
 686 */
 687
 688 #endif  /* __CONFIG_H */