include/configs/AMX860.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1
  37 #define CONFIG_AMX860           1
  38
  39 #define CONFIG_SYS_TEXT_BASE    0x40000000
  40
  41 #undef  CONFIG_8xx_CONS_SMC1            /* Console is on SCC2           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #define CONFIG_8xx_CONS_SCC2    1
  44 #undef  CONFIG_8xx_CONS_NONE
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  47
  48 #define MPC8XX_FACT             10              /* Multiply by 10       */
  49 #define MPC8XX_XIN              5000000                 /* 5 MHz in     */
  50 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
  51
  52 #if 0
  53 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  54 #else
  55 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  56 #endif
  57
  58 #define CONFIG_BOOTCOMMAND                                                      \
  59         "bootp;"                                                                \
  60         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  61         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  62         "bootm"                         /* autoboot command */
  63
  64 #undef CONFIG_BOOTARGS
  65
  66 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  67
  68 #define CONFIG_SCC1_ENET        1       /* use SCC1 ethernet */
  69
  70 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  71
  72
  73 /*
  74  * Command line configuration.
  75  */
  76 #include <config_cmd_default.h>
  77
  78 #define CONFIG_CMD_DHCP
  79 #define CONFIG_CMD_DATE
  80 #define CONFIG_CMD_NFS
  81 #define CONFIG_CMD_SNTP
  82
  83
  84 #if defined(CONFIG_CMD_KGDB)
  85 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
  86 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
  87 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
  88 #define CONFIG_KGDB_INDEX       1       /* which serial channel for kgdb */
  89 #define CONFIG_KGDB_BAUDRATE    9600    /* speed to run kgdb serial port at */
  90 #endif
  91
  92
  93 /*
  94  * BOOTP options
  95  */
  96 #define CONFIG_BOOTP_BOOTFILESIZE
  97 #define CONFIG_BOOTP_BOOTPATH
  98 #define CONFIG_BOOTP_GATEWAY
  99 #define CONFIG_BOOTP_HOSTNAME
 100 #define CONFIG_BOOTP_SUBNETMASK
 101
 102
 103 /*
 104  * Miscellaneous configurable options
 105  */
 106 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 107 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 108 #if defined(CONFIG_CMD_KGDB)
 109 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 110 #else
 111 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 112 #endif
 113 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 114 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 115 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 116
 117 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 118 #define CONFIG_SYS_MEMTEST_END          0x0200000       /* 1 ... 4 MB in DRAM   */
 119
 120 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 121
 122 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 123
 124 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 125
 126 /*
 127  * Low Level Configuration Settings
 128  * (address mappings, register initial values, etc.)
 129  * You should know what you are doing if you make changes here.
 130  */
 131
 132 /*-----------------------------------------------------------------------
 133  * Internal Memory Mapped Register
 134  */
 135 #define CONFIG_SYS_IMMR                 0xFF000000
 136
 137 /*-----------------------------------------------------------------------
 138  * Definitions for initial stack pointer and data area (in DPRAM)
 139  */
 140 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 141 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 142 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 143 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 144
 145 /*-----------------------------------------------------------------------
 146  * Start addresses for the final memory configuration
 147  * (Set up by the startup code)
 148  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 149  */
 150 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 151 #define CONFIG_SYS_FLASH_BASE           0x40000000
 152 #if defined(DEBUG)
 153 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 154 #else
 155 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 156 #endif
 157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 158 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 159
 160 /*
 161  * U-Boot for AMX board supports two types of memory extension
 162  * modules: one that provides 4 MB flash memory, and another one with
 163  * 16 MB EDO DRAM.
 164  *
 165  * The flash module swaps the CS0 and CS1 signals: if the module is
 166  * installed, CS0 is connected to Flash on the module and CS1 is
 167  * connected to the on-board Flash. This means that you must intall
 168  * U-Boot when the Flash module is plugged in, if you plan to use
 169  * it.
 170  *
 171  * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
 172  * must be defined. The DRAM module uses CS1.
 173  *
 174  * Only one of these modules may be installed at a time. If U-Boot
 175  * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
 176  * work if the Flash extension module is installed instead of the
 177  * DRAM module.
 178  */
 179 #define CONFIG_AMX_RAM_EXT      /* 16Mb Ext. DRAM module support */
 180
 181 /*
 182  * For booting Linux, the board info and command line data
 183  * have to be in the first 8 MB of memory, since this is
 184  * the maximum mapped by the Linux kernel during initialization.
 185  *
 186  * Use 4 MB for without and 8 MB with 16 MB DRAM extension module
 187  * (CONFIG_AMX_RAM_EXT)
 188  */
 189 #ifdef CONFIG_AMX_RAM_EXT
 190 # define        CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 191 #else
 192 # define        CONFIG_SYS_BOOTMAPSZ    (4 << 20)       /* Initial Memory map for Linux */
 193 #endif
 194 /*-----------------------------------------------------------------------
 195  * FLASH organization
 196  */
 197 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       35      /* max number of sectors on one chip    */
 199
 200 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 201 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 202
 203 #define CONFIG_ENV_IS_IN_FLASH  1
 204 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 205 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 206
 207 /*-----------------------------------------------------------------------
 208  * Cache Configuration
 209  */
 210 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 211 #if defined(CONFIG_CMD_KGDB)
 212 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 213 #endif
 214
 215 /*-----------------------------------------------------------------------
 216  * SYPCR - System Protection Control                                    11-9
 217  * SYPCR can only be written once after reset!
 218  *-----------------------------------------------------------------------
 219  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 220  */
 221 #if defined(CONFIG_WATCHDOG)
 222 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 223                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 224 #else
 225 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 226 #endif
 227
 228 /*-----------------------------------------------------------------------
 229  * SIUMCR - SIU Module Configuration                                    11-6
 230  *-----------------------------------------------------------------------
 231  * PCMCIA config., multi-function pin tri-state
 232  */
 233 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 234
 235 /*-----------------------------------------------------------------------
 236  * TBSCR - Time Base Status and Control                                 11-26
 237  *-----------------------------------------------------------------------
 238  * Clear Reference Interrupt Status, Timebase freezing enabled
 239  */
 240 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 241
 242 /*-----------------------------------------------------------------------
 243  * PISCR - Periodic Interrupt Status and Control                11-31
 244  *-----------------------------------------------------------------------
 245  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 246  */
 247 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 248
 249 /*-----------------------------------------------------------------------
 250  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 251  *-----------------------------------------------------------------------
 252  * set the PLL, the low-power modes and the reset control (15-29)
 253  */
 254 #define CONFIG_SYS_PLPRCR       (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 255                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 256
 257 /*-----------------------------------------------------------------------
 258  * SCCR - System Clock and reset Control Register               15-27
 259  *-----------------------------------------------------------------------
 260  * Set clock output, timebase and RTC source and divider,
 261  * power management and some other internal clocks
 262  */
 263 #define SCCR_MASK       SCCR_EBDF11
 264 #define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 265
 266 #define CONFIG_SYS_DER          0
 267
 268 /*
 269  * Init Memory Controller:
 270  *
 271  * BR0/1 and OR0/1 (FLASH)
 272  */
 273
 274 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 275 #ifndef CONFIG_AMX_RAM_EXT
 276 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #1        */
 277 #endif
 278
 279 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 280 #define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000      /* OR addr mask */
 281
 282 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 283 /*                               0x00000800     0x00000400 0x00000100 0x00000030     0x00000004 */
 284 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 285
 286 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 287
 288 #define CONFIG_SYS_OR0_PRELIM   0xFFC00954      /* Real values for the board */
 289 #define CONFIG_SYS_BR0_PRELIM   0x40000001      /* Real values for the board */
 290
 291 #ifndef CONFIG_AMX_RAM_EXT
 292 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 293 #define CONFIG_SYS_OR1_PRELIM   0xFFC00954      /* Real values for the board */
 294 #define CONFIG_SYS_BR1_PRELIM   0x60000001      /* Real values for the board */
 295 #endif
 296
 297 /* DSP ("Glue") Xilinx */
 298 #define CONFIG_SYS_OR6_PRELIM   0xFFFF8000      /* 32kB, 15 waits, cs after addr, no bursts */
 299 #define CONFIG_SYS_BR6_PRELIM   0x60000401      /* use GPCM for CS generation, 8 bit port */
 300
 301 #endif  /* __CONFIG_H */