include/configs/AP1000.h

   1 /*
   2  * AMIRIX.h: AMIRIX specific config options
   3  *
   4  * Author : Frank Smith (smith at amirix dot com)
   5  *
   6  * Derived from : other configuration header files in this tree
   7  *
   8  * This software may be used and distributed according to the terms of
   9  * the GNU General Public License (GPL) version 2, incorporated herein by
  10  * reference. Drivers based on or derived from this code fall under the GPL
  11  * and must retain the authorship, copyright and this license notice. This
  12  * file is not a complete program and may only be used when the entire
  13  * program is licensed under the GPL.
  14  *
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  * (easy to change)
  23  */
  24
  25 #undef DEBUG
  26
  27 #define CONFIG_405  1      /* This is a PPC405 CPU     */
  28 #define CONFIG_4xx  1      /* ...member of PPC4xx family   */
  29
  30 #define CONFIG_AP1000  1   /* ...on an AP1000 board    */
  31
  32 #define CONFIG_PCI 1
  33
  34 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
  35 #define CFG_PROMPT                      "0> "
  36 #define CFG_PROMPT_HUSH_PS2     "> "
  37
  38 #define CONFIG_COMMAND_EDIT 1
  39 #define CONFIG_COMMAND_HISTORY 1
  40 #define CONFIG_COMPLETE_ADDRESSES 1
  41
  42 #define CFG_ENV_IS_IN_FLASH     1
  43 #define CFG_FLASH_USE_BUFFER_WRITE
  44
  45 #ifdef CFG_ENV_IS_IN_NVRAM
  46 #undef CFG_ENV_IS_IN_FLASH
  47 #else
  48 #ifdef CFG_ENV_IS_IN_FLASH
  49 #undef CFG_ENV_IS_IN_NVRAM
  50 #endif
  51 #endif
  52
  53 #define CONFIG_BAUDRATE     57600
  54 #define CONFIG_BOOTDELAY    3  /* autoboot after 3 seconds */
  55
  56 #define CONFIG_BOOTCOMMAND  ""      /* autoboot command */
  57
  58 /* Size (bytes) of interrupt driven serial port buffer.
  59  * Set to 0 to use polling instead of interrupts.
  60  * Setting to 0 will also disable RTS/CTS handshaking.
  61  */
  62 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
  63
  64 #define CONFIG_BOOTARGS     "console=ttyS0,57600"
  65
  66 #define CONFIG_LOADS_ECHO   1   /* echo on for serial download  */
  67 #define CFG_LOADS_BAUD_CHANGE   1   /* allow baudrate change    */
  68
  69 #define CONFIG_COMMANDS        ( (CONFIG_CMD_DFL & \
  70                 (~CFG_CMD_RTC) & ~(CFG_CMD_I2C)) | \
  71                 CFG_CMD_IRQ | \
  72                 CFG_CMD_PCI | \
  73                 CFG_CMD_DHCP | \
  74                 CFG_CMD_ASKENV | \
  75                 CFG_CMD_ELF  | \
  76                 CFG_CMD_PING | \
  77                 CFG_CMD_MVENV  \
  78                                )
  79
  80 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  81 #include <cmd_confdefs.h>
  82
  83 #undef CONFIG_WATCHDOG          /* watchdog disabled        */
  84
  85 #define CONFIG_SYS_CLK_FREQ 30000000
  86
  87 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CFG_LONGHELP            /* undef to save memory     */
  93 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  94 #define CFG_CBSIZE  1024        /* Console I/O Buffer Size  */
  95 #else
  96 #define CFG_CBSIZE  256     /* Console I/O Buffer Size  */
  97 #endif
  98 /* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */
  99 #define CFG_PBSIZE (CFG_CBSIZE+4+16) /* Print Buffer Size */
 100 #define CFG_MAXARGS 16      /* max number of command args   */
 101 #define CFG_BARGSIZE    CFG_CBSIZE  /* Boot Argument Buffer Size    */
 102
 103 #define CFG_ALT_MEMTEST     1
 104 #define CFG_MEMTEST_START   0x00400000  /* memtest works on */
 105 #define CFG_MEMTEST_END     0x01000000  /* 4 ... 16 MB in DRAM  */
 106
 107 /*
 108  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 109  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
 110  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
 111  * The Linux BASE_BAUD define should match this configuration.
 112  *    baseBaud = cpuClock/(uartDivisor*16)
 113  * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
 114  * set Linux BASE_BAUD to 403200.
 115  */
 116 #undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
 117 #undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 118
 119 #define CFG_NS16550_CLK     40000000
 120 #define CFG_DUART_CHAN      0
 121 #define CFG_NS16550_COM1    (0x4C000000 + 0x1000)
 122 #define CFG_NS16550_COM2    (0x4C800000 + 0x1000)
 123 #define CFG_NS16550_REG_SIZE 4
 124 #define CFG_NS16550 1
 125 #define CFG_INIT_CHAN1   1
 126 #define CFG_INIT_CHAN2   0
 127
 128 /* The following table includes the supported baudrates */
 129 #define CFG_BAUDRATE_TABLE  \
 130     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 131
 132 #define CFG_LOAD_ADDR       0x00100000  /* default load address */
 133 #define CFG_EXTBDINFO       1   /* To use extended board_into (bd_t) */
 134
 135 #define CFG_HZ      1000        /* decrementer freq: 1 ms ticks */
 136
 137 /*-----------------------------------------------------------------------
 138  * Start addresses for the final memory configuration
 139  * (Set up by the startup code)
 140  * Please note that CFG_SDRAM_BASE _must_ start at 0
 141  */
 142 #define CFG_SDRAM_BASE      0x00000000
 143 #define CFG_FLASH_BASE      0x20000000
 144 #define CFG_MONITOR_BASE    TEXT_BASE
 145 #define CFG_MONITOR_LEN     (192 * 1024)    /* Reserve 196 kB for Monitor   */
 146 #define CFG_MALLOC_LEN      (128 * 1024)    /* Reserve 128 kB for malloc()  */
 147
 148 /*
 149  * For booting Linux, the board info and command line data
 150  * have to be in the first 8 MB of memory, since this is
 151  * the maximum mapped by the Linux kernel during initialization.
 152  */
 153 #define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 154 /*-----------------------------------------------------------------------
 155  * FLASH organization
 156  */
 157 #define CFG_FLASH_CFI       1
 158 #define CFG_PROGFLASH_BASE  CFG_FLASH_BASE
 159 #define CFG_CONFFLASH_BASE  0x24000000
 160
 161 #define CFG_MAX_FLASH_BANKS 2   /* max number of memory banks       */
 162 #define CFG_MAX_FLASH_SECT  256 /* max number of sectors on one chip    */
 163
 164 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)  */
 165 #define CFG_FLASH_WRITE_TOUT    500 /* Timeout for Flash Write (in ms)  */
 166
 167 #define CFG_FLASH_PROTECTION    1   /* use hardware protection      */
 168
 169 /* BEG ENVIRONNEMENT FLASH */
 170 #ifdef CFG_ENV_IS_IN_FLASH
 171 #define CFG_ENV_OFFSET      0x00040000 /* Offset of Environment Sector  */
 172 #define CFG_ENV_SIZE        0x1000  /* Total Size of Environment Sector */
 173 #define CFG_ENV_SECT_SIZE   0x20000 /* see README - env sector total size   */
 174 #endif
 175 /* END ENVIRONNEMENT FLASH */
 176 /*-----------------------------------------------------------------------
 177  * NVRAM organization
 178  */
 179 #define CFG_NVRAM_BASE_ADDR 0xf0000000  /* NVRAM base address   */
 180 #define CFG_NVRAM_SIZE      0x1ff8      /* NVRAM size   */
 181
 182 #ifdef CFG_ENV_IS_IN_NVRAM
 183 #define CFG_ENV_SIZE        0x1000      /* Size of Environment vars */
 184 #define CFG_ENV_ADDR        \
 185     (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)   /* Env  */
 186 #endif
 187 /*-----------------------------------------------------------------------
 188  * Cache Configuration
 189  */
 190 #define CFG_DCACHE_SIZE     16384
 191 #define CFG_CACHELINE_SIZE  32
 192 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 193 #define CFG_CACHELINE_SHIFT 5   /* log base 2 of the above value    */
 194 #endif
 195
 196 /*
 197  * Init Memory Controller:
 198  *
 199  * BR0/1 and OR0/1 (FLASH)
 200  */
 201
 202 #define FLASH_BASE0_PRELIM  CFG_FLASH_BASE  /* FLASH bank #0    */
 203 #define FLASH_BASE1_PRELIM  0       /* FLASH bank #1    */
 204
 205 /* Configuration Port location */
 206 #define CONFIG_PORT_ADDR    0xF0000500
 207
 208 /*-----------------------------------------------------------------------
 209  * Definitions for initial stack pointer and data area (in DPRAM)
 210  */
 211
 212 #define CFG_INIT_RAM_ADDR       0x400000  /* inside of SDRAM                     */
 213 #define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
 214 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 215 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 216 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 217
 218 /*-----------------------------------------------------------------------
 219  * Definitions for Serial Presence Detect EEPROM address
 220  * (to get SDRAM settings)
 221  */
 222 #define SPD_EEPROM_ADDRESS      0x50
 223
 224 /*
 225  * Internal Definitions
 226  *
 227  * Boot Flags
 228  */
 229 #define BOOTFLAG_COLD   0x01        /* Normal Power-On: Boot from FLASH */
 230 #define BOOTFLAG_WARM   0x02        /* Software reboot          */
 231
 232 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 233 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 234 #define CONFIG_KGDB_SER_INDEX   2   /* which serial port to use */
 235 #endif
 236
 237 /* JFFS2 stuff */
 238
 239 #define CFG_JFFS2_FIRST_BANK 0
 240 #define CFG_JFFS2_NUM_BANKS 1
 241 #define CFG_JFFS2_FIRST_SECTOR 1
 242
 243 #define CONFIG_NET_MULTI
 244 #define CONFIG_E1000
 245
 246 #define CFG_ETH_DEV_FN     0x0800
 247 #define CFG_ETH_IOBASE     0x31000000
 248 #define CFG_ETH_MEMBASE    0x32000000
 249
 250 #endif  /* __CONFIG_H */