include/configs/APC405.h

   1 /*
   2  * (C) Copyright 2005-2008
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2004
   6  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  38 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  39 #define CONFIG_APCG405          1       /* ...on a APC405 board         */
  40
  41 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  42 #define CONFIG_BOARD_EARLY_INIT_R 1
  43 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  44
  45 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  46
  47 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  48
  49 #define CONFIG_BAUDRATE         115200
  50 #define CONFIG_BOOTDELAY        1       /* autoboot after 3 seconds     */
  51
  52 #undef  CONFIG_BOOTARGS
  53
  54 #define CFG_USB_LOAD_COMMAND    "fatload usb 0 200000 pImage;"          \
  55                                 "fatload usb 0 300000 pImage.initrd"
  56 #define CFG_USB_SELF_COMMAND    "usb start;run usb_load;usb stop;"      \
  57                                 "run ramargs addip addcon usbargs;"     \
  58                                 "bootm 200000 300000"
  59 #define CFG_USB_ARGS            "setenv bootargs $(bootargs) usbboot=1"
  60
  61 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  62         "hostname=abg405\0"                                             \
  63         "bd_type=abg405\0"                                              \
  64         "serial#=AA0000\0"                                              \
  65         "kernel_addr=fe000000\0"                                        \
  66         "ramdisk_addr=fe100000\0"                                       \
  67         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  68         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  69         "nfsroot=$(serverip):$(rootpath)\0"                             \
  70         "addip=setenv bootargs $(bootargs) "                            \
  71                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
  72                 ":$(hostname)::off panic=1\0"                           \
  73         "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)"  \
  74                 " $(optargs)\0"                                         \
  75         "flash_self=run ramargs addip addcon;"                          \
  76                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
  77         "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;"          \
  78                 "bootm\0"                                               \
  79         "rootpath=/tftpboot/abg405/target_root\0"                       \
  80         "img=/tftpboot/abg405/pImage\0"                                 \
  81         "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0"                \
  82         "update=protect off fff80000 ffffffff;era fff80000 ffffffff;"   \
  83                 "cp.b 100000 fff80000 80000\0"                          \
  84         "ipaddr=10.0.111.111\0"                                         \
  85         "netmask=255.255.0.0\0"                                         \
  86         "serverip=10.0.0.190\0"                                         \
  87         "splashimage=ffe80000\0"                                        \
  88         "usb_load="CFG_USB_LOAD_COMMAND"\0"                             \
  89         "usb_self="CFG_USB_SELF_COMMAND"\0"                             \
  90         "usbargs="CFG_USB_ARGS"\0"                                      \
  91         ""
  92 #define CONFIG_BOOTCOMMAND      "run flash_self;run usb_self"
  93
  94 #define CONFIG_ETHADDR          00:02:27:8e:00:00
  95
  96 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  97 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  98
  99 #define CONFIG_NET_MULTI        1
 100 #undef  CONFIG_HAS_ETH1
 101
 102 #define CONFIG_MII              1       /* MII PHY management           */
 103 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 104 #define CONFIG_LXT971_NO_SLEEP  1
 105 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() */
 106
 107 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 108
 109 /*
 110  * BOOTP options
 111  */
 112 #define CONFIG_BOOTP_BOOTFILESIZE
 113 #define CONFIG_BOOTP_BOOTPATH
 114 #define CONFIG_BOOTP_GATEWAY
 115 #define CONFIG_BOOTP_HOSTNAME
 116
 117 /*
 118  * Command line configuration.
 119  */
 120 #include <config_cmd_default.h>
 121
 122 #define CONFIG_CMD_DHCP
 123 #define CONFIG_CMD_PCI
 124 #define CONFIG_CMD_IRQ
 125 #define CONFIG_CMD_IDE
 126 #define CONFIG_CMD_FAT
 127 #define CONFIG_CMD_ELF
 128 #define CONFIG_CMD_DATE
 129 #define CONFIG_CMD_I2C
 130 #define CONFIG_CMD_MII
 131 #define CONFIG_CMD_PING
 132 #define CONFIG_CMD_EEPROM
 133 #define CONFIG_CMD_USB
 134 #define CONFIG_CMD_AUTOSCRIPT
 135
 136 #define CONFIG_MAC_PARTITION
 137 #define CONFIG_DOS_PARTITION
 138
 139 #define CONFIG_SUPPORT_VFAT
 140
 141 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via CF or USB */
 142
 143 #undef  CONFIG_WATCHDOG                 /* watchdog disabled */
 144
 145 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
 146 #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
 147
 148 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
 149
 150 /*
 151  * Miscellaneous configurable options
 152  */
 153 #define CFG_LONGHELP                    /* undef to save memory */
 154 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 155 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 156
 157 #if defined(CONFIG_CMD_KGDB)
 158 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 159 #else
 160 #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 161 #endif
 162 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 163 #define CFG_MAXARGS     16              /* max number of command args */
 164 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 165
 166 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device */
 167
 168 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 169
 170 #define CFG_MEMTEST_START       0x0400000 /* memtest works on */
 171 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM */
 172
 173 #define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
 174
 175 /* The following table includes the supported baudrates */
 176 #define CFG_BAUDRATE_TABLE      \
 177         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
 178          57600, 115200, 230400, 460800, 921600 }
 179
 180 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 181 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 182
 183 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 184
 185 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 186
 187 /* Only interrupt boot if space is pressed */
 188 /* If a long serial cable is connected but */
 189 /* other end is dead, garbage will be read */
 190 #define CONFIG_AUTOBOOT_KEYED   1
 191 #define CONFIG_AUTOBOOT_PROMPT  "Press SPACE to abort autoboot in %d seconds\n"
 192 #undef CONFIG_AUTOBOOT_DELAY_STR
 193 #define CONFIG_AUTOBOOT_STOP_STR " "
 194
 195 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 196
 197 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 198
 199 /*
 200  * PCI stuff
 201  */
 202 #define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
 203 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 204 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 205
 206 #define CONFIG_PCI                      /* include pci support          */
 207 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 208 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 209                                         /* resource configuration       */
 210
 211 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 212 #define CONFIG_PCI_SKIP_HOST_BRIDGE 1
 213 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 214 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 215 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 216 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 217 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 218 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 219 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 220 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 221 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 222
 223 /*
 224  * IDE/ATA stuff
 225  */
 226 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 227 #undef  CONFIG_IDE_LED                  /* no led for ide supported */
 228 #define CONFIG_IDE_RESET        1       /* reset for ide supported */
 229
 230 #define CFG_IDE_MAXBUS          1               /* max. 1 IDE busses */
 231 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS) /* max. 1 drives per IDE bus */
 232
 233 #define CFG_ATA_BASE_ADDR       0xF0100000
 234 #define CFG_ATA_IDE0_OFFSET     0x0000
 235
 236 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O */
 237 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register access */
 238 #define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers */
 239
 240 /*
 241  * Start addresses for the final memory configuration
 242  * (Set up by the startup code)
 243  * Please note that CFG_SDRAM_BASE _must_ start at 0
 244  */
 245 #define CFG_SDRAM_BASE          0x00000000
 246 #define CFG_MONITOR_BASE        0xFFF80000
 247 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor */
 248 #define CFG_MALLOC_LEN          (2*1024*1024)   /* Reserve 2MB for malloc() */
 249
 250 /*
 251  * For booting Linux, the board info and command line data
 252  * have to be in the first 8 MB of memory, since this is
 253  * the maximum mapped by the Linux kernel during initialization.
 254  */
 255 #define CFG_BOOTMAPSZ           (8 << 20)       /* Init. Memory map for Linux */
 256
 257 /*
 258  * FLASH organization
 259  */
 260 #ifndef __ASSEMBLY__
 261 extern int flash_banks;
 262 #endif
 263
 264 #define CFG_FLASH_BASE          0xFE000000
 265 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 266 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 267 #define CFG_MAX_FLASH_SECT      256     /* max num of sects on one chip */
 268 #define CFG_MAX_FLASH_BANKS     flash_banks /* max num of flash banks */
 269                                             /* updated in board_early_init_r */
 270 #define CFG_MAX_FLASH_BANKS_DETECT 2
 271 #define CFG_FLASH_QUIET_TEST    1
 272 #define CFG_FLASH_INCREMENT     0x01000000
 273 #define CFG_FLASH_PROTECTION    1       /* use hardware protection */
 274 #define CFG_FLASH_AUTOPROTECT_LIST { \
 275                                 {0xfe000000, 0x500000}, \
 276                                 {0xffe80000, 0x180000} \
 277                                 }
 278 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
 279 #define CFG_FLASH_BANKS_LIST    { \
 280                                 CFG_FLASH_BASE, \
 281                                 CFG_FLASH_BASE + CFG_FLASH_INCREMENT \
 282                                 }
 283 #define CFG_FLASH_EMPTY_INFO    /* print 'E' for empty sector on flinfo */
 284
 285 /*
 286  * Environment Variable setup
 287  */
 288 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 289 #define CFG_ENV_OFFSET          0x000   /* environment starts at the */
 290                                         /* beginning of the EEPROM */
 291 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
 292 #define CONFIG_ENV_OVERWRITE    1       /* allow overwriting vendor vars */
 293
 294 #define CFG_NVRAM_BASE_ADDR     0xF0000500      /* NVRAM base address */
 295 #define CFG_NVRAM_SIZE          242             /* NVRAM size */
 296
 297 /*
 298  * I2C EEPROM (CAT24WC16) for environment
 299  */
 300 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 301 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address */
 302 #define CFG_I2C_SLAVE           0x7F
 303
 304 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08 */
 305 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address */
 306 /* mask of address bits that overflow into the "EEPROM chip address" */
 307 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 308 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has */
 309                                         /* 16 byte page write mode using*/
 310                                         /* last 4 bits of the address */
 311 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10 /* and takes up to 10 msec */
 312 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 313
 314 /*
 315  * External Bus Controller (EBC) Setup
 316  */
 317 #define FLASH0_BA       (CFG_FLASH_BASE + CFG_FLASH_INCREMENT) /* FLASH 0 BA */
 318 #define FLASH1_BA       CFG_FLASH_BASE      /* FLASH 1 Base Address          */
 319 #define CAN_BA          0xF0000000          /* CAN Base Address              */
 320 #define DUART0_BA       0xF0000400          /* DUART Base Address            */
 321 #define DUART1_BA       0xF0000408          /* DUART Base Address            */
 322 #define RTC_BA          0xF0000500          /* RTC Base Address              */
 323 #define PS2_BA          0xF0000600          /* PS/2 Base Address             */
 324 #define CF_BA           0xF0100000          /* CompactFlash Base Address     */
 325 #define FPGA_BA         0xF0100100          /* FPGA internal Base Address    */
 326 #define FUJI_BA         0xF0100200          /* Fuji internal Base Address    */
 327 #define PCMCIA1_BA      0x20000000          /* PCMCIA Slot 1 Base Address    */
 328 #define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address    */
 329 #define VGA_BA          0xF1000000          /* Epson VGA Base Address        */
 330
 331 #define CFG_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address    */
 332
 333 /* Memory Bank 0 (Flash Bank 0) initialization                               */
 334 #define CFG_EBC_PB0AP   0x92015480
 335 #define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
 336 #define CFG_EBC_PB0AP_HWREV8 CFG_EBC_PB0AP
 337 #define CFG_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
 338
 339 /* Memory Bank 1 (Flash Bank 1) initialization                               */
 340 #define CFG_EBC_PB1AP   0x92015480
 341 #define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 342
 343 /* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
 344 #define CFG_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 345 #define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 346
 347 /* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
 348 #define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 349 #define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 350
 351 /* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
 352 #define CFG_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 353 #define CFG_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
 354
 355 /* Memory Bank 5 (Epson VGA) initialization                                     */
 356 #define CFG_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
 357 #define CFG_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
 358
 359 /* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
 360 #define CFG_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 361 #define CFG_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
 362
 363 /*
 364  * FPGA stuff
 365  */
 366
 367 /* FPGA internal regs */
 368 #define CFG_FPGA_CTRL           0x008
 369 #define CFG_FPGA_CTRL2          0x00a
 370
 371 /* FPGA Control Reg */
 372 #define CFG_FPGA_CTRL_CF_RESET  0x0001
 373 #define CFG_FPGA_CTRL_WDI       0x0002
 374 #define CFG_FPGA_CTRL_PS2_RESET 0x0020
 375
 376 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 377 #define CFG_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
 378
 379 /* FPGA program pin configuration */
 380 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 381 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 382 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 383 #define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 384 #define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 385
 386 /*
 387  * LCD Setup
 388  */
 389 #define CFG_LCD_BIG_MEM         (VGA_BA + 0x200000) /* S1D13806 Mem Base */
 390 #define CFG_LCD_BIG_REG         VGA_BA /* S1D13806 Reg Base */
 391
 392 #define CONFIG_LCD_BIG          2 /* Epson S1D13806 used */
 393
 394 /* Image information... */
 395 #define CONFIG_LCD_USED         CONFIG_LCD_BIG
 396
 397 #define CFG_LCD_MEM             CFG_LCD_BIG_MEM
 398 #define CFG_LCD_REG             CFG_LCD_BIG_REG
 399
 400 #define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
 401
 402 /*
 403  * Definitions for initial stack pointer and data area (in data cache)
 404  */
 405
 406 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 407 #define CFG_TEMP_STACK_OCM      1
 408
 409 /* On Chip Memory location */
 410 #define CFG_OCM_DATA_ADDR       0xF8000000
 411 #define CFG_OCM_DATA_SIZE       0x1000
 412
 413 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM */
 414 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM */
 415 #define CFG_GBL_DATA_SIZE       128 /* reserved bytes for initial data */
 416 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 417 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 418
 419 /*
 420  * Internal Definitions
 421  *
 422  * Boot Flags
 423  */
 424 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 425 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 426
 427 /*
 428  * PCI OHCI controller
 429  */
 430 #define CONFIG_USB_OHCI_NEW     1
 431 #define CONFIG_PCI_OHCI         1
 432 #define CFG_OHCI_SWAP_REG_ACCESS 1
 433 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 434 #define CFG_USB_OHCI_SLOT_NAME  "ohci_pci"
 435 #define CONFIG_USB_STORAGE      1
 436 #define CFG_USB_OHCI_BOARD_INIT 1
 437
 438 #endif /* __CONFIG_H */