include/configs/AR405.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405GP CPU       */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_AR405            1       /* ...on a AR405 board          */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27
  28 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  29
  30 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  31
  32 #define CONFIG_BAUDRATE         9600
  33 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  34
  35 #if 1
  36 #define CONFIG_BOOTCOMMAND      "bootm fff00000" /* autoboot command    */
  37 #else
  38 #define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  39 #endif
  40
  41 #if 0
  42 #define CONFIG_BOOTARGS         "root=/dev/nfs "                        \
  43     "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "        \
  44     "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
  45 #else
  46 #define CONFIG_BOOTARGS         "root=/dev/hda1 "                       \
  47     "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
  48
  49 #endif
  50
  51 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  52
  53 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  54 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  55
  56 #define CONFIG_PPC4xx_EMAC
  57 #define CONFIG_MII              1       /* MII PHY management           */
  58 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  59 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  60
  61
  62 /*
  63  * BOOTP options
  64  */
  65 #define CONFIG_BOOTP_BOOTFILESIZE
  66 #define CONFIG_BOOTP_BOOTPATH
  67 #define CONFIG_BOOTP_GATEWAY
  68 #define CONFIG_BOOTP_HOSTNAME
  69
  70
  71 /*
  72  * Command line configuration.
  73  */
  74 #include <config_cmd_default.h>
  75
  76 #define CONFIG_CMD_DHCP
  77 #define CONFIG_CMD_PCI
  78 #define CONFIG_CMD_IRQ
  79 #define CONFIG_CMD_ELF
  80 #define CONFIG_CMD_MII
  81 #undef CONFIG_CMD_NFS
  82 #define CONFIG_CMD_PING
  83 #define CONFIG_CMD_BSP
  84
  85
  86 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  87
  88 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  89
  90 /*
  91  * Miscellaneous configurable options
  92  */
  93 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  94 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  95 #if defined(CONFIG_CMD_KGDB)
  96 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  97 #else
  98 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  99 #endif
 100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 101 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 102 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 103
 104 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 105
 106 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 107
 108 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 109 #define CONFIG_LOOPW            1       /* enable loopw command         */
 110 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 111
 112 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 113 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 114
 115 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 116 #define CONFIG_SYS_NS16550
 117 #define CONFIG_SYS_NS16550_SERIAL
 118 #define CONFIG_SYS_NS16550_REG_SIZE     1
 119 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 120
 121 #define CONFIG_SYS_EXT_SERIAL_CLOCK     14745600 /* use external serial clock   */
 122
 123 /* The following table includes the supported baudrates */
 124 #define CONFIG_SYS_BAUDRATE_TABLE       \
 125         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 126          57600, 115200, 230400, 460800, 921600 }
 127
 128 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 129 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 130
 131 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 132
 133 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 134
 135 /*-----------------------------------------------------------------------
 136  * PCI stuff
 137  *-----------------------------------------------------------------------
 138  */
 139 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 140 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 141 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 142
 143 #define CONFIG_PCI                      /* include pci support          */
 144 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 145 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 146 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 147                                         /* resource configuration       */
 148
 149 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 150
 151 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 152
 153 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 154
 155 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 156 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403   /* PCI Device ID: ARISTO405     */
 157 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 158 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 159 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 160 #define CONFIG_SYS_PCI_PTM2LA   0xfff00000      /* point to flash               */
 161 #define CONFIG_SYS_PCI_PTM2MS   0xfff00001      /* 1MB, enable                  */
 162 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 163
 164 /*-----------------------------------------------------------------------
 165  * Start addresses for the final memory configuration
 166  * (Set up by the startup code)
 167  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 168  */
 169 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 170 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 171 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 172 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 173 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 174
 175 /*
 176  * For booting Linux, the board info and command line data
 177  * have to be in the first 8 MB of memory, since this is
 178  * the maximum mapped by the Linux kernel during initialization.
 179  */
 180 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 181 /*-----------------------------------------------------------------------
 182  * FLASH organization
 183  */
 184 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 185 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 186
 187 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 188 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 189
 190 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 191 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 192 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 193 /*
 194  * The following defines are added for buggy IOP480 byte interface.
 195  * All other boards should use the standard values (CPCI405 etc.)
 196  */
 197 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 198 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 199 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 200
 201 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 202
 203 #define CONFIG_ENV_IS_IN_FLASH  1
 204 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 205 #define CONFIG_ENV_SECT_SIZE    0x10000 /* see README - env sector total size   */
 206 #define CONFIG_ENV_SIZE         0x04000         /* Size of Environment          */
 207
 208 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 209 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 210
 211 /*
 212  * Init Memory Controller:
 213  *
 214  * BR0/1 and OR0/1 (FLASH)
 215  */
 216
 217 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 218
 219 /*-----------------------------------------------------------------------
 220  * External Bus Controller (EBC) Setup
 221  */
 222
 223 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 224 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 225 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 226
 227 /* Memory Bank 1 (CAN0, 1, 2, 3) initialization                                 */
 228 #define CONFIG_SYS_EBC_PB1AP            0x01000380  /* enable Ready, BEM=0              */
 229 #define CONFIG_SYS_EBC_PB1CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 230
 231 /* Memory Bank 2 (Expension Bus) initialization                                 */
 232 #define CONFIG_SYS_EBC_PB2AP            0x01000280  /* disable Ready, BEM=0             */
 233 #define CONFIG_SYS_EBC_PB2CR            0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
 234
 235 /* Memory Bank 3 (16552) initialization                                         */
 236 #define CONFIG_SYS_EBC_PB3AP            0x01000380  /* enable Ready, BEM=0              */
 237 #define CONFIG_SYS_EBC_PB3CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 238
 239 /* Memory Bank 4 (FPGA regs) initialization                                     */
 240 #define CONFIG_SYS_EBC_PB4AP            0x01005380  /* enable Ready, BEM=0              */
 241 #define CONFIG_SYS_EBC_PB4CR            0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
 242
 243 /* Memory Bank 5 (Flash Bank 1/DUMMY) initialization                            */
 244 #define CONFIG_SYS_EBC_PB5AP            0x92015480
 245 #define CONFIG_SYS_EBC_PB5CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 246
 247 /*-----------------------------------------------------------------------
 248  * Definitions for initial stack pointer and data area (in data cache)
 249  */
 250 #define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 251
 252 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 253 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 254 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 255 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 256
 257 #endif  /* __CONFIG_H */