include/configs/AR405.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405GP CPU       */
  21 #define CONFIG_AR405            1       /* ...on a AR405 board          */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  24
  25 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  26
  27 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  28
  29 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  30
  31 #define CONFIG_BAUDRATE         9600
  32 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  33
  34 #if 1
  35 #define CONFIG_BOOTCOMMAND      "bootm fff00000" /* autoboot command    */
  36 #else
  37 #define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  38 #endif
  39
  40 #if 0
  41 #define CONFIG_BOOTARGS         "root=/dev/nfs "                        \
  42     "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "        \
  43     "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
  44 #else
  45 #define CONFIG_BOOTARGS         "root=/dev/hda1 "                       \
  46     "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
  47
  48 #endif
  49
  50 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  51
  52 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  53 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  54
  55 #define CONFIG_PPC4xx_EMAC
  56 #define CONFIG_MII              1       /* MII PHY management           */
  57 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  58 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  59
  60
  61 /*
  62  * BOOTP options
  63  */
  64 #define CONFIG_BOOTP_BOOTFILESIZE
  65 #define CONFIG_BOOTP_BOOTPATH
  66 #define CONFIG_BOOTP_GATEWAY
  67 #define CONFIG_BOOTP_HOSTNAME
  68
  69
  70 /*
  71  * Command line configuration.
  72  */
  73 #include <config_cmd_default.h>
  74
  75 #define CONFIG_CMD_DHCP
  76 #define CONFIG_CMD_PCI
  77 #define CONFIG_CMD_IRQ
  78 #define CONFIG_CMD_ELF
  79 #define CONFIG_CMD_MII
  80 #undef CONFIG_CMD_NFS
  81 #define CONFIG_CMD_PING
  82 #define CONFIG_CMD_BSP
  83
  84
  85 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  86
  87 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  93 #if defined(CONFIG_CMD_KGDB)
  94 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  95 #else
  96 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  97 #endif
  98 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  99 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 100 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 101
 102 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 103
 104 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 105
 106 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 107 #define CONFIG_LOOPW            1       /* enable loopw command         */
 108 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 109
 110 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 111 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 112
 113 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 114 #define CONFIG_SYS_NS16550
 115 #define CONFIG_SYS_NS16550_SERIAL
 116 #define CONFIG_SYS_NS16550_REG_SIZE     1
 117 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 118
 119 #define CONFIG_SYS_EXT_SERIAL_CLOCK     14745600 /* use external serial clock   */
 120
 121 /* The following table includes the supported baudrates */
 122 #define CONFIG_SYS_BAUDRATE_TABLE       \
 123         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 124          57600, 115200, 230400, 460800, 921600 }
 125
 126 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 127 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 128
 129 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 130
 131 /*-----------------------------------------------------------------------
 132  * PCI stuff
 133  *-----------------------------------------------------------------------
 134  */
 135 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 136 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 137 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 138
 139 #define CONFIG_PCI                      /* include pci support          */
 140 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 141 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 142 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 143                                         /* resource configuration       */
 144
 145 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 146
 147 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 148
 149 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 150
 151 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 152 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403   /* PCI Device ID: ARISTO405     */
 153 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 154 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 155 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 156 #define CONFIG_SYS_PCI_PTM2LA   0xfff00000      /* point to flash               */
 157 #define CONFIG_SYS_PCI_PTM2MS   0xfff00001      /* 1MB, enable                  */
 158 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 159
 160 /*-----------------------------------------------------------------------
 161  * Start addresses for the final memory configuration
 162  * (Set up by the startup code)
 163  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 164  */
 165 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 166 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 167 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 168 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 169 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 170
 171 /*
 172  * For booting Linux, the board info and command line data
 173  * have to be in the first 8 MB of memory, since this is
 174  * the maximum mapped by the Linux kernel during initialization.
 175  */
 176 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 177 /*-----------------------------------------------------------------------
 178  * FLASH organization
 179  */
 180 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 181 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 182
 183 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 184 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 185
 186 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 187 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 188 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 189 /*
 190  * The following defines are added for buggy IOP480 byte interface.
 191  * All other boards should use the standard values (CPCI405 etc.)
 192  */
 193 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 194 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 195 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 196
 197 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 198
 199 #define CONFIG_ENV_IS_IN_FLASH  1
 200 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 201 #define CONFIG_ENV_SECT_SIZE    0x10000 /* see README - env sector total size   */
 202 #define CONFIG_ENV_SIZE         0x04000         /* Size of Environment          */
 203
 204 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 205 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 206
 207 /*
 208  * Init Memory Controller:
 209  *
 210  * BR0/1 and OR0/1 (FLASH)
 211  */
 212
 213 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 214
 215 /*-----------------------------------------------------------------------
 216  * External Bus Controller (EBC) Setup
 217  */
 218
 219 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 220 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 221 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 222
 223 /* Memory Bank 1 (CAN0, 1, 2, 3) initialization                                 */
 224 #define CONFIG_SYS_EBC_PB1AP            0x01000380  /* enable Ready, BEM=0              */
 225 #define CONFIG_SYS_EBC_PB1CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 226
 227 /* Memory Bank 2 (Expension Bus) initialization                                 */
 228 #define CONFIG_SYS_EBC_PB2AP            0x01000280  /* disable Ready, BEM=0             */
 229 #define CONFIG_SYS_EBC_PB2CR            0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
 230
 231 /* Memory Bank 3 (16552) initialization                                         */
 232 #define CONFIG_SYS_EBC_PB3AP            0x01000380  /* enable Ready, BEM=0              */
 233 #define CONFIG_SYS_EBC_PB3CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 234
 235 /* Memory Bank 4 (FPGA regs) initialization                                     */
 236 #define CONFIG_SYS_EBC_PB4AP            0x01005380  /* enable Ready, BEM=0              */
 237 #define CONFIG_SYS_EBC_PB4CR            0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
 238
 239 /* Memory Bank 5 (Flash Bank 1/DUMMY) initialization                            */
 240 #define CONFIG_SYS_EBC_PB5AP            0x92015480
 241 #define CONFIG_SYS_EBC_PB5CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 242
 243 /*-----------------------------------------------------------------------
 244  * Definitions for initial stack pointer and data area (in data cache)
 245  */
 246 #define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 247
 248 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 249 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 250 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 251 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 252
 253 #endif  /* __CONFIG_H */