include/configs/ASH405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_ASH405           1       /* ...on a ASH405 board         */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  24
  25 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  26 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  27
  28 #define CONFIG_SYS_CLK_FREQ     33333300 /* external frequency to pll   */
  29
  30 #define CONFIG_BAUDRATE         9600
  31 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  32
  33 #undef  CONFIG_BOOTARGS
  34 #undef  CONFIG_BOOTCOMMAND
  35
  36 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  37
  38 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  39 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  40
  41 #undef  CONFIG_HAS_ETH1
  42
  43 #define CONFIG_PPC4xx_EMAC
  44 #define CONFIG_MII              1       /* MII PHY management           */
  45 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  46 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  47 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  48
  49 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  50
  51
  52 /*
  53  * BOOTP options
  54  */
  55 #define CONFIG_BOOTP_BOOTFILESIZE
  56 #define CONFIG_BOOTP_BOOTPATH
  57 #define CONFIG_BOOTP_GATEWAY
  58 #define CONFIG_BOOTP_HOSTNAME
  59
  60
  61 /*
  62  * Command line configuration.
  63  */
  64 #include <config_cmd_default.h>
  65
  66 #define CONFIG_CMD_DHCP
  67 #define CONFIG_CMD_IRQ
  68 #define CONFIG_CMD_ELF
  69 #define CONFIG_CMD_NAND
  70 #define CONFIG_CMD_DATE
  71 #define CONFIG_CMD_I2C
  72 #define CONFIG_CMD_MII
  73 #define CONFIG_CMD_PING
  74 #define CONFIG_CMD_EEPROM
  75
  76
  77 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  78
  79 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  80 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000500 /* RTC Base Address         */
  81
  82 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  83
  84 /*
  85  * Miscellaneous configurable options
  86  */
  87 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  88
  89 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  90
  91 #if defined(CONFIG_CMD_KGDB)
  92 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  93 #else
  94 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  95 #endif
  96 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  97 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  98 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  99
 100 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 101
 102 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 103
 104 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 105 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 106
 107 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 108 #define CONFIG_SYS_NS16550
 109 #define CONFIG_SYS_NS16550_SERIAL
 110 #define CONFIG_SYS_NS16550_REG_SIZE     1
 111 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 112
 113 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 114 #define CONFIG_SYS_BASE_BAUD        691200
 115
 116 /* The following table includes the supported baudrates */
 117 #define CONFIG_SYS_BAUDRATE_TABLE       \
 118         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 119          57600, 115200, 230400, 460800, 921600 }
 120
 121 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 122 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 123
 124 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 125
 126 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 127
 128 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 129
 130 /*-----------------------------------------------------------------------
 131  * NAND-FLASH stuff
 132  *-----------------------------------------------------------------------
 133  */
 134 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 135 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 136 #define NAND_BIG_DELAY_US       25
 137
 138 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 139 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 140 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 141 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 142
 143 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I  1       /* ".i" read skips bad blocks   */
 144 #define CONFIG_SYS_NAND_QUIET           1
 145 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 146 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
 147
 148 /*-----------------------------------------------------------------------
 149  * PCI stuff
 150  *-----------------------------------------------------------------------
 151  */
 152 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 153 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 154 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 155
 156 #define CONFIG_PCI                      /* include pci support          */
 157 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 158 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 159 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 160                                         /* resource configuration       */
 161
 162 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 163
 164 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 165 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405   /* PCI Device ID: CPCI-405      */
 166 #define CONFIG_SYS_PCI_CLASSCODE        0x0b20  /* PCI Class Code: Processor/PPC*/
 167 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 168 #define CONFIG_SYS_PCI_PTM1MS   0xfc000001      /* 64MB, enable hard-wired to 1 */
 169 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 170 #define CONFIG_SYS_PCI_PTM2LA   0xffc00000      /* point to flash               */
 171 #define CONFIG_SYS_PCI_PTM2MS   0xffc00001      /* 4MB, enable                  */
 172 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 173
 174 /*-----------------------------------------------------------------------
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 178  */
 179 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 180 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 182 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 183 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
 184
 185 /*
 186  * For booting Linux, the board info and command line data
 187  * have to be in the first 8 MB of memory, since this is
 188  * the maximum mapped by the Linux kernel during initialization.
 189  */
 190 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 191 /*-----------------------------------------------------------------------
 192  * FLASH organization
 193  */
 194 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 195 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 196
 197 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 198 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 199
 200 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 201 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 202 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 203 /*
 204  * The following defines are added for buggy IOP480 byte interface.
 205  * All other boards should use the standard values (CPCI405 etc.)
 206  */
 207 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 208 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 209 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 210
 211 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 212
 213 #if 0 /* test-only */
 214 #define CONFIG_SYS_JFFS2_FIRST_BANK     0           /* use for JFFS2 */
 215 #define CONFIG_SYS_JFFS2_NUM_BANKS      1           /* ! second bank contains U-Boot */
 216 #endif
 217
 218 /*-----------------------------------------------------------------------
 219  * Environment Variable setup
 220  */
 221 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 222 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 223 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 224                                    /* total size of a CAT24WC16 is 2048 bytes */
 225
 226 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 227 #define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 228
 229 /*-----------------------------------------------------------------------
 230  * I2C EEPROM (CAT24WC16) for environment
 231  */
 232 #define CONFIG_SYS_I2C
 233 #define CONFIG_SYS_I2C_PPC4XX
 234 #define CONFIG_SYS_I2C_PPC4XX_CH0
 235 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 236 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 237
 238 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 239 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 240 /* mask of address bits that overflow into the "EEPROM chip address"    */
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 243                                         /* 16 byte page write mode using*/
 244                                         /* last 4 bits of the address   */
 245 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 246
 247 /*
 248  * Init Memory Controller:
 249  *
 250  * BR0/1 and OR0/1 (FLASH)
 251  */
 252
 253 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 254
 255 /*-----------------------------------------------------------------------
 256  * External Bus Controller (EBC) Setup
 257  */
 258
 259 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 260 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 261 /*#define CONFIG_SYS_EBC_PB0AP            0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 262 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 263
 264 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 265 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 266 #define CONFIG_SYS_EBC_PB1CR            0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 267
 268 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 269 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 270 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 271
 272 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
 273 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 274 #define CONFIG_SYS_EBC_PB3CR            0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 275
 276 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 277 #define DUART0_BA       0xF0000400          /* DUART Base Address               */
 278 #define DUART1_BA       0xF0000408          /* DUART Base Address               */
 279 #define DUART2_BA       0xF0000410          /* DUART Base Address               */
 280 #define DUART3_BA       0xF0000418          /* DUART Base Address               */
 281 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 282 #define CONFIG_SYS_NAND_BASE    0xF4000000
 283
 284 /*-----------------------------------------------------------------------
 285  * FPGA stuff
 286  */
 287 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 288 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024    /* 128kByte is enough for XC2S50E*/
 289
 290 /* FPGA program pin configuration */
 291 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 292 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 293 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 294 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* FPGA init pin (ppc input)     */
 295 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* FPGA done pin (ppc input)     */
 296
 297 /*-----------------------------------------------------------------------
 298  * Definitions for initial stack pointer and data area (in data cache)
 299  */
 300 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 301 #define CONFIG_SYS_TEMP_STACK_OCM         1
 302
 303 /* On Chip Memory location */
 304 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 305 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 306 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 307 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 308
 309 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 310 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 311
 312 /*-----------------------------------------------------------------------
 313  * Definitions for GPIO setup (PPC405EP specific)
 314  *
 315  * GPIO0[0]     - External Bus Controller BLAST output
 316  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 317  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 318  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 319  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 320  * GPIO0[24-27] - UART0 control signal inputs/outputs
 321  * GPIO0[28-29] - UART1 data signal input/output
 322  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 323  */
 324 #define CONFIG_SYS_GPIO0_OSRL           0x40000550
 325 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 326 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 327 #define CONFIG_SYS_GPIO0_ISR1H          0x15555445
 328 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 329 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 330 #define CONFIG_SYS_GPIO0_TCR            0xF7FE0014
 331
 332 #define CONFIG_SYS_DUART_RST            (0x80000000 >> 14)
 333
 334 /*
 335  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 336  * This value will be set if iic boot eprom is disabled.
 337  */
 338 #if 0
 339 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 340 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 341 #endif
 342 #if 1
 343 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 344 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 345 #endif
 346 #if 0
 347 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 348 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 349 #endif
 350
 351 #endif  /* __CONFIG_H */