include/configs/ATUM8548.h

   1 /*
   2  * Copyright 2007
   3  * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
   4  *
   5  * Copyright 2004, 2007 Freescale Semiconductor.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * atum8548 board configuration file
  28  *
  29  * Please refer to doc/README.atum8548 for more info.
  30  *
  31  */
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* Debug Options, Disable in production
  36 #define ET_DEBUG                1
  37 #define CONFIG_PANIC_HANG       1
  38 #define DEBUG                   1
  39 */
  40
  41 /* CPLD Configuration Options */
  42 #define MPC85xx_ATUM_CLKOCR            0x80000002
  43
  44 /* High Level Configuration Options */
  45 #define CONFIG_BOOKE            1       /* BOOKE */
  46 #define CONFIG_E500             1       /* BOOKE e500 family */
  47 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  48 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  49
  50 #define CONFIG_PCI              1       /* enable any pci type devices */
  51 #define CONFIG_PCI1             1       /* PCI controller 1 */
  52 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  53 #define CONFIG_PCI2             1       /* PCI controller 2 */
  54 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  55
  56 #define CONFIG_TSEC_ENET        1       /* tsec ethernet support */
  57 #define CONFIG_ENV_OVERWRITE
  58
  59 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  60
  61 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  62
  63 #define CONFIG_SYS_CLK_FREQ     33000000
  64
  65 /*
  66  * These can be toggled for performance analysis, otherwise use default.
  67  */
  68 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  69 #define CONFIG_BTB                      /* toggle branch predition */
  70 #define CONFIG_CLEAR_LAW0               /* Clear LAW0 in cpu_init_r */
  71
  72 /*
  73  * Only possible on E500 Version 2 or newer cores.
  74  */
  75 #define CONFIG_ENABLE_36BIT_PHYS        1
  76
  77 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  78
  79 #define CONFIG_CMD_SDRAM                1       /* SDRAM DIMM SPD info printout */
  80 #define CONFIG_ENABLE_36BIT_PHYS        1
  81 #undef  CONFIG_SYS_DRAM_TEST
  82 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  83 #define CONFIG_SYS_MEMTEST_END          0x00400000
  84
  85 /*
  86  * Base addresses -- Note these are effective addresses where the
  87  * actual resources get mapped (not physical addresses)
  88  */
  89 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  90 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  91 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  92 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  93
  94 #define PCI_SPEED               33333000        /* CPLD currenlty does not have PCI setup info */
  95 #define CONFIG_SYS_PCI1_ADDR    (CONFIG_SYS_CCSRBAR+0x8000)
  96 #define CONFIG_SYS_PCI2_ADDR    (CONFIG_SYS_CCSRBAR+0x9000)
  97 #define CONFIG_SYS_PCIE1_ADDR   (CONFIG_SYS_CCSRBAR+0xa000)
  98
  99 /* DDR Setup */
 100 #define CONFIG_FSL_DDR2
 101 #undef CONFIG_FSL_DDR_INTERACTIVE
 102 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
 103 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 104 #define CONFIG_DDR_SPD
 105
 106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 107 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 108
 109 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 110 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 111 #define CONFIG_VERY_BIG_RAM
 112
 113 #define CONFIG_NUM_DDR_CONTROLLERS      1
 114 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 115 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 116
 117 /* I2C addresses of SPD EEPROMs */
 118 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 119
 120 /* Manually set up DDR parameters */
 121 #define CONFIG_SYS_SDRAM_SIZE   1024            /* DDR is 1024MB */
 122 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f      /* 0-1024 */
 123 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000102
 124 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 125 #define CONFIG_SYS_DDR_TIMING_1 0x38355322
 126 #define CONFIG_SYS_DDR_TIMING_2 0x039048c7
 127 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 128 #define CONFIG_SYS_DDR_MODE     0x00000432
 129 #define CONFIG_SYS_DDR_INTERVAL 0x05150100
 130 #define DDR_SDRAM_CFG   0x43000000
 131
 132 #undef CONFIG_CLOCKS_IN_MHZ
 133
 134 /*
 135  * Local Bus Definitions
 136  */
 137
 138 /*
 139  * FLASH on the Local Bus
 140  * based on flash chip S29GL01GP
 141  * One bank, 128M, using the CFI driver.
 142  * Boot from BR0 bank at 0xf800_0000
 143  *
 144  * BR0:
 145  *    Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
 146  *    Port Size = 16 bits = BRx[19:20] = 10
 147  *    Use GPCM = BRx[24:26] = 000
 148  *    Valid = BRx[31] = 1
 149  *
 150  * 0    4    8    12   16   20   24   28
 151  * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001    BR0
 152  *
 153  * OR0:
 154  *    Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
 155  *    Reserved ORx[17:18] = 00
 156  *    CSNT = ORx[20] = 1
 157  *    ACS = half cycle delay = ORx[21:22] = 11
 158  *    SCY = 6 = ORx[24:27] = 0110
 159  *    TRLX = use relaxed timing = ORx[29] = 1
 160  *    EAD = use external address latch delay = OR[31] = 1
 161  *
 162  * 0    4    8    12   16   20   24   28
 163  * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65    ORx
 164  */
 165
 166 #define CONFIG_SYS_BOOT_BLOCK           0xf8000000      /* boot TLB block */
 167 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK   /* start of FLASH 128M */
 168
 169 #define CONFIG_SYS_BR0_PRELIM           0xf8001001
 170
 171 #define CONFIG_SYS_OR0_PRELIM           0xf8000E65
 172
 173 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks      */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 175 #undef  CONFIG_SYS_FLASH_CHECKSUM
 176 #define CONFIG_SYS_FLASH_ERASE_TOUT     512000  /* Flash Erase Timeout (ms) */
 177 #define CONFIG_SYS_FLASH_WRITE_TOUT     8000    /* Flash Write Timeout (ms) */
 178
 179
 180 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 181
 182 #define CONFIG_FLASH_CFI_DRIVER    1
 183 #define CONFIG_SYS_FLASH_CFI           1
 184 #define CONFIG_SYS_FLASH_EMPTY_INFO
 185
 186 /*
 187  * Flash on the LocalBus
 188  */
 189 #define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable    */
 190
 191 /* Memory */
 192 #define CONFIG_SYS_INIT_RAM_LOCK        1
 193 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 194 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 195
 196 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 197
 198 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 199 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 200 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 201
 202 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 203 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 204
 205 /* Serial Port */
 206 #define CONFIG_CONS_INDEX       1
 207 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 208 #define CONFIG_SYS_NS16550
 209 #define CONFIG_SYS_NS16550_SERIAL
 210 #define CONFIG_SYS_NS16550_REG_SIZE     1
 211 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 212
 213 #define CONFIG_SYS_BAUDRATE_TABLE \
 214         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 215
 216 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 217 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 218
 219 /* Use the HUSH parser */
 220 #define CONFIG_SYS_HUSH_PARSER
 221 #ifdef  CONFIG_SYS_HUSH_PARSER
 222 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 223 #endif
 224
 225 /* pass open firmware flat tree */
 226 #define CONFIG_OF_LIBFDT                1
 227 #define CONFIG_OF_BOARD_SETUP           1
 228
 229 /*
 230  * I2C
 231  */
 232 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 233 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 234 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 235 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 236 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 237 #define CONFIG_SYS_I2C_SLAVE            0x7F
 238 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 239 #define CONFIG_SYS_I2C_OFFSET           0x3000
 240
 241 /*
 242  * General PCI
 243  * Memory space is mapped 1-1, but I/O space must start from 0.
 244  */
 245 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 246
 247 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 248 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 249 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 250 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 251 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 252 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 253
 254 #ifdef CONFIG_PCI2
 255 #define CONFIG_SYS_PCI2_MEM_BASE        0xC0000000
 256 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 257 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 258 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 259 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
 260 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 261 #endif
 262
 263 #ifdef CONFIG_PCIE1
 264 #define CONFIG_SYS_PCIE1_MEM_BASE       0xa0000000
 265 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 266 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 267 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 268 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 269 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 270 #endif
 271
 272
 273 #if !defined(CONFIG_PCI_PNP)
 274     #define PCI_ENET0_IOADDR    0xe0000000
 275     #define PCI_ENET0_MEMADDR   0xe0000000
 276     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 277 #endif
 278
 279 #if defined(CONFIG_PCI)
 280
 281 #define CONFIG_NET_MULTI
 282 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 283
 284 #undef CONFIG_EEPRO100
 285 #undef CONFIG_TULIP
 286
 287 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 288
 289 #endif  /* CONFIG_PCI */
 290
 291 #if defined(CONFIG_TSEC_ENET)
 292
 293 #ifndef CONFIG_NET_MULTI
 294 #define CONFIG_NET_MULTI        1
 295 #endif
 296
 297 #define CONFIG_MII              1       /* MII PHY management */
 298 #define CONFIG_TSEC1    1
 299 #define CONFIG_TSEC1_NAME       "eTSEC0"
 300 #define CONFIG_TSEC2    1
 301 #define CONFIG_TSEC2_NAME       "eTSEC1"
 302 #define CONFIG_TSEC3    1
 303 #define CONFIG_TSEC3_NAME       "eTSEC2"
 304 #define CONFIG_TSEC4    1
 305 #define CONFIG_TSEC4_NAME       "eTSEC3"
 306 #undef CONFIG_MPC85XX_FEC
 307
 308 #define TSEC1_PHY_ADDR          0
 309 #define TSEC2_PHY_ADDR          1
 310 #define TSEC3_PHY_ADDR          2
 311 #define TSEC4_PHY_ADDR          3
 312
 313 #define TSEC1_PHYIDX            0
 314 #define TSEC2_PHYIDX            0
 315 #define TSEC3_PHYIDX            0
 316 #define TSEC4_PHYIDX            0
 317 #define TSEC1_FLAGS             TSEC_GIGABIT
 318 #define TSEC2_FLAGS             TSEC_GIGABIT
 319 #define TSEC3_FLAGS             TSEC_GIGABIT
 320 #define TSEC4_FLAGS             TSEC_GIGABIT
 321
 322 /* Options are: eTSEC[0-3] */
 323 #define CONFIG_ETHPRIME         "eTSEC2"
 324 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 325 #endif  /* CONFIG_TSEC_ENET */
 326
 327 /*
 328  * Environment
 329  */
 330 #define CONFIG_ENV_IS_IN_FLASH  1
 331 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 332 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 333 #define CONFIG_ENV_SIZE         0x2000
 334
 335 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 336 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 337
 338 /*
 339  * BOOTP options
 340  */
 341 #define CONFIG_BOOTP_BOOTFILESIZE
 342 #define CONFIG_BOOTP_BOOTPATH
 343 #define CONFIG_BOOTP_GATEWAY
 344 #define CONFIG_BOOTP_HOSTNAME
 345
 346
 347 /*
 348  * Command line configuration.
 349  */
 350 #include <config_cmd_default.h>
 351
 352 #define CONFIG_CMD_PING
 353 #define CONFIG_CMD_I2C
 354 #define CONFIG_CMD_MII
 355
 356 #if defined(CONFIG_PCI)
 357     #define CONFIG_CMD_PCI
 358 #endif
 359
 360
 361 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 362
 363 /*
 364  * Miscellaneous configurable options
 365  */
 366 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 367 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 368 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 369 #if defined(CONFIG_CMD_KGDB)
 370 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 371 #else
 372 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 373 #endif
 374 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 375 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 376 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 377 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 378
 379 /*
 380  * For booting Linux, the board info and command line data
 381  * have to be in the first 8 MB of memory, since this is
 382  * the maximum mapped by the Linux kernel during initialization.
 383  */
 384 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 385
 386 /*
 387  * Internal Definitions
 388  *
 389  * Boot Flags
 390  */
 391 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 392 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 393
 394 #if defined(CONFIG_CMD_KGDB)
 395 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 396 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 397 #endif
 398
 399 /*
 400  * Environment Configuration
 401  */
 402
 403 /* The mac addresses for all ethernet interface */
 404 #if defined(CONFIG_TSEC_ENET)
 405 #define CONFIG_HAS_ETH0
 406 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 407 #define CONFIG_HAS_ETH1
 408 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 409 #define CONFIG_HAS_ETH2
 410 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 411 #define CONFIG_HAS_ETH3
 412 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 413 #endif
 414
 415 #define CONFIG_IPADDR    10.101.43.142
 416
 417 #define CONFIG_HOSTNAME  atum
 418 #define CONFIG_ROOTPATH  /nfsroot
 419 #define CONFIG_BOOTFILE  /tftpboot/uImage.atum
 420 #define CONFIG_UBOOTPATH        /tftpboot/uboot.bin     /* TFTP server */
 421
 422 #define CONFIG_SERVERIP  10.101.43.10
 423 #define CONFIG_GATEWAYIP 10.101.45.1
 424 #define CONFIG_NETMASK   255.255.248.0
 425
 426 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 427
 428 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 429 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 430
 431 #define CONFIG_BAUDRATE 115200
 432
 433 #define CONFIG_NFSBOOTCOMMAND                                           \
 434    "setenv bootargs root=/dev/nfs rw "                                  \
 435       "nfsroot=$serverip:$rootpath "                                    \
 436       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 437       "console=$consoledev,$baudrate $othbootargs;"                     \
 438    "tftp $loadaddr $bootfile;"                                          \
 439    "tftp $dtbaddr $dtbfile;"                                            \
 440    "bootm $loadaddr - $dtbaddr"
 441
 442
 443 #define CONFIG_RAMBOOTCOMMAND \
 444    "setenv bootargs root=/dev/ram rw "                                  \
 445       "console=$consoledev,$baudrate $othbootargs;"                     \
 446    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 447    "tftp $loadaddr $bootfile;"                                          \
 448    "tftp $dtbaddr $dtbfile;"                                            \
 449    "bootm $loadaddr $ramdiskaddr $dtbaddr"
 450
 451 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 452
 453 #endif  /* __CONFIG_H */