include/configs/Adder.h

   1 /*
   2  * Copyright (C) 2004-2005 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * Support for Analogue&Micro Adder boards family.
   6  * Tested on AdderII and Adder87x.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
  14 #define CONFIG_MPC875
  15 #endif
  16
  17 #define CONFIG_ADDER                            /* Analogue&Micro Adder board   */
  18
  19 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  20
  21 #define CONFIG_8xx_CONS_SMC1    1               /* Console is on SMC1           */
  22 #define CONFIG_BAUDRATE         38400
  23
  24 #define CONFIG_ETHER_ON_FEC1
  25 #define CONFIG_ETHER_ON_FEC2
  26 #define CONFIG_HAS_ETH0
  27 #define CONFIG_HAS_ETH1
  28
  29 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
  30 #define CONFIG_SYS_DISCOVER_PHY
  31 #define CONFIG_MII_INIT         1
  32 #define FEC_ENET
  33 #endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
  34
  35 #define CONFIG_8xx_OSCLK                10000000 /* 10 MHz oscillator on EXTCLK */
  36 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000
  37 #define CONFIG_SYS_8xx_CPUCLK_MIN               40000000
  38 #ifdef CONFIG_MPC852T
  39 #define CONFIG_SYS_8xx_CPUCLK_MAX               50000000
  40 #else
  41 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000
  42 #endif /* CONFIG_MPC852T */
  43
  44
  45 /*
  46  * BOOTP options
  47  */
  48 #define CONFIG_BOOTP_BOOTFILESIZE
  49 #define CONFIG_BOOTP_BOOTPATH
  50 #define CONFIG_BOOTP_GATEWAY
  51 #define CONFIG_BOOTP_HOSTNAME
  52
  53
  54 /*
  55  * Command line configuration.
  56  */
  57 #include <config_cmd_default.h>
  58
  59 #define CONFIG_CMD_DHCP
  60 #define CONFIG_CMD_IMMAP
  61 #define CONFIG_CMD_MII
  62 #define CONFIG_CMD_PING
  63
  64
  65 #define CONFIG_BOOTDELAY        5               /* Autoboot after 5 seconds     */
  66 #define CONFIG_BOOTCOMMAND      "bootm fe040000"        /* Autoboot command     */
  67 #define CONFIG_BOOTARGS         "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
  68
  69 #define CONFIG_BZIP2            /* Include support for bzip2 compressed images  */
  70 #undef  CONFIG_WATCHDOG         /* Disable platform specific watchdog           */
  71
  72 /*-----------------------------------------------------------------------
  73  * Miscellaneous configurable options
  74  */
  75 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
  76 #define CONFIG_SYS_HUSH_PARSER
  77 #define CONFIG_SYS_LONGHELP                             /* #undef to save memory        */
  78 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  79 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
  80 #define CONFIG_SYS_MAXARGS              16              /* Max number of command args   */
  81 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  82
  83 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* Default load address         */
  84
  85 #define CONFIG_SYS_HZ                   1000            /* Decrementer freq: 1 ms ticks */
  86
  87 /*-----------------------------------------------------------------------
  88  * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
  89  */
  90 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  91 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x01000000      /* Up to 16 Mbyte               */
  92
  93 #define CONFIG_SYS_MAMR         0x00002114
  94
  95 /*
  96  * 4096 Up to 4096 SDRAM rows
  97  * 1000 factor s -> ms
  98  * 32   PTP (pre-divider from MPTPR)
  99  * 4    Number of refresh cycles per period
 100  * 64   Refresh cycle in ms per number of rows
 101  */
 102 #define CONFIG_SYS_PTA_PER_CLK          ((4096 * 32 * 1000) / (4 * 64))
 103
 104 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on             */
 105 #define CONFIG_SYS_MEMTEST_END          0x00500000      /* 1 ... 5 MB in SDRAM          */
 106
 107 #define CONFIG_SYS_RESET_ADDRESS        0x09900000
 108
 109 /*-----------------------------------------------------------------------
 110  * For booting Linux, the board info and command line data
 111  * have to be in the first 8 MB of memory, since this is
 112  * the maximum mapped by the Linux kernel during initialization.
 113  */
 114 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 115
 116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 117 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 KB for Monitor   */
 118 #ifdef CONFIG_BZIP2
 119 #define CONFIG_SYS_MALLOC_LEN           (2500 << 10)    /* Reserve ~2.5 MB for malloc() */
 120 #else
 121 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 KB for malloc()  */
 122 #endif /* CONFIG_BZIP2 */
 123
 124 /*-----------------------------------------------------------------------
 125  * Flash organisation
 126  */
 127 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 128 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 129 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* Max number of flash banks    */
 131 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* Max num of sects on one chip */
 132
 133 /* Environment is in flash */
 134 #define CONFIG_ENV_IS_IN_FLASH
 135 #define CONFIG_ENV_SECT_SIZE    0x10000         /* We use one complete sector   */
 136 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 137
 138 #define CONFIG_ENV_OVERWRITE
 139
 140 #define CONFIG_SYS_OR0_PRELIM           0xFF000774
 141 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
 142
 143 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 144
 145 /*-----------------------------------------------------------------------
 146  * Internal Memory Map Register
 147  */
 148 #define CONFIG_SYS_IMMR         0xFF000000
 149
 150 /*-----------------------------------------------------------------------
 151  * Definitions for initial stack pointer and data area (in DPRAM)
 152  */
 153 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 154 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00          /* Size of used area in DPRAM   */
 155 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 156 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 157
 158 /*-----------------------------------------------------------------------
 159  * Configuration registers
 160  */
 161 #ifdef CONFIG_WATCHDOG
 162 #define CONFIG_SYS_SYPCR                (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 163                                  SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
 164                                  SYPCR_SWP)
 165 #else
 166 #define CONFIG_SYS_SYPCR                (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 167                                  SYPCR_SWF  | SYPCR_SWP)
 168 #endif /* CONFIG_WATCHDOG */
 169
 170 #define CONFIG_SYS_SIUMCR               (SIUMCR_MLRC01 | SIUMCR_DBGC11)
 171
 172 /* TBSCR - Time Base Status and Control Register */
 173 #define CONFIG_SYS_TBSCR                (TBSCR_TBF | TBSCR_TBE)
 174
 175 /* PISCR - Periodic Interrupt Status and Control */
 176 #define CONFIG_SYS_PISCR                (PISCR_PS | PISCR_PITF)
 177
 178 /* PLPRCR - PLL, Low-Power, and Reset Control Register */
 179 /* #define CONFIG_SYS_PLPRCR            PLPRCR_TEXPS */
 180
 181 /* SCCR - System Clock and reset Control Register */
 182 #define SCCR_MASK               SCCR_EBDF11
 183 #define CONFIG_SYS_SCCR         SCCR_RTSEL
 184
 185 #define CONFIG_SYS_DER                  0
 186
 187 /*-----------------------------------------------------------------------
 188  * Cache Configuration
 189  */
 190 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx chips                 */
 191
 192 /* pass open firmware flat tree */
 193 #define CONFIG_OF_LIBFDT        1
 194 #define CONFIG_OF_BOARD_SETUP   1
 195
 196 #endif /* __CONFIG_H */