include/configs/Alaska8220.h

   1 /*
   2  * (C) Copyright 2004
   3  * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31 #define CONFIG_MPC8220          1
  32 #define CONFIG_ALASKA8220       1       /* ... on Alaska board  */
  33
  34 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
  35    determine the CPU speed. */
  36 #define CFG_MPC8220_CLKIN       30000000/* ... running at 30MHz */
  37
  38 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
  39 #define BOOTFLAG_WARM           0x02    /* Software reboot      */
  40
  41 #define CFG_CACHELINE_SIZE      32      /* For MPC8220 CPUs */
  42
  43 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  44 #  define CFG_CACHELINE_SHIFT   5   /* log base 2 of the above value */
  45 #endif
  46
  47 /*
  48  * Serial console configuration
  49  */
  50 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC */
  51 #define CONFIG_EXTUART_CONSOLE  1
  52
  53 #ifdef CONFIG_EXTUART_CONSOLE
  54 #   define CFG_NS16550
  55 #   define CFG_NS16550_REG_SIZE 1
  56 #   define CFG_NS16550_COM1     (CFG_CPLD_BASE + 0x1008)
  57 #endif
  58
  59 #define CONFIG_BAUDRATE         115200      /* ... at 115200 bps */
  60
  61
  62 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  63
  64 /*
  65  * Supported commands
  66  */
  67 /* CONFIG_CMD_DFL includes CFG_CMD_BDI (bdinfo), CFG_CMD_LOADS (loads),
  68    CFG_CMD_LOADB (loadb), CFG_CMD_IMI (iminfo), CFG_CMD_FLASH
  69    (flinfo, erase, protect), CFG_CMD_MEMORY (md, mm, nm, mw, cp, cmp,
  70    crc, base, loop, mtest), CFG_CMD_ENV (printenv, setenv, saveenv),
  71    CFG_CMD_BOOTD (bootd), CFG_CMD_CONSOLE (coninfo), CFG_CMD_NET (bootp,
  72    tftpboot, rarpboot), CFG_CMD_RUN, CFG_CMD_MISC (sleep, etc),
  73    CFG_CMD_BSP, CFG_CMD_IMLS, CFG_CMD_FPGA */
  74
  75 #define CONFIG_COMMANDS     (CONFIG_CMD_DFL  | \
  76                              CFG_CMD_BOOTD   | \
  77                              CFG_CMD_CACHE   | \
  78                              CFG_CMD_DIAG    | \
  79                              CFG_CMD_EEPROM  | \
  80                              CFG_CMD_ELF     | \
  81                              CFG_CMD_I2C     | \
  82                              CFG_CMD_NET     | \
  83                              CFG_CMD_PING    | \
  84                              CFG_CMD_REGINFO | \
  85                              CFG_CMD_SDRAM     \
  86                              )
  87 /*                             CFG_CMD_DHCP    | \ */
  88 /*                             CFG_CMD_MII     | \ */
  89 /*                             CFG_CMD_PCI     | \ */
  90 /*                             CFG_CMD_USB */
  91
  92 #   define CONFIG_NET_MULTI
  93 /*#if (CONFIG_COMMANDS & CFG_CMD_NET)
  94 #   define CONFIG_NET_MULTI
  95 #else
  96 #   undef CONFIG_NET_MULTI
  97 #endif*/
  98
  99
 100 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 101 #include <cmd_confdefs.h>
 102
 103 /*
 104  * Autobooting
 105  */
 106 #define CONFIG_BOOTDELAY        5    /* autoboot after 5 seconds */
 107 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 108 #define CONFIG_ETHADDR          00:e0:0c:bc:e0:60
 109 #define CONFIG_HAS_ETH1
 110 #define CONFIG_ETH1ADDR         00:e0:0c:bc:e0:61
 111 #define CONFIG_IPADDR           192.162.1.2
 112 #define CONFIG_NETMASK          255.255.255.0
 113 #define CONFIG_SERVERIP         192.162.1.1
 114 #define CONFIG_GATEWAYIP        192.162.1.1
 115 #define CONFIG_HOSTNAME         Alaska
 116 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 117
 118
 119 /*
 120  * I2C configuration
 121  */
 122 #define CONFIG_HARD_I2C         1
 123 #define CFG_I2C_MODULE          1
 124
 125 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 126 #define CFG_I2C_SLAVE           0x7F
 127
 128 /*
 129  * EEPROM configuration
 130  */
 131 #define CFG_I2C_EEPROM_ADDR             0x52    /* 1011000xb */
 132 #define CFG_I2C_EEPROM_ADDR_LEN         1
 133 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 134 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 135 /*
 136 #define CFG_ENV_IS_IN_EEPROM    1
 137 #define CFG_ENV_OFFSET          0
 138 #define CFG_ENV_SIZE            256
 139 */
 140
 141 /* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
 142    else undefined it will boot from Intel Strata flash */
 143 #define CFG_AMD_BOOT            1
 144
 145 /*
 146  * Flexbus Chipselect configuration
 147  */
 148 #if defined (CFG_AMD_BOOT)
 149 #define CFG_CS0_BASE            0xfff0
 150 #define CFG_CS0_MASK            0x00080000  /* 512 KB */
 151 #define CFG_CS0_CTRL            0x003f0d40
 152
 153 #define CFG_CS1_BASE            0xfe00
 154 #define CFG_CS1_MASK            0x01000000  /* 16 MB */
 155 #define CFG_CS1_CTRL            0x003f1540
 156 #else
 157 #define CFG_CS0_BASE            0xff00
 158 #define CFG_CS0_MASK            0x01000000  /* 16 MB */
 159 #define CFG_CS0_CTRL            0x003f1540
 160
 161 #define CFG_CS1_BASE            0xfe08
 162 #define CFG_CS1_MASK            0x00080000  /* 512 KB */
 163 #define CFG_CS1_CTRL            0x003f0d40
 164 #endif
 165
 166 #define CFG_CS2_BASE            0xf100
 167 #define CFG_CS2_MASK            0x00040000
 168 #define CFG_CS2_CTRL            0x003f1140
 169
 170 #define CFG_CS3_BASE            0xf200
 171 #define CFG_CS3_MASK            0x00040000
 172 #define CFG_CS3_CTRL            0x003f1100
 173
 174
 175 #define CFG_FLASH0_BASE         (CFG_CS0_BASE << 16)
 176 #define CFG_FLASH1_BASE         (CFG_CS1_BASE << 16)
 177
 178 #if defined (CFG_AMD_BOOT)
 179 #define CFG_AMD_BASE            CFG_FLASH0_BASE
 180 #define CFG_INTEL_BASE          CFG_FLASH1_BASE + 0xf00000
 181 #define CFG_FLASH_BASE          CFG_AMD_BASE
 182 #else
 183 #define CFG_INTEL_BASE          CFG_FLASH0_BASE + 0xf00000
 184 #define CFG_AMD_BASE            CFG_FLASH1_BASE
 185 #define CFG_FLASH_BASE          CFG_INTEL_BASE
 186 #endif
 187
 188 #define CFG_CPLD_BASE           (CFG_CS2_BASE << 16)
 189 #define CFG_FPGA_BASE           (CFG_CS3_BASE << 16)
 190
 191
 192 #define CFG_MAX_FLASH_BANKS     4       /* max num of memory banks      */
 193 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 194
 195 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 196 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 197 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 198 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 199 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 200
 201 #define PHYS_AMD_SECT_SIZE      0x00010000 /*  64 KB sectors (x2) */
 202 #define PHYS_INTEL_SECT_SIZE    0x00020000 /* 128 KB sectors (x2) */
 203
 204 #define CFG_FLASH_CHECKSUM
 205 /*
 206  * Environment settings
 207  */
 208 #define CFG_ENV_IS_IN_FLASH     1
 209 #if defined (CFG_AMD_BOOT)
 210 #define CFG_ENV_ADDR            (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
 211 #define CFG_ENV_SIZE            PHYS_AMD_SECT_SIZE
 212 #define CFG_ENV_SECT_SIZE       PHYS_AMD_SECT_SIZE
 213 #define CFG_ENV1_ADDR           (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
 214 #define CFG_ENV1_SIZE           PHYS_INTEL_SECT_SIZE
 215 #define CFG_ENV1_SECT_SIZE      PHYS_INTEL_SECT_SIZE
 216 #else
 217 #define CFG_ENV_ADDR            (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
 218 #define CFG_ENV_SIZE            PHYS_INTEL_SECT_SIZE
 219 #define CFG_ENV_SECT_SIZE       PHYS_INTEL_SECT_SIZE
 220 #define CFG_ENV1_ADDR           (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
 221 #define CFG_ENV1_SIZE           PHYS_AMD_SECT_SIZE
 222 #define CFG_ENV1_SECT_SIZE      PHYS_AMD_SECT_SIZE
 223 #endif
 224
 225 #define CONFIG_ENV_OVERWRITE    1
 226
 227 #if defined CFG_ENV_IS_IN_FLASH
 228 #undef CFG_ENV_IS_IN_NVRAM
 229 #undef CFG_ENV_IS_IN_EEPROM
 230 #elif defined CFG_ENV_IS_IN_NVRAM
 231 #undef CFG_ENV_IS_IN_FLASH
 232 #undef CFG_ENV_IS_IN_EEPROM
 233 #elif defined CFG_ENV_IS_IN_EEPROM
 234 #undef CFG_ENV_IS_IN_NVRAM
 235 #undef CFG_ENV_IS_IN_FLASH
 236 #endif
 237
 238 #ifndef CFG_JFFS2_FIRST_SECTOR
 239 #define CFG_JFFS2_FIRST_SECTOR  0
 240 #endif
 241 #ifndef CFG_JFFS2_FIRST_BANK
 242 #define CFG_JFFS2_FIRST_BANK    0
 243 #endif
 244 #ifndef CFG_JFFS2_NUM_BANKS
 245 #define CFG_JFFS2_NUM_BANKS     1
 246 #endif
 247 #define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
 248
 249 /*
 250  * Memory map
 251  */
 252 #define CFG_MBAR                0xF0000000
 253 #define CFG_SDRAM_BASE          0x00000000
 254 #define CFG_DEFAULT_MBAR        0x80000000
 255 #define CFG_SRAM_BASE           (CFG_MBAR + 0x20000)
 256 #define CFG_SRAM_SIZE           0x8000
 257
 258 /* Use SRAM until RAM will be available */
 259 #define CFG_INIT_RAM_ADDR       (CFG_MBAR + 0x20000)
 260 #define CFG_INIT_RAM_END        0x8000  /* End of used area in DPRAM */
 261
 262 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 263 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 264 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 265
 266 #define CFG_MONITOR_BASE        TEXT_BASE
 267 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 268 #   define CFG_RAMBOOT          1
 269 #endif
 270
 271 #define CFG_MONITOR_LEN         (256 << 10) /* Reserve 256 kB for Monitor   */
 272 #define CFG_MALLOC_LEN          (128 << 10) /* Reserve 128 kB for malloc()  */
 273 #define CFG_BOOTMAPSZ           (8 << 20)   /* Initial Memory map for Linux */
 274
 275 /*
 276  * Ethernet configuration
 277  */
 278 #define CONFIG_MPC8220_FEC      1
 279 #define CONFIG_FEC_10MBIT       1 /* Workaround for FEC 100Mbit problem */
 280 #define CONFIG_PHY_ADDR         0x18
 281
 282
 283 /*
 284  * Miscellaneous configurable options
 285  */
 286 #define CFG_LONGHELP                        /* undef to save memory     */
 287 #define CFG_PROMPT              "=> "       /* Monitor Command Prompt   */
 288 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 289 #define CFG_CBSIZE              1024        /* Console I/O Buffer Size  */
 290 #else
 291 #define CFG_CBSIZE              256         /* Console I/O Buffer Size  */
 292 #endif
 293 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 294 #define CFG_MAXARGS             16          /* max number of command args   */
 295 #define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
 296
 297 #define CFG_MEMTEST_START       0x00100000  /* memtest works on */
 298 #define CFG_MEMTEST_END         0x00f00000  /* 1 ... 15 MB in DRAM  */
 299
 300 #define CFG_LOAD_ADDR           0x100000    /* default load address */
 301
 302 #define CFG_HZ                  1000        /* decrementer freq: 1 ms ticks */
 303
 304 /*
 305  * Various low-level settings
 306  */
 307 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 308 #define CFG_HID0_FINAL          HID0_ICE
 309
 310 #endif /* __CONFIG_H */