include/configs/BAB7xx.h

   1 /*
   2  * (C) Copyright 2002 ELTEC Elektronik AG
   3  * Frank Gottschling <fgottschling@eltec.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #define GTREGREAD(x) 0xffffffff         /* needed for debug */
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  39
  40 /* these hardware addresses are pretty bogus, please change them to
  41    suit your needs */
  42
  43 /* first ethernet */
  44 #define CONFIG_ETHADDR          00:00:5b:ee:de:ad
  45
  46 #define CONFIG_IPADDR           192.168.0.105
  47 #define CONFIG_SERVERIP         192.168.0.100
  48
  49 #define CONFIG_BAB7xx           1       /* this is an BAB740/BAB750 board */
  50
  51 #define CONFIG_BAUDRATE         9600    /* console baudrate */
  52
  53 #undef  CONFIG_WATCHDOG
  54
  55 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  56
  57 #define CONFIG_ZERO_BOOTDELAY_CHECK
  58
  59 #undef  CONFIG_BOOTARGS
  60 #define CONFIG_BOOTCOMMAND                                  \
  61     "bootp 1000000; "                                       \
  62     "setenv bootargs root=ramfs console=ttyS00,9600 "       \
  63     "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
  64     "${netmask}:${hostname}:eth0:none; "                    \
  65     "bootm"
  66
  67 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  68 #define CONFIG_SYS_LOADS_BAUD_CHANGE           /* allow baudrate changes */
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_SUBNETMASK
  74 #define CONFIG_BOOTP_GATEWAY
  75 #define CONFIG_BOOTP_HOSTNAME
  76 #define CONFIG_BOOTP_BOOTPATH
  77
  78 #define CONFIG_BOOTP_BOOTFILESIZE
  79
  80
  81 /*
  82  * Command line configuration.
  83  */
  84 #include <config_cmd_default.h>
  85
  86 #define CONFIG_CMD_PCI
  87 #define CONFIG_CMD_JFFS2
  88 #define CONFIG_CMD_SCSI
  89 #define CONFIG_CMD_IDE
  90 #define CONFIG_CMD_DATE
  91 #define CONFIG_CMD_FDC
  92 #define CONFIG_CMD_ELF
  93
  94
  95 /*
  96  * Miscellaneous configurable options
  97  */
  98 #define CONFIG_SYS_LONGHELP                    /* undef to save memory */
  99 #define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt */
 100
 101 /*
 102  * choose between COM1 and COM2 as serial console
 103  */
 104 #define CONFIG_CONS_INDEX       1
 105
 106 #if defined(CONFIG_CMD_KGDB)
 107 #define CONFIG_SYS_CBSIZE              1024        /* Console I/O Buffer Size */
 108 #else
 109 #define CONFIG_SYS_CBSIZE              256         /* Console I/O Buffer Size */
 110 #endif
 111 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 112 #define CONFIG_SYS_MAXARGS             16          /* max number of command args    */
 113 #define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 114
 115 #define CONFIG_SYS_MEMTEST_START       0x00000000  /* memtest works on    */
 116 #define CONFIG_SYS_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
 117
 118 #define CONFIG_SYS_LOAD_ADDR           0x1000000   /* default load address    */
 119
 120 #define CONFIG_SYS_HZ                  1000        /* dec. freq: 1 ms ticks */
 121
 122 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 123
 124 /*
 125  * Low Level Configuration Settings
 126  * (address mappings, register initial values, etc.)
 127  * You should know what you are doing if you make changes here.
 128  */
 129 #define CONFIG_SYS_BOARD_ASM_INIT
 130 #define CONFIG_MISC_INIT_R
 131
 132 /*
 133  * Choose the address mapping scheme for the MPC106 mem controller.
 134  * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
 135  */
 136 #define CONFIG_SYS_ADDRESS_MAP_A
 137 #ifdef  CONFIG_SYS_ADDRESS_MAP_A
 138
 139 #define CONFIG_SYS_PCI_MEMORY_BUS      0x80000000
 140 #define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
 141 #define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
 142
 143 #define CONFIG_SYS_PCI_MEM_BUS         0x00000000
 144 #define CONFIG_SYS_PCI_MEM_PHYS        0xc0000000
 145 #define CONFIG_SYS_PCI_MEM_SIZE        0x3f000000
 146
 147 #define CONFIG_SYS_ISA_MEM_BUS         0
 148 #define CONFIG_SYS_ISA_MEM_PHYS        0
 149 #define CONFIG_SYS_ISA_MEM_SIZE        0
 150
 151 #define CONFIG_SYS_PCI_IO_BUS          0x1000
 152 #define CONFIG_SYS_PCI_IO_PHYS         0x81000000
 153 #define CONFIG_SYS_PCI_IO_SIZE         0x01000000-CONFIG_SYS_PCI_IO_BUS
 154
 155 #define CONFIG_SYS_ISA_IO_BUS          0x00000000
 156 #define CONFIG_SYS_ISA_IO_PHYS         0x80000000
 157 #define CONFIG_SYS_ISA_IO_SIZE         0x00800000
 158
 159 #else
 160
 161 #define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
 162 #define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
 163 #define CONFIG_SYS_PCI_MEMORY_SIZE     0x40000000
 164
 165 #define CONFIG_SYS_PCI_MEM_BUS         0x80000000
 166 #define CONFIG_SYS_PCI_MEM_PHYS        0x80000000
 167 #define CONFIG_SYS_PCI_MEM_SIZE        0x7d000000
 168
 169 #define CONFIG_SYS_ISA_MEM_BUS         0x00000000
 170 #define CONFIG_SYS_ISA_MEM_PHYS        0xfd000000
 171 #define CONFIG_SYS_ISA_MEM_SIZE        0x01000000
 172
 173 #define CONFIG_SYS_PCI_IO_BUS          0x00800000
 174 #define CONFIG_SYS_PCI_IO_PHYS         0xfe800000
 175 #define CONFIG_SYS_PCI_IO_SIZE         0x00400000
 176
 177 #define CONFIG_SYS_ISA_IO_BUS          0x00000000
 178 #define CONFIG_SYS_ISA_IO_PHYS         0xfe000000
 179 #define CONFIG_SYS_ISA_IO_SIZE         0x00800000
 180
 181 #endif /*CONFIG_SYS_ADDRESS_MAP_A */
 182
 183 #define CONFIG_SYS_60X_PCI_MEM_OFFSET  0x00000000
 184
 185 /* driver defines FDC,IDE,... */
 186 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
 187 #define CONFIG_SYS_ISA_IO              CONFIG_SYS_ISA_IO_PHYS
 188 #define CONFIG_SYS_60X_PCI_IO_OFFSET   CONFIG_SYS_ISA_IO_PHYS
 189
 190 /*
 191  * Start addresses for the final memory configuration
 192  * (Set up by the startup code)
 193  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 194  */
 195 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 196 #define CONFIG_SYS_FLASH_BASE          0xfff00000
 197
 198 /*
 199  * Definitions for initial stack pointer and data area
 200  */
 201 #define CONFIG_SYS_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
 202 #define CONFIG_SYS_INIT_RAM_END        0x4000
 203 #define CONFIG_SYS_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
 204 #define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 205 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 206
 207 /*
 208  * Flash mapping/organization on the MPC10x.
 209  */
 210 #define FLASH_BASE0_PRELIM      0xff800000
 211 #define FLASH_BASE1_PRELIM      0xffc00000
 212
 213 #define CONFIG_SYS_MAX_FLASH_BANKS     2           /* max number of memory banks    */
 214 #define CONFIG_SYS_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
 215
 216 #define CONFIG_SYS_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
 217 #define CONFIG_SYS_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
 218
 219 /*
 220  * JFFS2 partitions
 221  *
 222  */
 223 /* No command line, one static partition */
 224 #undef CONFIG_CMD_MTDPARTS
 225 #define CONFIG_JFFS2_DEV                "nor"
 226 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 227 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 228
 229 /* mtdparts command line support
 230  *
 231  * Note: fake mtd_id used, no linux mtd map file
 232  */
 233 /*
 234 #define CONFIG_CMD_MTDPARTS
 235 #define MTDIDS_DEFAULT          "nor0=bab7xx-0"
 236 #define MTDPARTS_DEFAULT        "mtdparts=bab7xx-0:-(jffs2)"
 237 */
 238
 239 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
 240 #define CONFIG_SYS_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
 241 #define CONFIG_SYS_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
 242 #undef  CONFIG_SYS_MEMTEST
 243
 244 /*
 245  * Environment settings
 246  */
 247 #define CONFIG_ENV_OVERWRITE
 248 #define CONFIG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
 249 #define CONFIG_SYS_NVRAM_SIZE          0x1ff0      /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
 250 #define CONFIG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
 251 /*
 252  * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
 253  * user applications can use the remaining space for other purposes.
 254  */
 255 #define CONFIG_ENV_ADDR            (CONFIG_SYS_NVRAM_SIZE +0x10 -0x800)
 256 #define CONFIG_SYS_NV_SROM_COPY_ADDR   (CONFIG_SYS_NVRAM_SIZE +0x10 -0x400)
 257 #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE            /* This board needs a special routine to access the NVRAM */
 258 #define CONFIG_SYS_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
 259
 260 /*
 261  * Serial devices
 262  */
 263 #define CONFIG_SYS_NS16550
 264 #define CONFIG_SYS_NS16550_SERIAL
 265 #define CONFIG_SYS_NS16550_REG_SIZE    1
 266 #define CONFIG_SYS_NS16550_CLK         1843200
 267 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
 268 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
 269
 270 /*
 271  * PCI stuff
 272  */
 273 #define CONFIG_PCI                                /* include pci support */
 274 #define CONFIG_SYS_EARLY_PCI_INIT
 275 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 276 #define CONFIG_PCI_HOST         PCI_HOST_AUTO
 277 #undef  CONFIG_PCI_SCAN_SHOW
 278
 279 /*
 280  * Video console (graphic: SMI LynxEM, keyboard: i8042)
 281  */
 282 #define CONFIG_VIDEO
 283 #define CONFIG_CFB_CONSOLE
 284 #define CONFIG_VIDEO_SMI_LYNXEM
 285 #define CONFIG_I8042_KBD
 286 #define CONFIG_VIDEO_LOGO
 287 #define CONFIG_CONSOLE_TIME
 288 #define CONFIG_CONSOLE_EXTRA_INFO
 289 #define CONFIG_CONSOLE_CURSOR
 290 #define CONFIG_SYS_CONSOLE_BLINK_COUNT         30000    /* approx. 2 HZ */
 291
 292 /*
 293  * IDE/SCSI globals
 294  */
 295 #ifndef __ASSEMBLY__
 296 extern unsigned int    eltec_board;
 297 extern unsigned int    ata_reset_time;
 298 extern unsigned int    scsi_reset_time;
 299 extern unsigned short  scsi_dev_id;
 300 extern unsigned int    scsi_max_scsi_id;
 301 extern unsigned char   scsi_sym53c8xx_ccf;
 302 #endif
 303
 304 /*
 305  * ATAPI Support (experimental)
 306  */
 307 #define CONFIG_ATAPI
 308 #define CONFIG_SYS_IDE_MAXBUS          1                       /* max. 2 IDE busses    */
 309 #define CONFIG_SYS_IDE_MAXDEVICE       (CONFIG_SYS_IDE_MAXBUS*2)      /* max. 2 drives per IDE bus */
 310
 311 #define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_60X_PCI_IO_OFFSET   /* base address */
 312 #define CONFIG_SYS_ATA_IDE0_OFFSET     0x1F0                   /* default ide0 offste */
 313 #define CONFIG_SYS_ATA_IDE1_OFFSET     0x170                   /* default ide1 offset */
 314 #define CONFIG_SYS_ATA_DATA_OFFSET     0                       /* data reg offset    */
 315 #define CONFIG_SYS_ATA_REG_OFFSET      0                       /* reg offset */
 316 #define CONFIG_SYS_ATA_ALT_OFFSET      0x200                   /* alternate register offset */
 317
 318 #define ATA_RESET_TIME          (ata_reset_time)
 319
 320 #undef  CONFIG_IDE_PCMCIA                               /* no pcmcia interface required */
 321 #undef  CONFIG_IDE_LED                                  /* no led for ide supported */
 322
 323 /*
 324  * SCSI support (experimental) only SYM53C8xx supported
 325  */
 326 #define CONFIG_SCSI_SYM53C8XX
 327 #define CONFIG_SCSI_DEV_ID      (scsi_dev_id)           /* 875 or 860 */
 328 #define CONFIG_SYS_SCSI_SYM53C8XX_CCF  (scsi_sym53c8xx_ccf)    /* value for none 40 mhz clocks */
 329 #define CONFIG_SYS_SCSI_MAX_LUN        8                       /* number of supported LUNs */
 330 #define CONFIG_SYS_SCSI_MAX_SCSI_ID    (scsi_max_scsi_id)      /* max SCSI ID (0-6) */
 331 #define CONFIG_SYS_SCSI_MAX_DEVICE     (15 * CONFIG_SYS_SCSI_MAX_LUN) /* max. Target devices */
 332 #define CONFIG_SYS_SCSI_SPIN_UP_TIME   (scsi_reset_time)
 333
 334 /*
 335  * Partion suppport
 336  */
 337 #define CONFIG_DOS_PARTITION
 338 #define CONFIG_MAC_PARTITION
 339 #define CONFIG_ISO_PARTITION
 340
 341 /*
 342  * Winbond Configuration
 343  */
 344 #define CONFIG_WINBOND_83C553      1                       /* has a winbond bridge */
 345 #define CONFIG_SYS_USE_WINBOND_IDE     0                       /* use winbond 83c553 internal ide */
 346 #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800          /* pci-isa bridge config addr */
 347 #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900          /* ide config addr */
 348
 349 /*
 350  * NS87308 Configuration
 351  */
 352 #define CONFIG_NS87308                    /* Nat Semi super-io cntr on ISA bus */
 353 #define CONFIG_SYS_NS87308_BADDR_10    1
 354 #define CONFIG_SYS_NS87308_DEVS        (CONFIG_SYS_NS87308_UART1   | \
 355                                  CONFIG_SYS_NS87308_UART2   | \
 356                                  CONFIG_SYS_NS87308_KBC1    | \
 357                                  CONFIG_SYS_NS87308_MOUSE   | \
 358                                  CONFIG_SYS_NS87308_FDC     | \
 359                                  CONFIG_SYS_NS87308_RARP    | \
 360                                  CONFIG_SYS_NS87308_GPIO    | \
 361                                  CONFIG_SYS_NS87308_POWRMAN | \
 362                                  CONFIG_SYS_NS87308_RTC_APC )
 363
 364 #define CONFIG_SYS_NS87308_PS2MOD
 365 #define CONFIG_SYS_NS87308_GPIO_BASE   0x0220
 366 #define CONFIG_SYS_NS87308_PWMAN_BASE  0x0460
 367 #define CONFIG_SYS_NS87308_PMC2        0x00        /* SuperI/O clock source is 24MHz via X1 */
 368
 369 /*
 370  * set up the NVRAM access registers
 371  * NVRAM's controlled by the configurable CS line from the 87308
 372  */
 373 #define CONFIG_SYS_NS87308_CS0_BASE    0x0076
 374 #define CONFIG_SYS_NS87308_CS0_CONF    0x40
 375 #define CONFIG_SYS_NS87308_CS1_BASE    0x0070
 376 #define CONFIG_SYS_NS87308_CS1_CONF    0x1C
 377 #define CONFIG_SYS_NS87308_CS2_BASE    0x0071
 378 #define CONFIG_SYS_NS87308_CS2_CONF    0x1C
 379
 380 #define CONFIG_RTC_MK48T59
 381
 382 /*
 383  * Initial BATs
 384  */
 385 #if 1
 386
 387 #define CONFIG_SYS_IBAT0L 0
 388 #define CONFIG_SYS_IBAT0U 0
 389 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
 390 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
 391
 392 #define CONFIG_SYS_IBAT1L 0
 393 #define CONFIG_SYS_IBAT1U 0
 394 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
 395 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
 396
 397 #define CONFIG_SYS_IBAT2L 0
 398 #define CONFIG_SYS_IBAT2U 0
 399 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
 400 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
 401
 402 #define CONFIG_SYS_IBAT3L 0
 403 #define CONFIG_SYS_IBAT3U 0
 404 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
 405 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 406
 407 #else
 408
 409 /* SDRAM */
 410 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
 411 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 412 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
 413 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
 414
 415 /* address range for flashes */
 416 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
 417 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
 418 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
 419 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
 420
 421 /* ISA IO space */
 422 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
 423 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
 424 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
 425 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
 426
 427 /* ISA memory space */
 428 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
 429 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
 430 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
 431 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 432
 433 #endif
 434
 435 /*
 436  * Speed settings are board specific
 437  */
 438 #ifndef __ASSEMBLY__
 439 extern  unsigned long           bab7xx_get_bus_freq (void);
 440 extern  unsigned long           bab7xx_get_gclk_freq (void);
 441 #endif
 442 #define CONFIG_SYS_BUS_CLK      bab7xx_get_bus_freq()
 443 #define CONFIG_SYS_CPU_CLK      bab7xx_get_gclk_freq()
 444
 445 /*
 446  * For booting Linux, the board info and command line data
 447  * have to be in the first 8 MB of memory, since this is
 448  * the maximum mapped by the Linux kernel during initialization.
 449  */
 450 #define CONFIG_SYS_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
 451
 452 /*
 453  * Cache Configuration
 454  */
 455 #define CONFIG_SYS_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
 456 #if defined(CONFIG_CMD_KGDB)
 457 #define CONFIG_SYS_CACHELINE_SHIFT        5    /* log base 2 of the above value */
 458 #endif
 459
 460 /*
 461  * L2 Cache Configuration is board specific for BAB740/BAB750
 462  * Init values read from revision srom.
 463  */
 464 #undef  CONFIG_SYS_L2
 465 #define L2_INIT     (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 466                      L2CR_L2OH_5   | L2CR_L2CTL   | L2CR_L2WT)
 467 #define L2_ENABLE   (L2_INIT | L2CR_L2E)
 468
 469 #define CONFIG_SYS_L2_BAB7xx
 470
 471 #define CONFIG_NET_MULTI                /* Multi ethernet cards support */
 472 #define CONFIG_TULIP
 473 #define CONFIG_TULIP_SELECT_MEDIA
 474
 475 #endif    /* __CONFIG_H */