include/configs/BC3450.h

   1 /*
   2  * -- Version 1.1 --
   3  *
   4  * (C) Copyright 2003-2005
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * (C) Copyright 2004-2005
   8  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   9  *
  10  * (C) Copyright 2005
  11  * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
  12  *
  13  * History:
  14  *      1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  */
  41 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU           */
  42 #define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU)   */
  43 #define CONFIG_TQM5200          1       /* ... on a TQM5200 module          */
  44
  45 #define CONFIG_BC3450           1       /* ... on a BC3450 mainboard        */
  46 #define CONFIG_BC3450_PS2       1       /*  + a PS/2 converter onboard      */
  47 #define CONFIG_BC3450_IDE       1       /*  + IDE drives (Compact Flash)    */
  48 #define CONFIG_BC3450_USB       1       /*  + USB support                   */
  49 # define CONFIG_FAT             1       /*    + FAT support                 */
  50 # define CONFIG_EXT2            1       /*    + EXT2 support                */
  51 #undef CONFIG_BC3450_BUZZER             /*  + Buzzer onboard                */
  52 #undef CONFIG_BC3450_CAN                /*  + CAN transceiver               */
  53 #undef CONFIG_BC3450_DS1340             /*  + a RTC DS1340 onboard          */
  54 #undef CONFIG_BC3450_DS3231             /*  + a RTC DS3231 onboard      tbd */
  55 #undef CONFIG_BC3450_AC97               /*  + AC97 on PSC2,             tbd */
  56 #define CONFIG_BC3450_FP        1       /*  + enable FP O/P                 */
  57 #undef CONFIG_BC3450_CRT                /*  + enable CRT O/P (Debug only!)  */
  58
  59 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz     */
  60
  61 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
  62 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
  63
  64 /*
  65  * Serial console configuration
  66  */
  67 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  68 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps            */
  69 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  70
  71 /*
  72  * AT-PS/2 Multiplexer
  73  */
  74 #ifdef CONFIG_BC3450_PS2
  75 # define CONFIG_PS2KBD                  /* AT-PS/2 Keyboard             */
  76 # define CONFIG_PS2MULT                 /* .. on PS/2 Multiplexer       */
  77 # define CONFIG_PS2SERIAL       6               /* .. on PSC6           */
  78 # define CONFIG_PS2MULT_DELAY   (CFG_HZ/2)      /* Initial delay        */
  79 # define CONFIG_BOARD_EARLY_INIT_R
  80 #endif /* CONFIG_BC3450_PS2 */
  81
  82 /*
  83  * PCI Mapping:
  84  * 0x40000000 - 0x4fffffff - PCI Memory
  85  * 0x50000000 - 0x50ffffff - PCI IO Space
  86  */
  87 # define CONFIG_PCI             1
  88 # define CONFIG_PCI_PNP         1
  89 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  90 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  91
  92 #define CONFIG_PCI_MEM_BUS      0x40000000
  93 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  94 #define CONFIG_PCI_MEM_SIZE     0x10000000
  95
  96 #define CONFIG_PCI_IO_BUS       0x50000000
  97 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  98 #define CONFIG_PCI_IO_SIZE      0x01000000
  99
 100 #define CONFIG_NET_MULTI        1
 101 /*#define CONFIG_EEPRO100       XXX - FIXME: conflicts when CONFIG_MII is enabled */
 102 #define CFG_RX_ETH_BUFFER       8       /* use 8 rx buffer on eepro100  */
 103 #define CONFIG_NS8382X          1
 104
 105 /*
 106  * Video console
 107  */
 108 # define CONFIG_VIDEO
 109 # define CONFIG_VIDEO_SM501
 110 # define CONFIG_VIDEO_SM501_32BPP
 111 # define CONFIG_CFB_CONSOLE
 112 # define CONFIG_VIDEO_LOGO
 113 # define CONFIG_VGA_AS_SINGLE_DEVICE
 114 # define CONFIG_CONSOLE_EXTRA_INFO      /* display Board/Device-Infos */
 115 # define CONFIG_VIDEO_SW_CURSOR
 116 # define CONFIG_SPLASH_SCREEN
 117 # define CFG_CONSOLE_IS_IN_ENV
 118
 119 /*
 120  * Partitions
 121  */
 122 #define CONFIG_MAC_PARTITION
 123 #define CONFIG_DOS_PARTITION
 124 #define CONFIG_ISO_PARTITION
 125
 126 /*
 127  * USB
 128  */
 129 #ifdef CONFIG_BC3450_USB
 130 # define CONFIG_USB_OHCI
 131 # define CONFIG_USB_STORAGE
 132 #endif /* CONFIG_BC3450_USB */
 133
 134 /*
 135  * POST support
 136  */
 137 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 138                                  CFG_POST_CPU      | \
 139                                  CFG_POST_I2C)
 140
 141 #ifdef CONFIG_POST
 142 /* preserve space for the post_word at end of on-chip SRAM */
 143 # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 144 #endif /* CONFIG_POST */
 145
 146
 147 /*
 148  * BOOTP options
 149  */
 150 #define CONFIG_BOOTP_BOOTFILESIZE
 151 #define CONFIG_BOOTP_BOOTPATH
 152 #define CONFIG_BOOTP_GATEWAY
 153 #define CONFIG_BOOTP_HOSTNAME
 154
 155
 156 /*
 157  * Command line configuration.
 158  */
 159 #include <config_cmd_default.h>
 160
 161 #define CONFIG_CMD_ASKENV
 162 #define CONFIG_CMD_DATE
 163 #define CONFIG_CMD_DHCP
 164 #define CONFIG_CMD_ECHO
 165 #define CONFIG_CMD_EEPROM
 166 #define CONFIG_CMD_I2C
 167 #define CONFIG_CMD_JFFS2
 168 #define CONFIG_CMD_MII
 169 #define CONFIG_CMD_NFS
 170 #define CONFIG_CMD_PING
 171 #define CONFIG_CMD_REGINFO
 172 #define CONFIG_CMD_SNTP
 173 #define CONFIG_CMD_BSP
 174
 175 #ifdef CONFIG_VIDEO
 176     #define CONFIG_CMD_BMP
 177 #endif
 178
 179 #ifdef CONFIG_BC3450_IDE
 180     #define CONFIG_CMD_IDE
 181 #endif
 182
 183 #if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
 184     #ifdef CONFIG_FAT
 185         #define CONFIG_CMD_FAT
 186     #endif
 187
 188     #ifdef CONFIG_EXT2
 189         #define CONFIG_CMD_EXT2
 190     #endif
 191 #endif
 192
 193 #ifdef CONFIG_BC3450_USB
 194     #define CONFIG_CMD_USB
 195 #endif
 196
 197 #ifdef CONFIG_PCI
 198     #define CONFIG_CMD_PCI
 199 #endif
 200
 201 #ifdef CONFIG_POST
 202     #define CONFIG_CMD_DIAG
 203 #endif
 204
 205
 206 #define CONFIG_TIMESTAMP                /* display image timestamps */
 207
 208 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 209 #   define CFG_LOWBOOT          1
 210 #endif
 211
 212 /*
 213  * Autobooting
 214  */
 215 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 216 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 217
 218 #define CONFIG_PREBOOT  "echo;" \
 219         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 220         "echo;"
 221
 222 #undef  CONFIG_BOOTARGS
 223
 224 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 225         "netdev=eth0\0"                                                 \
 226         "ipaddr=192.168.1.10\0"                                         \
 227         "serverip=192.168.1.3\0"                                        \
 228         "netmask=255.255.255.0\0"                                       \
 229         "hostname=bc3450\0"                                             \
 230         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 231         "kernel_addr=fc0a0000\0"                                        \
 232         "ramdisk_addr=fc1c0000\0"                                       \
 233         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 234         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 235                 "nfsroot=$(serverip):$(rootpath)\0"                     \
 236         "ideargs=setenv bootargs root=/dev/hda2 ro\0"                   \
 237         "addip=setenv bootargs $(bootargs) "                            \
 238                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 239                 ":$(hostname):$(netdev):off panic=1\0"                  \
 240         "addcons=setenv bootargs $(bootargs) "                          \
 241                 "console=ttyS0,$(baudrate) console=tty0\0"              \
 242         "flash_self=run ramargs addip addcons;"                         \
 243                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
 244         "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"   \
 245         "net_nfs=tftp 200000 $(bootfile); "                             \
 246                 "run nfsargs addip addcons; bootm\0"                    \
 247         "ide_nfs=run nfsargs addip addcons; "                           \
 248                 "disk 200000 0:1; bootm\0"                              \
 249         "ide_ide=run ideargs addip addcons; "                           \
 250                 "disk 200000 0:1; bootm\0"                              \
 251         "usb_self=run usbload; run ramargs addip addcons; "             \
 252                 "bootm 200000 400000\0"                                 \
 253         "usbload=usb reset; usb scan; usbboot 200000 0:1; "             \
 254                 "usbboot 400000 0:2\0"                                  \
 255         "bootfile=uImage\0"                                             \
 256         "load=tftp 200000 $(u-boot)\0"                                  \
 257         "u-boot=u-boot.bin\0"                                           \
 258         "update=protect off FC000000 FC05FFFF;"                         \
 259                 "erase FC000000 FC05FFFF;"                              \
 260                 "cp.b 200000 FC000000 $(filesize);"                     \
 261                 "protect on FC000000 FC05FFFF\0"                        \
 262         ""
 263
 264 #define CONFIG_BOOTCOMMAND      "run flash_self"
 265
 266 /*
 267  * IPB Bus clocking configuration.
 268  */
 269 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 270
 271 /*
 272  * PCI Bus clocking configuration
 273  *
 274  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 275  * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 276  *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 277  */
 278 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 279 # define CFG_PCICLK_EQUALS_IPBCLK_DIV2  /* define for 66MHz speed */
 280 #endif
 281
 282 /*
 283  * I2C configuration
 284  */
 285 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 286 #define CFG_I2C_MODULE          2       /* Select I2C module #2 */
 287
 288 /*
 289  * I2C clock frequency
 290  *
 291  * Please notice, that the resulting clock frequency could differ from the
 292  * configured value. This is because the I2C clock is derived from system
 293  * clock over a frequency divider with only a few divider values. U-boot
 294  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 295  * approximation allways lies below the configured value, never above.
 296  */
 297 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 298 #define CFG_I2C_SLAVE           0x7F
 299
 300 /*
 301  * EEPROM configuration for I²C EEPROM M24C32
 302  * M24C64 should work also. For other EEPROMs config should be verified.
 303  *
 304  * The TQM5200 module may hold an EEPROM at address 0x50.
 305  */
 306 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x (TQM) */
 307 #define CFG_I2C_EEPROM_ADDR_LEN         2
 308 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 309 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 310
 311 /*
 312  * RTC configuration
 313  */
 314 #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
 315 # define CONFIG_RTC_M41T11      1
 316 # define CFG_I2C_RTC_ADDR       0x68
 317 #else
 318 # define CONFIG_RTC_MPC5200     1       /* use MPC5200 internal RTC */
 319 # define CONFIG_BOARD_EARLY_INIT_R
 320 #endif
 321
 322 /*
 323  * Flash configuration
 324  */
 325 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 326
 327 /* use CFI flash driver if no module variant is spezified */
 328 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 329 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 330 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 331 #define CFG_FLASH_EMPTY_INFO
 332 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 333 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 334 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 335
 336 #if !defined(CFG_LOWBOOT)
 337 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 338 #else   /* CFG_LOWBOOT */
 339 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 340 #endif  /* CFG_LOWBOOT */
 341 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 342                                            (= chip selects) */
 343 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 344 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 345
 346 /* Dynamic MTD partition support */
 347 #define CONFIG_JFFS2_CMDLINE
 348 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 349 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 350                                                 "1408k(kernel),"        \
 351                                                 "2m(initrd),"           \
 352                                                 "4m(small-fs),"         \
 353                                                 "16m(big-fs),"          \
 354                                                 "8m(misc)"
 355
 356 /*
 357  * Environment settings
 358  */
 359 #define CFG_ENV_IS_IN_FLASH     1
 360 #define CFG_ENV_SIZE            0x10000
 361 #define CFG_ENV_SECT_SIZE       0x20000
 362 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 363 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 364
 365 /*
 366  * Memory map
 367  */
 368 #define CFG_MBAR                0xF0000000
 369 #define CFG_SDRAM_BASE          0x00000000
 370 #define CFG_DEFAULT_MBAR        0x80000000
 371
 372 /* Use ON-Chip SRAM until RAM will be available */
 373 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 374 #ifdef CONFIG_POST
 375 /* preserve space for the post_word at end of on-chip SRAM */
 376 # define CFG_INIT_RAM_END       MPC5XXX_SRAM_POST_SIZE
 377 #else
 378 # define CFG_INIT_RAM_END       MPC5XXX_SRAM_SIZE
 379 #endif /*CONFIG_POST*/
 380
 381 #define CFG_GBL_DATA_SIZE       128     /* Bytes reserved for initial data  */
 382 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 383 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 384
 385 #define CFG_MONITOR_BASE        TEXT_BASE
 386 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 387 #   define CFG_RAMBOOT          1
 388 #endif
 389
 390 #define CFG_MONITOR_LEN         (384 << 10) /* Reserve 384 kB for Monitor   */
 391 #define CFG_MALLOC_LEN          (128 << 10) /* Reserve 128 kB for malloc()  */
 392 #define CFG_BOOTMAPSZ           (8 << 20)   /* Initial Memory map for Linux */
 393
 394 /*
 395  * Ethernet configuration
 396  *
 397  * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
 398  */
 399 #define CONFIG_MPC5xxx_FEC      1
 400 #undef CONFIG_FEC_10MBIT
 401 #define CONFIG_PHY_ADDR         0x00
 402
 403 /*
 404  * GPIO configuration on BC3450
 405  *
 406  *  PSC1:   UART1 (Service-UART)         [0x xxxxxxx4]
 407  *  PSC2:   UART2                        [0x xxxxxx4x]
 408  *    or:   AC/97 if CONFIG_BC3450_AC97  [0x xxxxxx2x]
 409  *  PSC3:   USB2                         [0x xxxxx1xx]
 410  *  USB:    UART4(ext.)/UART5(int.)      [0x xxxx2xxx]
 411  *            (this has to match
 412  *            CONFIG_USB_CONFIG which is
 413  *            used by usb_ohci.c to set
 414  *            the USB ports)
 415  *  Eth:    10/100Mbit Ethernet          [0x xxx0xxxx]
 416  *            (this is reset to '5'
 417  *            in FEC driver: fec.c)
 418  *  PSC6:   UART6 (int. to PS/2 contr.)  [0x xx5xxxxx]
 419  *  ATA/CS: ???                          [0x x1xxxxxx]
 420  *          FIXME! UM Fig 2-10 suggests  [0x x0xxxxxx]
 421  *  CS1:    Use Pin gpio_wkup_6 as second
 422  *          SDRAM chip select (mem_cs1)
 423  *  Timer:  CAN2 / SPI
 424  *  I2C:    CAN1 / I²C2                  [0x bxxxxxxx]
 425  */
 426 #ifdef CONFIG_BC3450_AC97
 427 # define CFG_GPS_PORT_CONFIG    0xb1502124
 428 #else /* PSC2=UART2 */
 429 # define CFG_GPS_PORT_CONFIG    0xb1502144
 430 #endif
 431
 432 /*
 433  * Miscellaneous configurable options
 434  */
 435 #define CFG_LONGHELP                            /* undef to save memory     */
 436 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt   */
 437 #if defined(CONFIG_CMD_KGDB)
 438 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size  */
 439 #else
 440 #define CFG_CBSIZE              256             /* Console I/O Buffer Size  */
 441 #endif
 442 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size  */
 443 #define CFG_MAXARGS             16              /* max no of command args   */
 444 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Arg. Buffer Size    */
 445
 446 #define CFG_ALT_MEMTEST                         /* Enable an alternative,   */
 447                                                 /*  more extensive mem test */
 448
 449 #define CFG_MEMTEST_START       0x00100000      /* memtest works on         */
 450 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM      */
 451
 452 #define CFG_LOAD_ADDR           0x100000        /* default load address     */
 453
 454 #define CFG_HZ                  1000            /* dec freq: 1ms ticks      */
 455
 456 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs                 */
 457 #if defined(CONFIG_CMD_KGDB)
 458 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value    */
 459 #endif
 460
 461 /*
 462  * Enable loopw command.
 463  */
 464 #define CONFIG_LOOPW
 465
 466 /*
 467  * Various low-level settings
 468  */
 469 #if defined(CONFIG_MPC5200)
 470 # define CFG_HID0_INIT          HID0_ICE | HID0_ICFI
 471 # define CFG_HID0_FINAL         HID0_ICE
 472 #else
 473 # define CFG_HID0_INIT          0
 474 # define CFG_HID0_FINAL         0
 475 #endif
 476
 477 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 478 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 479 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 480 # define CFG_BOOTCS_CFG         0x0008DF30      /* for pci_clk  = 66 MHz */
 481 #else
 482 # define CFG_BOOTCS_CFG         0x0004DF30      /* for pci_clk = 33 MHz  */
 483 #endif
 484 #define CFG_CS0_START           CFG_FLASH_BASE
 485 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 486
 487 /* automatic configuration of chip selects */
 488 #ifdef CONFIG_TQM5200
 489 # define CONFIG_LAST_STAGE_INIT
 490 #endif /* CONFIG_TQM5200 */
 491
 492 /*
 493  * SRAM - Do not map below 2 GB in address space, because this area is used
 494  * for SDRAM autosizing.
 495  */
 496 #ifdef CONFIG_TQM5200
 497 # define CFG_CS2_START          0xE5000000
 498 # define CFG_CS2_SIZE           0x100000        /* 1 MByte */
 499 # define CFG_CS2_CFG            0x0004D930
 500 #endif /* CONFIG_TQM5200 */
 501
 502 /*
 503  * Grafic controller - Do not map below 2 GB in address space, because this
 504  * area is used for SDRAM autosizing.
 505  */
 506 #ifdef CONFIG_TQM5200
 507 # define SM501_FB_BASE          0xE0000000
 508 # define CFG_CS1_START          (SM501_FB_BASE)
 509 # define CFG_CS1_SIZE           0x4000000       /* 64 MByte */
 510 # define CFG_CS1_CFG            0x8F48FF70
 511 # define SM501_MMIO_BASE        CFG_CS1_START + 0x03E00000
 512 #endif /* CONFIG_TQM5200 */
 513
 514 #define CFG_CS_BURST            0x00000000
 515 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for     */
 516                                                 /*  flash and SM501     */
 517
 518 #define CFG_RESET_ADDRESS       0xff000000
 519
 520 /*
 521  * USB stuff
 522  */
 523 #define CONFIG_USB_CLOCK        0x0001BBBB
 524 #define CONFIG_USB_CONFIG       0x00002000      /* we're using Port 2   */
 525
 526 /*
 527  * IDE/ATA stuff Supports IDE harddisk
 528  */
 529 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 530
 531 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE     not supported */
 532 #undef  CONFIG_IDE_LED                  /* LED for ide    not supported */
 533
 534 #define CONFIG_IDE_RESET                /* reset for ide      supported */
 535 #define CONFIG_IDE_PREINIT
 536
 537 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 538 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drives per IDE bus    */
 539
 540 #define CFG_ATA_IDE0_OFFSET     0x0000
 541
 542 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 543
 544 /* Offset for data I/O */
 545 #define CFG_ATA_DATA_OFFSET     (0x0060)
 546
 547 /* Offset for normal register accesses */
 548 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 549
 550 /* Offset for alternate registers */
 551 #define CFG_ATA_ALT_OFFSET      (0x005C)
 552
 553 /* Interval between registers */
 554 #define CFG_ATA_STRIDE          4
 555
 556 #endif /* __CONFIG_H */