include/configs/BC3450.h

   1 /*
   2  * -- Version 1.1 --
   3  *
   4  * (C) Copyright 2003-2005
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * (C) Copyright 2004-2005
   8  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   9  *
  10  * (C) Copyright 2005
  11  * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
  12  *
  13  * History:
  14  *      1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  */
  41 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU           */
  42 #define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU)   */
  43 #define CONFIG_TQM5200          1       /* ... on a TQM5200 module          */
  44
  45 #define CONFIG_BC3450           1       /* ... on a BC3450 mainboard        */
  46 #define CONFIG_BC3450_PS2       1       /*  + a PS/2 converter onboard      */
  47 #define CONFIG_BC3450_IDE       1       /*  + IDE drives (Compact Flash)    */
  48 #define CONFIG_BC3450_USB       1       /*  + USB support                   */
  49 # define CONFIG_FAT             1       /*    + FAT support                 */
  50 # define CONFIG_EXT2            1       /*    + EXT2 support                */
  51 #undef CONFIG_BC3450_BUZZER             /*  + Buzzer onboard                */
  52 #undef CONFIG_BC3450_CAN                /*  + CAN transceiver               */
  53 #undef CONFIG_BC3450_DS1340             /*  + a RTC DS1340 onboard          */
  54 #undef CONFIG_BC3450_DS3231             /*  + a RTC DS3231 onboard      tbd */
  55 #undef CONFIG_BC3450_AC97               /*  + AC97 on PSC2,             tbd */
  56 #define CONFIG_BC3450_FP        1       /*  + enable FP O/P                 */
  57 #undef CONFIG_BC3450_CRT                /*  + enable CRT O/P (Debug only!)  */
  58
  59 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz     */
  60
  61 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
  62 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
  63
  64 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs                 */
  65 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  66 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value    */
  67 #endif
  68
  69 /*
  70  * Serial console configuration
  71  */
  72 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  73 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps            */
  74 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  75
  76 /*
  77  * AT-PS/2 Multiplexer
  78  */
  79 #ifdef CONFIG_BC3450_PS2
  80 # define CONFIG_PS2KBD                  /* AT-PS/2 Keyboard             */
  81 # define CONFIG_PS2MULT                 /* .. on PS/2 Multiplexer       */
  82 # define CONFIG_PS2SERIAL       6               /* .. on PSC6           */
  83 # define CONFIG_PS2MULT_DELAY   (CFG_HZ/2)      /* Initial delay        */
  84 # define CONFIG_BOARD_EARLY_INIT_R
  85 #endif /* CONFIG_BC3450_PS2 */
  86
  87 /*
  88  * PCI Mapping:
  89  * 0x40000000 - 0x4fffffff - PCI Memory
  90  * 0x50000000 - 0x50ffffff - PCI IO Space
  91  */
  92 # define CONFIG_PCI             1
  93 # define CONFIG_PCI_PNP         1
  94 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  95
  96 #define CONFIG_PCI_MEM_BUS      0x40000000
  97 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  98 #define CONFIG_PCI_MEM_SIZE     0x10000000
  99
 100 #define CONFIG_PCI_IO_BUS       0x50000000
 101 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 102 #define CONFIG_PCI_IO_SIZE      0x01000000
 103
 104 #define CONFIG_NET_MULTI        1
 105 /*#define CONFIG_EEPRO100       XXX - FIXME: conflicts when CONFIG_MII is enabled */
 106 #define CFG_RX_ETH_BUFFER       8       /* use 8 rx buffer on eepro100  */
 107 #define CONFIG_NS8382X          1
 108
 109 #ifdef CONFIG_PCI
 110 # define ADD_PCI_CMD            CFG_CMD_PCI
 111 #else
 112 # define ADD_PCI_CMD            0
 113 #endif
 114
 115 /*
 116  * Video console
 117  */
 118 # define CONFIG_VIDEO
 119 # define CONFIG_VIDEO_SM501
 120 # define CONFIG_VIDEO_SM501_32BPP
 121 # define CONFIG_CFB_CONSOLE
 122 # define CONFIG_VIDEO_LOGO
 123 # define CONFIG_VGA_AS_SINGLE_DEVICE
 124 # define CONFIG_CONSOLE_EXTRA_INFO      /* display Board/Device-Infos */
 125 # define CONFIG_VIDEO_SW_CURSOR
 126 # define CONFIG_SPLASH_SCREEN
 127 # define CFG_CONSOLE_IS_IN_ENV
 128
 129 #ifdef CONFIG_VIDEO
 130 # define ADD_BMP_CMD            CFG_CMD_BMP
 131 #else
 132 # define ADD_BMP_CMD            0
 133 #endif
 134
 135 /*
 136  * Partitions
 137  */
 138 #define CONFIG_MAC_PARTITION
 139 #define CONFIG_DOS_PARTITION
 140 #define CONFIG_ISO_PARTITION
 141
 142 /*
 143  * USB
 144  */
 145 #ifdef CONFIG_BC3450_USB
 146 # define CONFIG_USB_OHCI
 147 # define ADD_USB_CMD            CFG_CMD_USB
 148 # define CONFIG_USB_STORAGE
 149 #else /* !CONFIG_BC3450_USB */
 150 # define ADD_USB_CMD            0
 151 #endif /* CONFIG_BC3450_USB */
 152
 153 /*
 154  * POST support
 155  */
 156 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 157                                  CFG_POST_CPU      | \
 158                                  CFG_POST_I2C)
 159
 160 #ifdef CONFIG_POST
 161 # define CFG_CMD_POST_DIAG CFG_CMD_DIAG
 162 /* preserve space for the post_word at end of on-chip SRAM */
 163 # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 164 #else
 165 # define CFG_CMD_POST_DIAG 0
 166 #endif /* CONFIG_POST */
 167
 168 /*
 169  * IDE
 170  */
 171 #ifdef CONFIG_BC3450_IDE
 172 # define ADD_IDE_CMD            CFG_CMD_IDE
 173 #else
 174 # define ADD_IDE_CMD            0
 175 #endif /* CONFIG_BC3450_IDE */
 176
 177 /*
 178  * Filesystem support
 179  */
 180 #if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB)
 181 #ifdef CONFIG_FAT
 182 # define ADD_FAT_CMD            CFG_CMD_FAT
 183 #else
 184 # define ADD_FAT_CMD            0
 185 #endif /* CONFIG_FAT */
 186
 187 #ifdef CONFIG_EXT2
 188 # define ADD_EXT2_CMD           CFG_CMD_EXT2
 189 #else
 190 # define ADD_EXT2_CMD           0
 191 #endif /* CONFIG_EXT2 */
 192 #endif /* CONFIG_BC3450_IDE / _USB */
 193
 194 /*
 195  * Supported commands
 196  */
 197 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 198                                 ADD_BMP_CMD     | \
 199                                 ADD_IDE_CMD     | \
 200                                 ADD_FAT_CMD     | \
 201                                 ADD_EXT2_CMD    | \
 202                                 ADD_PCI_CMD     | \
 203                                 ADD_USB_CMD     | \
 204                                 CFG_CMD_ASKENV  | \
 205                                 CFG_CMD_DATE    | \
 206                                 CFG_CMD_DHCP    | \
 207                                 CFG_CMD_ECHO    | \
 208                                 CFG_CMD_EEPROM  | \
 209                                 CFG_CMD_I2C     | \
 210                                 CFG_CMD_JFFS2   | \
 211                                 CFG_CMD_MII     | \
 212                                 CFG_CMD_NFS     | \
 213                                 CFG_CMD_PING    | \
 214                                 CFG_CMD_POST_DIAG | \
 215                                 CFG_CMD_REGINFO | \
 216                                 CFG_CMD_SNTP    | \
 217                                 CFG_CMD_BSP)
 218
 219 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 220 #include <cmd_confdefs.h>
 221
 222 #define CONFIG_TIMESTAMP                /* display image timestamps */
 223
 224 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 225 #   define CFG_LOWBOOT          1
 226 #endif
 227
 228 /*
 229  * Autobooting
 230  */
 231 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 232 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 233
 234 #define CONFIG_PREBOOT  "echo;" \
 235         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 236         "echo;"
 237
 238 #undef  CONFIG_BOOTARGS
 239
 240 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 241         "netdev=eth0\0"                                                 \
 242         "ipaddr=192.168.1.10\0"                                         \
 243         "serverip=192.168.1.3\0"                                        \
 244         "netmask=255.255.255.0\0"                                       \
 245         "hostname=bc3450\0"                                             \
 246         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 247         "kernel_addr=fc0a0000\0"                                        \
 248         "ramdisk_addr=fc1c0000\0"                                       \
 249         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 250         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 251                 "nfsroot=$(serverip):$(rootpath)\0"                     \
 252         "ideargs=setenv bootargs root=/dev/hda2 ro\0"                   \
 253         "addip=setenv bootargs $(bootargs) "                            \
 254                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 255                 ":$(hostname):$(netdev):off panic=1\0"                  \
 256         "addcons=setenv bootargs $(bootargs) "                          \
 257                 "console=ttyS0,$(baudrate) console=tty0\0"              \
 258         "flash_self=run ramargs addip addcons;"                         \
 259                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
 260         "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"   \
 261         "net_nfs=tftp 200000 $(bootfile); "                             \
 262                 "run nfsargs addip addcons; bootm\0"                    \
 263         "ide_nfs=run nfsargs addip addcons; "                           \
 264                 "disk 200000 0:1; bootm\0"                              \
 265         "ide_ide=run ideargs addip addcons; "                           \
 266                 "disk 200000 0:1; bootm\0"                              \
 267         "usb_self=run usbload; run ramargs addip addcons; "             \
 268                 "bootm 200000 400000\0"                                 \
 269         "usbload=usb reset; usb scan; usbboot 200000 0:1; "             \
 270                 "usbboot 400000 0:2\0"                                  \
 271         "bootfile=uImage\0"                                             \
 272         "load=tftp 200000 $(u-boot)\0"                                  \
 273         "u-boot=u-boot.bin\0"                                           \
 274         "update=protect off FC000000 FC05FFFF;"                         \
 275                 "erase FC000000 FC05FFFF;"                              \
 276                 "cp.b 200000 FC000000 $(filesize);"                     \
 277                 "protect on FC000000 FC05FFFF\0"                        \
 278         ""
 279
 280 #define CONFIG_BOOTCOMMAND      "run flash_self"
 281
 282 /*
 283  * IPB Bus clocking configuration.
 284  */
 285 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 286
 287 /*
 288  * PCI Bus clocking configuration
 289  *
 290  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 291  * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 292  *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 293  */
 294 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 295 # define CFG_PCICLK_EQUALS_IPBCLK_DIV2  /* define for 66MHz speed */
 296 #endif
 297
 298 /*
 299  * I2C configuration
 300  */
 301 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 302 #define CFG_I2C_MODULE          2       /* Select I2C module #2 */
 303
 304 /*
 305  * I2C clock frequency
 306  *
 307  * Please notice, that the resulting clock frequency could differ from the
 308  * configured value. This is because the I2C clock is derived from system
 309  * clock over a frequency divider with only a few divider values. U-boot
 310  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 311  * approximation allways lies below the configured value, never above.
 312  */
 313 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 314 #define CFG_I2C_SLAVE           0x7F
 315
 316 /*
 317  * EEPROM configuration for I²C EEPROM M24C32
 318  * M24C64 should work also. For other EEPROMs config should be verified.
 319  *
 320  * The TQM5200 module may hold an EEPROM at address 0x50.
 321  */
 322 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x (TQM) */
 323 #define CFG_I2C_EEPROM_ADDR_LEN         2
 324 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 325 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 326
 327 /*
 328  * RTC configuration
 329  */
 330 #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
 331 # define CONFIG_RTC_M41T11      1
 332 # define CFG_I2C_RTC_ADDR       0x68
 333 #else
 334 # define CONFIG_RTC_MPC5200     1       /* use MPC5200 internal RTC */
 335 # define CONFIG_BOARD_EARLY_INIT_R
 336 #endif
 337
 338 /*
 339  * Flash configuration
 340  */
 341 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 342
 343 /* use CFI flash driver if no module variant is spezified */
 344 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 345 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 346 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 347 #define CFG_FLASH_EMPTY_INFO
 348 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 349 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 350 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 351
 352 #if !defined(CFG_LOWBOOT)
 353 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 354 #else   /* CFG_LOWBOOT */
 355 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 356 #endif  /* CFG_LOWBOOT */
 357 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 358                                            (= chip selects) */
 359 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 360 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 361
 362 /* Dynamic MTD partition support */
 363 #define CONFIG_JFFS2_CMDLINE
 364 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 365 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 366                                                 "1408k(kernel),"        \
 367                                                 "2m(initrd),"           \
 368                                                 "4m(small-fs),"         \
 369                                                 "16m(big-fs),"          \
 370                                                 "8m(misc)"
 371
 372 /*
 373  * Environment settings
 374  */
 375 #define CFG_ENV_IS_IN_FLASH     1
 376 #define CFG_ENV_SIZE            0x10000
 377 #define CFG_ENV_SECT_SIZE       0x20000
 378 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 379 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 380
 381 /*
 382  * Memory map
 383  */
 384 #define CFG_MBAR                0xF0000000
 385 #define CFG_SDRAM_BASE          0x00000000
 386 #define CFG_DEFAULT_MBAR        0x80000000
 387
 388 /* Use ON-Chip SRAM until RAM will be available */
 389 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 390 #ifdef CONFIG_POST
 391 /* preserve space for the post_word at end of on-chip SRAM */
 392 # define CFG_INIT_RAM_END       MPC5XXX_SRAM_POST_SIZE
 393 #else
 394 # define CFG_INIT_RAM_END       MPC5XXX_SRAM_SIZE
 395 #endif /*CONFIG_POST*/
 396
 397 #define CFG_GBL_DATA_SIZE       128     /* Bytes reserved for initial data  */
 398 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 399 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 400
 401 #define CFG_MONITOR_BASE        TEXT_BASE
 402 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 403 #   define CFG_RAMBOOT          1
 404 #endif
 405
 406 #define CFG_MONITOR_LEN         (384 << 10) /* Reserve 384 kB for Monitor   */
 407 #define CFG_MALLOC_LEN          (128 << 10) /* Reserve 128 kB for malloc()  */
 408 #define CFG_BOOTMAPSZ           (8 << 20)   /* Initial Memory map for Linux */
 409
 410 /*
 411  * Ethernet configuration
 412  *
 413  * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
 414  */
 415 #define CONFIG_MPC5xxx_FEC      1
 416 #undef CONFIG_FEC_10MBIT
 417 #define CONFIG_PHY_ADDR         0x00
 418
 419 /*
 420  * GPIO configuration on BC3450
 421  *
 422  *  PSC1:   UART1 (Service-UART)         [0x xxxxxxx4]
 423  *  PSC2:   UART2                        [0x xxxxxx4x]
 424  *    or:   AC/97 if CONFIG_BC3450_AC97  [0x xxxxxx2x]
 425  *  PSC3:   USB2                         [0x xxxxx1xx]
 426  *  USB:    UART4(ext.)/UART5(int.)      [0x xxxx2xxx]
 427  *            (this has to match
 428  *            CONFIG_USB_CONFIG which is
 429  *            used by usb_ohci.c to set
 430  *            the USB ports)
 431  *  Eth:    10/100Mbit Ethernet          [0x xxx0xxxx]
 432  *            (this is reset to '5'
 433  *            in FEC driver: fec.c)
 434  *  PSC6:   UART6 (int. to PS/2 contr.)  [0x xx5xxxxx]
 435  *  ATA/CS: ???                          [0x x1xxxxxx]
 436  *          FIXME! UM Fig 2-10 suggests  [0x x0xxxxxx]
 437  *  CS1:    Use Pin gpio_wkup_6 as second
 438  *          SDRAM chip select (mem_cs1)
 439  *  Timer:  CAN2 / SPI
 440  *  I2C:    CAN1 / I²C2                  [0x bxxxxxxx]
 441  */
 442 #ifdef CONFIG_BC3450_AC97
 443 # define CFG_GPS_PORT_CONFIG    0xb1502124
 444 #else /* PSC2=UART2 */
 445 # define CFG_GPS_PORT_CONFIG    0xb1502144
 446 #endif
 447
 448 /*
 449  * Miscellaneous configurable options
 450  */
 451 #define CFG_LONGHELP                            /* undef to save memory     */
 452 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt   */
 453 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 454 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size  */
 455 #else
 456 #define CFG_CBSIZE              256             /* Console I/O Buffer Size  */
 457 #endif
 458 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size  */
 459 #define CFG_MAXARGS             16              /* max no of command args   */
 460 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Arg. Buffer Size    */
 461
 462 #define CFG_ALT_MEMTEST                         /* Enable an alternative,   */
 463                                                 /*  more extensive mem test */
 464
 465 #define CFG_MEMTEST_START       0x00100000      /* memtest works on         */
 466 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM      */
 467
 468 #define CFG_LOAD_ADDR           0x100000        /* default load address     */
 469
 470 #define CFG_HZ                  1000            /* dec freq: 1ms ticks      */
 471
 472 /*
 473  * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 474  * which is normally part of the default commands (CFV_CMD_DFL)
 475  */
 476 #define CONFIG_LOOPW
 477
 478 /*
 479  * Various low-level settings
 480  */
 481 #if defined(CONFIG_MPC5200)
 482 # define CFG_HID0_INIT          HID0_ICE | HID0_ICFI
 483 # define CFG_HID0_FINAL         HID0_ICE
 484 #else
 485 # define CFG_HID0_INIT          0
 486 # define CFG_HID0_FINAL         0
 487 #endif
 488
 489 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 490 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 491 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 492 # define CFG_BOOTCS_CFG         0x0008DF30      /* for pci_clk  = 66 MHz */
 493 #else
 494 # define CFG_BOOTCS_CFG         0x0004DF30      /* for pci_clk = 33 MHz  */
 495 #endif
 496 #define CFG_CS0_START           CFG_FLASH_BASE
 497 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 498
 499 /* automatic configuration of chip selects */
 500 #ifdef CONFIG_TQM5200
 501 # define CONFIG_LAST_STAGE_INIT
 502 #endif /* CONFIG_TQM5200 */
 503
 504 /*
 505  * SRAM - Do not map below 2 GB in address space, because this area is used
 506  * for SDRAM autosizing.
 507  */
 508 #ifdef CONFIG_TQM5200
 509 # define CFG_CS2_START          0xE5000000
 510 # define CFG_CS2_SIZE           0x100000        /* 1 MByte */
 511 # define CFG_CS2_CFG            0x0004D930
 512 #endif /* CONFIG_TQM5200 */
 513
 514 /*
 515  * Grafic controller - Do not map below 2 GB in address space, because this
 516  * area is used for SDRAM autosizing.
 517  */
 518 #ifdef CONFIG_TQM5200
 519 # define SM501_FB_BASE          0xE0000000
 520 # define CFG_CS1_START          (SM501_FB_BASE)
 521 # define CFG_CS1_SIZE           0x4000000       /* 64 MByte */
 522 # define CFG_CS1_CFG            0x8F48FF70
 523 # define SM501_MMIO_BASE        CFG_CS1_START + 0x03E00000
 524 #endif /* CONFIG_TQM5200 */
 525
 526 #define CFG_CS_BURST            0x00000000
 527 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for     */
 528                                                 /*  flash and SM501     */
 529
 530 #define CFG_RESET_ADDRESS       0xff000000
 531
 532 /*
 533  * USB stuff
 534  */
 535 #define CONFIG_USB_CLOCK        0x0001BBBB
 536 #define CONFIG_USB_CONFIG       0x00002000      /* we're using Port 2   */
 537
 538 /*
 539  * IDE/ATA stuff Supports IDE harddisk
 540  */
 541 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 542
 543 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE     not supported */
 544 #undef  CONFIG_IDE_LED                  /* LED for ide    not supported */
 545
 546 #define CONFIG_IDE_RESET                /* reset for ide      supported */
 547 #define CONFIG_IDE_PREINIT
 548
 549 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 550 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drives per IDE bus    */
 551
 552 #define CFG_ATA_IDE0_OFFSET     0x0000
 553
 554 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 555
 556 /* Offset for data I/O */
 557 #define CFG_ATA_DATA_OFFSET     (0x0060)
 558
 559 /* Offset for normal register accesses */
 560 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 561
 562 /* Offset for alternate registers */
 563 #define CFG_ATA_ALT_OFFSET      (0x005C)
 564
 565 /* Interval between registers */
 566 #define CFG_ATA_STRIDE          4
 567
 568 #endif /* __CONFIG_H */