include/configs/BC3450.h

   1 /*
   2  * -- Version 1.1 --
   3  *
   4  * (C) Copyright 2003-2005
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * (C) Copyright 2004-2005
   8  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   9  *
  10  * (C) Copyright 2005
  11  * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
  12  *
  13  * History:
  14  *      1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  */
  41 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU           */
  42 #define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU)   */
  43 #define CONFIG_TQM5200          1       /* ... on a TQM5200 module          */
  44
  45 #define CONFIG_BC3450           1       /* ... on a BC3450 mainboard        */
  46 #define CONFIG_BC3450_PS2       1       /*  + a PS/2 converter onboard      */
  47 #define CONFIG_BC3450_IDE       1       /*  + IDE drives (Compact Flash)    */
  48 #define CONFIG_BC3450_USB       1       /*  + USB support                   */
  49 # define CONFIG_FAT             1       /*    + FAT support                 */
  50 # define CONFIG_EXT2            1       /*    + EXT2 support                */
  51 #undef CONFIG_BC3450_BUZZER             /*  + Buzzer onboard                */
  52 #undef CONFIG_BC3450_CAN                /*  + CAN transceiver               */
  53 #undef CONFIG_BC3450_DS1340             /*  + a RTC DS1340 onboard          */
  54 #undef CONFIG_BC3450_DS3231             /*  + a RTC DS3231 onboard      tbd */
  55 #undef CONFIG_BC3450_AC97               /*  + AC97 on PSC2,             tbd */
  56 #define CONFIG_BC3450_FP        1       /*  + enable FP O/P                 */
  57 #undef CONFIG_BC3450_CRT                /*  + enable CRT O/P (Debug only!)  */
  58
  59 /*
  60  * Valid values for CONFIG_SYS_TEXT_BASE are:
  61  * 0xFC000000   boot low (standard configuration with room for
  62  *              max 64 MByte Flash ROM)
  63  * 0x00100000   boot from RAM (for testing only)
  64  */
  65 #ifndef CONFIG_SYS_TEXT_BASE
  66 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  67 #endif
  68
  69 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz     */
  70
  71 #define CONFIG_HIGH_BATS        1       /* High BATs supported              */
  72
  73 /*
  74  * Serial console configuration
  75  */
  76 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  77 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps            */
  78 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  79
  80 /*
  81  * AT-PS/2 Multiplexer
  82  */
  83 #ifdef CONFIG_BC3450_PS2
  84 # define CONFIG_PS2KBD                  /* AT-PS/2 Keyboard             */
  85 # define CONFIG_PS2MULT                 /* .. on PS/2 Multiplexer       */
  86 # define CONFIG_PS2SERIAL       6               /* .. on PSC6           */
  87 # define CONFIG_PS2MULT_DELAY   (CONFIG_SYS_HZ/2)       /* Initial delay        */
  88 # define CONFIG_BOARD_EARLY_INIT_R
  89 #endif /* CONFIG_BC3450_PS2 */
  90
  91 /*
  92  * PCI Mapping:
  93  * 0x40000000 - 0x4fffffff - PCI Memory
  94  * 0x50000000 - 0x50ffffff - PCI IO Space
  95  */
  96 # define CONFIG_PCI             1
  97 # define CONFIG_PCI_PNP         1
  98 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  99 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 100
 101 #define CONFIG_PCI_MEM_BUS      0x40000000
 102 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 103 #define CONFIG_PCI_MEM_SIZE     0x10000000
 104
 105 #define CONFIG_PCI_IO_BUS       0x50000000
 106 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 107 #define CONFIG_PCI_IO_SIZE      0x01000000
 108
 109 #define CONFIG_NET_MULTI        1
 110 /*#define CONFIG_EEPRO100       XXX - FIXME: conflicts when CONFIG_MII is enabled */
 111 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
 112 #define CONFIG_NS8382X          1
 113
 114 /*
 115  * Video console
 116  */
 117 # define CONFIG_VIDEO
 118 # define CONFIG_VIDEO_SM501
 119 # define CONFIG_VIDEO_SM501_32BPP
 120 # define CONFIG_CFB_CONSOLE
 121 # define CONFIG_VIDEO_LOGO
 122 # define CONFIG_VGA_AS_SINGLE_DEVICE
 123 # define CONFIG_CONSOLE_EXTRA_INFO      /* display Board/Device-Infos */
 124 # define CONFIG_VIDEO_SW_CURSOR
 125 # define CONFIG_SPLASH_SCREEN
 126 # define CONFIG_SYS_CONSOLE_IS_IN_ENV
 127
 128 /*
 129  * Partitions
 130  */
 131 #define CONFIG_MAC_PARTITION
 132 #define CONFIG_DOS_PARTITION
 133 #define CONFIG_ISO_PARTITION
 134
 135 /*
 136  * USB
 137  */
 138 #ifdef CONFIG_BC3450_USB
 139 # define CONFIG_USB_OHCI
 140 # define CONFIG_USB_STORAGE
 141 #endif /* CONFIG_BC3450_USB */
 142
 143 /*
 144  * POST support
 145  */
 146 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
 147                                  CONFIG_SYS_POST_CPU       | \
 148                                  CONFIG_SYS_POST_I2C)
 149
 150 #ifdef CONFIG_POST
 151 /* preserve space for the post_word at end of on-chip SRAM */
 152 # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 153 #endif /* CONFIG_POST */
 154
 155
 156 /*
 157  * BOOTP options
 158  */
 159 #define CONFIG_BOOTP_BOOTFILESIZE
 160 #define CONFIG_BOOTP_BOOTPATH
 161 #define CONFIG_BOOTP_GATEWAY
 162 #define CONFIG_BOOTP_HOSTNAME
 163
 164
 165 /*
 166  * Command line configuration.
 167  */
 168 #include <config_cmd_default.h>
 169
 170 #define CONFIG_CMD_ASKENV
 171 #define CONFIG_CMD_DATE
 172 #define CONFIG_CMD_DHCP
 173 #define CONFIG_CMD_ECHO
 174 #define CONFIG_CMD_EEPROM
 175 #define CONFIG_CMD_I2C
 176 #define CONFIG_CMD_JFFS2
 177 #define CONFIG_CMD_MII
 178 #define CONFIG_CMD_NFS
 179 #define CONFIG_CMD_PING
 180 #define CONFIG_CMD_REGINFO
 181 #define CONFIG_CMD_SNTP
 182 #define CONFIG_CMD_BSP
 183
 184 #ifdef CONFIG_VIDEO
 185     #define CONFIG_CMD_BMP
 186 #endif
 187
 188 #ifdef CONFIG_BC3450_IDE
 189     #define CONFIG_CMD_IDE
 190 #endif
 191
 192 #if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
 193     #ifdef CONFIG_FAT
 194         #define CONFIG_CMD_FAT
 195     #endif
 196
 197     #ifdef CONFIG_EXT2
 198         #define CONFIG_CMD_EXT2
 199     #endif
 200 #endif
 201
 202 #ifdef CONFIG_BC3450_USB
 203     #define CONFIG_CMD_USB
 204 #endif
 205
 206 #ifdef CONFIG_PCI
 207     #define CONFIG_CMD_PCI
 208 #endif
 209
 210 #ifdef CONFIG_POST
 211     #define CONFIG_CMD_DIAG
 212 #endif
 213
 214
 215 #define CONFIG_TIMESTAMP                /* display image timestamps */
 216
 217 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000)                /* Boot low */
 218 #   define CONFIG_SYS_LOWBOOT           1
 219 #endif
 220
 221 /*
 222  * Autobooting
 223  */
 224 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 225 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 226
 227 #define CONFIG_PREBOOT  "echo;" \
 228         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 229         "echo;"
 230
 231 #undef  CONFIG_BOOTARGS
 232
 233 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 234         "netdev=eth0\0"                                                 \
 235         "ipaddr=192.168.1.10\0"                                         \
 236         "serverip=192.168.1.3\0"                                        \
 237         "netmask=255.255.255.0\0"                                       \
 238         "hostname=bc3450\0"                                             \
 239         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 240         "kernel_addr=fc0a0000\0"                                        \
 241         "ramdisk_addr=fc1c0000\0"                                       \
 242         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 243         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 244                 "nfsroot=$(serverip):$(rootpath)\0"                     \
 245         "ideargs=setenv bootargs root=/dev/hda2 ro\0"                   \
 246         "addip=setenv bootargs $(bootargs) "                            \
 247                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 248                 ":$(hostname):$(netdev):off panic=1\0"                  \
 249         "addcons=setenv bootargs $(bootargs) "                          \
 250                 "console=ttyS0,$(baudrate) console=tty0\0"              \
 251         "flash_self=run ramargs addip addcons;"                         \
 252                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
 253         "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"   \
 254         "net_nfs=tftp 200000 $(bootfile); "                             \
 255                 "run nfsargs addip addcons; bootm\0"                    \
 256         "ide_nfs=run nfsargs addip addcons; "                           \
 257                 "disk 200000 0:1; bootm\0"                              \
 258         "ide_ide=run ideargs addip addcons; "                           \
 259                 "disk 200000 0:1; bootm\0"                              \
 260         "usb_self=run usbload; run ramargs addip addcons; "             \
 261                 "bootm 200000 400000\0"                                 \
 262         "usbload=usb reset; usb scan; usbboot 200000 0:1; "             \
 263                 "usbboot 400000 0:2\0"                                  \
 264         "bootfile=uImage\0"                                             \
 265         "load=tftp 200000 $(u-boot)\0"                                  \
 266         "u-boot=u-boot.bin\0"                                           \
 267         "update=protect off FC000000 FC05FFFF;"                         \
 268                 "erase FC000000 FC05FFFF;"                              \
 269                 "cp.b 200000 FC000000 $(filesize);"                     \
 270                 "protect on FC000000 FC05FFFF\0"                        \
 271         ""
 272
 273 #define CONFIG_BOOTCOMMAND      "run flash_self"
 274
 275 /*
 276  * IPB Bus clocking configuration.
 277  */
 278 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 279
 280 /*
 281  * PCI Bus clocking configuration
 282  *
 283  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 284  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 285  *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 286  */
 287 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 288 # define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2   /* define for 66MHz speed */
 289 #endif
 290
 291 /*
 292  * I2C configuration
 293  */
 294 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 295 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 */
 296
 297 /*
 298  * I2C clock frequency
 299  *
 300  * Please notice, that the resulting clock frequency could differ from the
 301  * configured value. This is because the I2C clock is derived from system
 302  * clock over a frequency divider with only a few divider values. U-boot
 303  * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 304  * approximation allways lies below the configured value, never above.
 305  */
 306 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 307 #define CONFIG_SYS_I2C_SLAVE            0x7F
 308
 309 /*
 310  * EEPROM configuration for I²C EEPROM M24C32
 311  * M24C64 should work also. For other EEPROMs config should be verified.
 312  *
 313  * The TQM5200 module may hold an EEPROM at address 0x50.
 314  */
 315 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x (TQM) */
 316 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 317 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write */
 318 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 319
 320 /*
 321  * RTC configuration
 322  */
 323 #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
 324 # define CONFIG_RTC_M41T11      1
 325 # define CONFIG_SYS_I2C_RTC_ADDR        0x68
 326 #else
 327 # define CONFIG_RTC_MPC5200     1       /* use MPC5200 internal RTC */
 328 # define CONFIG_BOARD_EARLY_INIT_R
 329 #endif
 330
 331 /*
 332  * Flash configuration
 333  */
 334 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
 335
 336 /* use CFI flash driver if no module variant is spezified */
 337 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 338 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 339 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_BOOTCS_START }
 340 #define CONFIG_SYS_FLASH_EMPTY_INFO
 341 #define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MByte */
 342 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 343 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* not supported yet for AMD */
 344
 345 #if !defined(CONFIG_SYS_LOWBOOT)
 346 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
 347 #else   /* CONFIG_SYS_LOWBOOT */
 348 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 349 #endif  /* CONFIG_SYS_LOWBOOT */
 350 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 351                                            (= chip selects) */
 352 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 353 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 354
 355 /* Dynamic MTD partition support */
 356 #define CONFIG_CMD_MTDPARTS
 357 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 358 #define CONFIG_FLASH_CFI_MTD
 359 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 360 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 361                                                 "1408k(kernel),"        \
 362                                                 "2m(initrd),"           \
 363                                                 "4m(small-fs),"         \
 364                                                 "16m(big-fs),"          \
 365                                                 "8m(misc)"
 366
 367 /*
 368  * Environment settings
 369  */
 370 #define CONFIG_ENV_IS_IN_FLASH  1
 371 #define CONFIG_ENV_SIZE         0x10000
 372 #define CONFIG_ENV_SECT_SIZE    0x20000
 373 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 374 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 375
 376 /*
 377  * Memory map
 378  */
 379 #define CONFIG_SYS_MBAR         0xF0000000
 380 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 381 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 382
 383 /* Use ON-Chip SRAM until RAM will be available */
 384 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 385 #ifdef CONFIG_POST
 386 /* preserve space for the post_word at end of on-chip SRAM */
 387 # define CONFIG_SYS_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 388 #else
 389 # define CONFIG_SYS_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 390 #endif /*CONFIG_POST*/
 391
 392 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* Bytes reserved for initial data  */
 393 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 394 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 395
 396 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 397 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 398 #   define CONFIG_SYS_RAMBOOT           1
 399 #endif
 400
 401 #define CONFIG_SYS_MONITOR_LEN          (384 << 10) /* Reserve 384 kB for Monitor   */
 402 #define CONFIG_SYS_MALLOC_LEN           (128 << 10) /* Reserve 128 kB for malloc()  */
 403 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)   /* Initial Memory map for Linux */
 404
 405 /*
 406  * Ethernet configuration
 407  *
 408  * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
 409  */
 410 #define CONFIG_MPC5xxx_FEC      1
 411 #define CONFIG_MPC5xxx_FEC_MII100
 412 #undef CONFIG_MPC5xxx_MII10
 413 #define CONFIG_PHY_ADDR         0x00
 414
 415 /*
 416  * GPIO configuration on BC3450
 417  *
 418  *  PSC1:   UART1 (Service-UART)         [0x xxxxxxx4]
 419  *  PSC2:   UART2                        [0x xxxxxx4x]
 420  *    or:   AC/97 if CONFIG_BC3450_AC97  [0x xxxxxx2x]
 421  *  PSC3:   USB2                         [0x xxxxx1xx]
 422  *  USB:    UART4(ext.)/UART5(int.)      [0x xxxx2xxx]
 423  *            (this has to match
 424  *            CONFIG_USB_CONFIG which is
 425  *            used by usb_ohci.c to set
 426  *            the USB ports)
 427  *  Eth:    10/100Mbit Ethernet          [0x xxx0xxxx]
 428  *            (this is reset to '5'
 429  *            in FEC driver: fec.c)
 430  *  PSC6:   UART6 (int. to PS/2 contr.)  [0x xx5xxxxx]
 431  *  ATA/CS: ???                          [0x x1xxxxxx]
 432  *          FIXME! UM Fig 2-10 suggests  [0x x0xxxxxx]
 433  *  CS1:    Use Pin gpio_wkup_6 as second
 434  *          SDRAM chip select (mem_cs1)
 435  *  Timer:  CAN2 / SPI
 436  *  I2C:    CAN1 / I²C2                  [0x bxxxxxxx]
 437  */
 438 #ifdef CONFIG_BC3450_AC97
 439 # define CONFIG_SYS_GPS_PORT_CONFIG     0xb1502124
 440 #else /* PSC2=UART2 */
 441 # define CONFIG_SYS_GPS_PORT_CONFIG     0xb1502144
 442 #endif
 443
 444 /*
 445  * Miscellaneous configurable options
 446  */
 447 #define CONFIG_SYS_LONGHELP                             /* undef to save memory     */
 448 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt   */
 449 #if defined(CONFIG_CMD_KGDB)
 450 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size  */
 451 #else
 452 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size  */
 453 #endif
 454 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size  */
 455 #define CONFIG_SYS_MAXARGS              16              /* max no of command args   */
 456 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Arg. Buffer Size    */
 457
 458 #define CONFIG_SYS_ALT_MEMTEST                          /* Enable an alternative,   */
 459                                                 /*  more extensive mem test */
 460
 461 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on         */
 462 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM      */
 463
 464 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address     */
 465
 466 #define CONFIG_SYS_HZ                   1000            /* dec freq: 1ms ticks      */
 467
 468 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                 */
 469 #if defined(CONFIG_CMD_KGDB)
 470 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value    */
 471 #endif
 472
 473 /*
 474  * Enable loopw command.
 475  */
 476 #define CONFIG_LOOPW
 477
 478 /*
 479  * Various low-level settings
 480  */
 481 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 482 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 483
 484 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 485 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 486 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 487 # define CONFIG_SYS_BOOTCS_CFG          0x0008DF30      /* for pci_clk  = 66 MHz */
 488 #else
 489 # define CONFIG_SYS_BOOTCS_CFG          0x0004DF30      /* for pci_clk = 33 MHz  */
 490 #endif
 491 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 492 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 493
 494 /* automatic configuration of chip selects */
 495 #ifdef CONFIG_TQM5200
 496 # define CONFIG_LAST_STAGE_INIT
 497 #endif /* CONFIG_TQM5200 */
 498
 499 /*
 500  * SRAM - Do not map below 2 GB in address space, because this area is used
 501  * for SDRAM autosizing.
 502  */
 503 #ifdef CONFIG_TQM5200
 504 # define CONFIG_SYS_CS2_START           0xE5000000
 505 # define CONFIG_SYS_CS2_SIZE            0x100000        /* 1 MByte */
 506 # define CONFIG_SYS_CS2_CFG             0x0004D930
 507 #endif /* CONFIG_TQM5200 */
 508
 509 /*
 510  * Grafic controller - Do not map below 2 GB in address space, because this
 511  * area is used for SDRAM autosizing.
 512  */
 513 #ifdef CONFIG_TQM5200
 514 # define SM501_FB_BASE          0xE0000000
 515 # define CONFIG_SYS_CS1_START           (SM501_FB_BASE)
 516 # define CONFIG_SYS_CS1_SIZE            0x4000000       /* 64 MByte */
 517 # define CONFIG_SYS_CS1_CFG             0x8F48FF70
 518 # define SM501_MMIO_BASE        CONFIG_SYS_CS1_START + 0x03E00000
 519 #endif /* CONFIG_TQM5200 */
 520
 521 #define CONFIG_SYS_CS_BURST             0x00000000
 522 #define CONFIG_SYS_CS_DEADCYCLE 0x33333311      /* 1 dead cycle for     */
 523                                                 /*  flash and SM501     */
 524
 525 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 526
 527 /*
 528  * USB stuff
 529  */
 530 #define CONFIG_USB_CLOCK        0x0001BBBB
 531 #define CONFIG_USB_CONFIG       0x00002000      /* we're using Port 2   */
 532
 533 /*
 534  * IDE/ATA stuff Supports IDE harddisk
 535  */
 536 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 537
 538 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE     not supported */
 539 #undef  CONFIG_IDE_LED                  /* LED for ide    not supported */
 540
 541 #define CONFIG_IDE_RESET                /* reset for ide      supported */
 542 #define CONFIG_IDE_PREINIT
 543
 544 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 545 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 546
 547 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 548
 549 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 550
 551 /* Offset for data I/O */
 552 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 553
 554 /* Offset for normal register accesses */
 555 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 556
 557 /* Offset for alternate registers */
 558 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 559
 560 /* Interval between registers */
 561 #define CONFIG_SYS_ATA_STRIDE           4
 562
 563 #endif /* __CONFIG_H */