include/configs/BUBINGA405EP.h

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /* Debug options */
  32 /*#define __DEBUG_START_FROM_SRAM__ */
  33
  34
  35 /*
  36  * High Level Configuration Options
  37  * (easy to change)
  38  */
  39
  40 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  41 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  42 #define CONFIG_BUBINGA405EP     1       /* ...on a BUBINGA405EP board   */
  43
  44 #define CONFIG_BOARD_PRE_INIT   1       /* Call board_pre_init  */
  45
  46 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  47
  48 #define CONFIG_NO_SERIAL_EEPROM
  49 /*#undef CONFIG_NO_SERIAL_EEPROM*/
  50 /*----------------------------------------------------------------------------*/
  51 /*----------------------------------------------------------------------------*/
  52 /*----------------------------------------------------------------------------*/
  53 #ifdef CONFIG_NO_SERIAL_EEPROM
  54
  55 /*
  56 !-------------------------------------------------------------------------------
  57 ! Defines for entry options.
  58 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
  59 !       are plugged in the board will be utilized as non-ECC DIMMs.
  60 !-------------------------------------------------------------------------------
  61 */
  62 #define        AUTO_MEMORY_CONFIG
  63 #define        DIMM_READ_ADDR 0xAB
  64 #define        DIMM_WRITE_ADDR 0xAA
  65
  66 /*
  67 !-------------------------------------------------------------------------------
  68 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  69 ! assuming a 33MHz input clock to the 405EP from the C9531.
  70 !-------------------------------------------------------------------------------
  71 */
  72 #define PLLMR0_DEFAULT   PLLMR0_266_133_66
  73 #define PLLMR1_DEFAULT   PLLMR1_266_133_66
  74
  75 #endif
  76 /*----------------------------------------------------------------------------*/
  77 /*----------------------------------------------------------------------------*/
  78 /*----------------------------------------------------------------------------*/
  79
  80 /*#define CFG_ENV_IS_IN_FLASH     1*/   /* use FLASH for environment vars       */
  81 #define CFG_ENV_IS_IN_NVRAM     1       /* use NVRAM for environment vars       */
  82
  83 #ifdef CFG_ENV_IS_IN_NVRAM
  84 #undef CFG_ENV_IS_IN_FLASH
  85 #else
  86 #ifdef CFG_ENV_IS_IN_FLASH
  87 #undef CFG_ENV_IS_IN_NVRAM
  88 #endif
  89 #endif
  90
  91 #define CONFIG_BAUDRATE         115200
  92 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  93
  94 #if 1
  95 #define CONFIG_BOOTCOMMAND      "" /* autoboot command  */
  96 #else
  97 #define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  98 #endif
  99
 100 /* Size (bytes) of interrupt driven serial port buffer.
 101  * Set to 0 to use polling instead of interrupts.
 102  * Setting to 0 will also disable RTS/CTS handshaking.
 103  */
 104 #if 0
 105 #define CONFIG_SERIAL_SOFTWARE_FIFO 4000
 106 #else
 107 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 108 #endif
 109
 110 #if 0
 111 #define CONFIG_BOOTARGS         "root=/dev/nfs "                        \
 112     "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "        \
 113     "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
 114 #else
 115 #define CONFIG_BOOTARGS         "root=/dev/hda1 "                       \
 116    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
 117
 118 #endif
 119
 120 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 121 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 122
 123 #define CONFIG_MII              1       /* MII PHY management           */
 124 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 125
 126 #define CONFIG_RTC_DS174x       1       /* use DS1743 RTC in Bubinga    */
 127
 128 /*
 129 #ifndef __DEBUG_START_FROM_SRAM__
 130 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 131                                 CFG_CMD_PCI     | \
 132                                 CFG_CMD_IRQ     | \
 133                                 CFG_CMD_KGDB    | \
 134                                 CFG_CMD_DHCP    | \
 135                                 CFG_CMD_DATE    | \
 136                                 CFG_CMD_BEDBUG  | \
 137                                 CFG_CMD_ELF     )
 138 #else
 139 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 140                                 CFG_CMD_PCI     | \
 141                                 CFG_CMD_IRQ     | \
 142                                 CFG_CMD_KGDB    | \
 143                                 CFG_CMD_DHCP    | \
 144                                 CFG_CMD_DATE    | \
 145                                 CFG_CMD_DATE    | \
 146                                 CFG_CMD_ELF     )
 147 #endif
 148 */
 149
 150 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 151                                 CFG_CMD_PCI     | \
 152                                 CFG_CMD_IRQ     | \
 153                                 CFG_CMD_KGDB    | \
 154                                 CFG_CMD_DHCP    | \
 155                                 CFG_CMD_DATE    | \
 156                                 CFG_CMD_DATE    | \
 157                                 CFG_CMD_ELF     )
 158
 159 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 160 #include <cmd_confdefs.h>
 161
 162 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 163
 164 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 165
 166 /*
 167  * Miscellaneous configurable options
 168  */
 169 #define CFG_LONGHELP                    /* undef to save memory         */
 170 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 171 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 172 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 173 #else
 174 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 175 #endif
 176 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 177 #define CFG_MAXARGS     16              /* max number of command args   */
 178 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 179
 180 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 181 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 182
 183 /*
 184  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 185  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
 186  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
 187  * The Linux BASE_BAUD define should match this configuration.
 188  *    baseBaud = cpuClock/(uartDivisor*16)
 189  * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
 190  * set Linux BASE_BAUD to 403200.
 191  */
 192 #undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
 193 #undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 194 #define CFG_BASE_BAUD       691200
 195
 196 /* The following table includes the supported baudrates */
 197 #define CFG_BAUDRATE_TABLE  \
 198     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 199
 200 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 201 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 202
 203 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 204
 205 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 206 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 207 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 208 #define CFG_I2C_SLAVE           0x7F
 209
 210
 211 /*-----------------------------------------------------------------------
 212  * PCI stuff
 213  *-----------------------------------------------------------------------
 214  */
 215 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 216 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 217 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 218
 219 #define CONFIG_PCI                      /* include pci support          */
 220 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 221 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 222                                         /* resource configuration       */
 223
 224 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 225 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 226 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 227 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 228 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 229 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 230 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 231 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 232
 233 /*-----------------------------------------------------------------------
 234  * External peripheral base address
 235  *-----------------------------------------------------------------------
 236  */
 237 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 238 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 239
 240 #define CFG_KEY_REG_BASE_ADDR   0xF0100000
 241 #define CFG_IR_REG_BASE_ADDR    0xF0200000
 242 #define CFG_FPGA_REG_BASE_ADDR  0xF0300000
 243
 244 /*-----------------------------------------------------------------------
 245  * Start addresses for the final memory configuration
 246  * (Set up by the startup code)
 247  * Please note that CFG_SDRAM_BASE _must_ start at 0
 248  */
 249 #define CFG_SDRAM_BASE          0x00000000
 250 #ifdef __DEBUG_START_FROM_SRAM__
 251 #define CFG_SRAM_BASE           0xFFF80000
 252 #define CFG_FLASH_BASE          0xFFF00000
 253 #define CFG_MONITOR_BASE        CFG_SRAM_BASE
 254 #else
 255 #define CFG_SRAM_BASE           0xFFF00000
 256 #define CFG_FLASH_BASE          0xFFF80000
 257 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 258 #endif
 259
 260
 261 /*#define CFG_MONITOR_LEN               (200 * 1024)    /XXX* Reserve 200 kB for Monitor        */
 262 #define CFG_MONITOR_LEN         (192 * 1024)    /* Reserve 200 kB for Monitor   */
 263 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 264
 265 /*
 266  * For booting Linux, the board info and command line data
 267  * have to be in the first 8 MB of memory, since this is
 268  * the maximum mapped by the Linux kernel during initialization.
 269  */
 270 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 271 /*-----------------------------------------------------------------------
 272  * FLASH organization
 273  */
 274 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 275 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 276
 277 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 278 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 279
 280 /* BEG ENVIRONNEMENT FLASH */
 281 #ifdef CFG_ENV_IS_IN_FLASH
 282 #define CFG_ENV_OFFSET          0x00050000 /* Offset of Environment Sector  */
 283 #define CFG_ENV_SIZE            0x10000 /* Total Size of Environment Sector     */
 284 #define CFG_ENV_SECT_SIZE       0x10000 /* see README - env sector total size   */
 285 #endif
 286 /* END ENVIRONNEMENT FLASH */
 287 /*-----------------------------------------------------------------------
 288  * NVRAM organization
 289  */
 290 #define CFG_NVRAM_BASE_ADDR     0xf0000000      /* NVRAM base address   */
 291 #define CFG_NVRAM_SIZE          0x1ff8          /* NVRAM size   */
 292
 293 #ifdef CFG_ENV_IS_IN_NVRAM
 294 #define CFG_ENV_SIZE            0x1000          /* Size of Environment vars     */
 295 #define CFG_ENV_ADDR            \
 296         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)       /* Env  */
 297 #endif
 298 /*-----------------------------------------------------------------------
 299  * Cache Configuration
 300  */
 301 #define CFG_DCACHE_SIZE         16384   /* For IBM 405EP CPU                    */
 302 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 303 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 304 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 305 #endif
 306
 307 /*
 308  * Init Memory Controller:
 309  *
 310  * BR0/1 and OR0/1 (FLASH)
 311  */
 312
 313 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0        */
 314 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 315
 316
 317 /* Configuration Port location */
 318 #define CONFIG_PORT_ADDR        0xF0000500
 319
 320 /*-----------------------------------------------------------------------
 321  * Definitions for initial stack pointer and data area (in data cache)
 322  */
 323 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 324 #define CFG_TEMP_STACK_OCM        1
 325
 326 /* On Chip Memory location */
 327 #define CFG_OCM_DATA_ADDR       0xF8000000
 328 #define CFG_OCM_DATA_SIZE       0x1000
 329 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 330 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 331
 332 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 333 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 334 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 335
 336 /*-----------------------------------------------------------------------
 337  * External Bus Controller (EBC) Setup
 338  */
 339
 340 /* Memory Bank 0 (Flash/SRAM) initialization                                    */
 341 #define CFG_EBC_PB0AP           0x04006000
 342 #define CFG_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
 343
 344 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 345 #define CFG_EBC_PB1AP           0x04041000
 346 #define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 347
 348 /* Memory Bank 2 (not used) initialization                                      */
 349 #define CFG_EBC_PB2AP           0x00000000
 350 #define CFG_EBC_PB2CR           0x00000000
 351
 352 /* Memory Bank 2 (not used) initialization                                      */
 353 #define CFG_EBC_PB3AP           0x00000000
 354 #define CFG_EBC_PB3CR           0x00000000
 355
 356 /* Memory Bank 4 (FPGA regs) initialization                                     */
 357 #define CFG_EBC_PB4AP           0x01815000
 358 #define CFG_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 359
 360 /*-----------------------------------------------------------------------
 361  * Definitions for Serial Presence Detect EEPROM address
 362  * (to get SDRAM settings)
 363  */
 364 #define SPD_EEPROM_ADDRESS      0x55
 365
 366 /*-----------------------------------------------------------------------
 367  * Definitions for GPIO setup (PPC405EP specific)
 368  *
 369  * GPIO0[0]     - External Bus Controller BLAST output
 370  * GPIO0[1-9]   - Instruction trace outputs
 371  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 372  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 373  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 374  * GPIO0[24-27] - UART0 control signal inputs/outputs
 375  * GPIO0[28-29] - UART1 data signal input/output
 376  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 377  */
 378 #define CFG_GPIO0_OSRH          0x55555555
 379 #define CFG_GPIO0_OSRL          0x40000110
 380 #define CFG_GPIO0_ISR1H         0x00000000
 381 #define CFG_GPIO0_ISR1L         0x15555445
 382 #define CFG_GPIO0_TSRH          0x00000000
 383 #define CFG_GPIO0_TSRL          0x00000000
 384 #define CFG_GPIO0_TCR           0xFFFF8014
 385
 386 /*-----------------------------------------------------------------------
 387  * Some BUBINGA stuff...
 388  */
 389 #define NVRAM_BASE      0xF0000000
 390 #define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
 391 #define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
 392 #define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
 393 #define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/
 394
 395 #define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
 396 #define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
 397 #define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
 398 #define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
 399 #define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
 400 #define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */
 401
 402 #define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
 403 #define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
 404 #define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
 405 #define FPGA_REG1_CLOCK_BIT_SHIFT  4
 406 #define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
 407 #define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
 408 #define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
 409 #define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
 410
 411
 412 /*
 413  * Internal Definitions
 414  *
 415  * Boot Flags
 416  */
 417 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 418 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 419
 420 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 421 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 422 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 423 #endif
 424
 425 #endif  /* __CONFIG_H */