include/configs/CANBT.h

   1 /*
   2  * (C) Copyright 2001
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405CR            1       /* This is a PPC405CR CPU       */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_CANBT            1       /* ...on a CANBT board          */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27
  28 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  29
  30 #define CONFIG_BAUDRATE         115200
  31 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 seconds     */
  32
  33 #undef  CONFIG_BOOTARGS
  34 #define CONFIG_BOOTCOMMAND                                              \
  35         "setenv bootargs root=/dev/ram rw console=ttyS0,115200; "       \
  36         "bootm ffe00000 ffe80000"
  37
  38 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  39 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  40
  41 #undef  CONFIG_PCI_PNP                  /* no pci plug-and-play         */
  42
  43 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  44
  45
  46 /*
  47  * BOOTP options
  48  */
  49 #define CONFIG_BOOTP_BOOTFILESIZE
  50 #define CONFIG_BOOTP_BOOTPATH
  51 #define CONFIG_BOOTP_GATEWAY
  52 #define CONFIG_BOOTP_HOSTNAME
  53
  54
  55 /*
  56  * Command line configuration.
  57  */
  58 #include <config_cmd_default.h>
  59
  60 #define CONFIG_CMD_IRQ
  61 #define CONFIG_CMD_EEPROM
  62
  63 #undef CONFIG_CMD_NET
  64 #undef CONFIG_CMD_NFS
  65
  66 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  67
  68 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  69
  70 /*
  71  * Miscellaneous configurable options
  72  */
  73 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  74 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  75 #if defined(CONFIG_CMD_KGDB)
  76 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  77 #else
  78 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  79 #endif
  80 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  81 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  82 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  83
  84 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  85
  86 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  87 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  88
  89 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  90 #define CONFIG_SYS_NS16550
  91 #define CONFIG_SYS_NS16550_SERIAL
  92 #define CONFIG_SYS_NS16550_REG_SIZE     1
  93 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  94
  95 #define CONFIG_SYS_EXT_SERIAL_CLOCK     14745600 /* use external serial clock   */
  96
  97 /* The following table includes the supported baudrates */
  98 #define CONFIG_SYS_BAUDRATE_TABLE       \
  99         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 100          57600, 115200, 230400, 460800, 921600 }
 101
 102 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 103 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 104
 105 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 106
 107 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 108
 109 /*-----------------------------------------------------------------------
 110  * Start addresses for the final memory configuration
 111  * (Set up by the startup code)
 112  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 113  */
 114 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 115 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 116 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 117 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 118 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 119
 120 /*
 121  * For booting Linux, the board info and command line data
 122  * have to be in the first 8 MB of memory, since this is
 123  * the maximum mapped by the Linux kernel during initialization.
 124  */
 125 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 126 /*-----------------------------------------------------------------------
 127  * FLASH organization
 128  */
 129 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 130 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 131
 132 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 133 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 134
 135 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 136 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 137 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 138 /*
 139  * The following defines are added for buggy IOP480 byte interface.
 140  * All other boards should use the standard values (CPCI405 etc.)
 141  */
 142 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 143 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 144 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 145
 146 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 147
 148 #if 0 /* Use FLASH for environment variables */
 149
 150 #define CONFIG_ENV_IS_IN_FLASH  1
 151 #define CONFIG_ENV_OFFSET               0x00010000      /* Offset of Environment Sector */
 152 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector     */
 153
 154 #define CONFIG_ENV_SECT_SIZE    0x10000 /* see README - env sector total size   */
 155
 156 #else /* Use EEPROM for environment variables */
 157
 158 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 159 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 160 #define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars */
 161                                    /* total size of a CAT24WC08 is 1024 bytes */
 162 #endif
 163
 164 /*-----------------------------------------------------------------------
 165  * I2C EEPROM (CAT24WC08) for environment
 166  */
 167 #define CONFIG_SYS_I2C
 168 #define CONFIG_SYS_I2C_PPC4XX
 169 #define CONFIG_SYS_I2C_PPC4XX_CH0
 170 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 171 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 172
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08     */
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* bytes of address     */
 175 /* mask of address bits that overflow into the "EEPROM chip address"    */
 176 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 177
 178 /*
 179  * Init Memory Controller:
 180  *
 181  * BR0/1 and OR0/1 (FLASH)
 182  */
 183
 184 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 185 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 186
 187 /*-----------------------------------------------------------------------
 188  * External Bus Controller (EBC) Setup
 189  */
 190
 191 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 192 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 193 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 194
 195 /* Memory Bank 1 (CAN/USB) initialization                                       */
 196 #define CONFIG_SYS_EBC_PB1AP            0x010053C0  /* enable Ready, BEM=1              */
 197 #define CONFIG_SYS_EBC_PB1CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 198
 199 /* Memory Bank 2 (Misc-IO/LEDs) initialization                                  */
 200 #define CONFIG_SYS_EBC_PB2AP            0x000004c0  /* no Ready, BEM=1                  */
 201 #define CONFIG_SYS_EBC_PB2CR            0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
 202
 203 /* Memory Bank 3 (CAN Features) initialization                                  */
 204 #define CONFIG_SYS_EBC_PB3AP            0x80000040  /* no Ready, BEM=1                  */
 205 #define CONFIG_SYS_EBC_PB3CR            0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
 206
 207 /*-----------------------------------------------------------------------
 208  * Definitions for initial stack pointer and data area (in RAM)
 209  */
 210 #define CONFIG_SYS_INIT_RAM_ADDR        0x00ef0000 /* inside of SDRAM                   */
 211 #define CONFIG_SYS_INIT_RAM_SIZE        0x0f00  /* Size of used area in RAM            */
 212 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 213 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 214
 215 #endif  /* __CONFIG_H */