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[people/ms/u-boot.git] / include / configs / CATcenter.h
1 /*
2 * ueberarbeitet durch Christoph Seyfert
3 *
4 * (C) Copyright 2004-2005 DENX Software Engineering,
5 * Wolfgang Grandegger <wg@denx.de>
6 * (C) Copyright 2003
7 * DAVE Srl
8 *
9 * http://www.dave-tech.it
10 * http://www.wawnet.biz
11 * mailto:info@wawnet.biz
12 *
13 * Credits: Stefan Roese, Wolfgang Denk
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31 /*
32 * board/config.h - configuration options, board specific
33 */
34
35 #ifndef __CONFIG_H
36 #define __CONFIG_H
37
38 #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
39 #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
40 #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
41 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
42 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
43 #endif
44
45 /* Only one of the following two symbols must be defined (default is 25 MHz)
46 * CONFIG_PPCHAMELEON_CLK_25
47 * CONFIG_PPCHAMELEON_CLK_33
48 */
49 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
50 #define CONFIG_PPCHAMELEON_CLK_25
51 #endif
52
53 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54 #error "* Two external frequencies (SysClk) are defined! *"
55 #endif
56
57 #undef CONFIG_PPCHAMELEON_SMI712
58
59 /*
60 * Debug stuff
61 */
62 #undef __DEBUG_START_FROM_SRAM__
63 #define __DISABLE_MACHINE_EXCEPTION__
64
65 #ifdef __DEBUG_START_FROM_SRAM__
66 #define CFG_DUMMY_FLASH_SIZE 1024*1024*4
67 #endif
68
69 /*
70 * High Level Configuration Options
71 * (easy to change)
72 */
73
74 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
75 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
76 #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
77
78 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
79 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
80
81 #ifdef CONFIG_PPCHAMELEON_CLK_25
82 # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
83 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
84 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
85 #else
86 # error "* External frequency (SysClk) not defined! *"
87 #endif
88
89 #define CONFIG_UART1_CONSOLE 1 /* Use second UART */
90 #define CONFIG_BAUDRATE 115200
91 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
92
93 #define CONFIG_VERSION_VARIABLE 1 /* add version variable */
94 #define CONFIG_IDENT_STRING "1"
95
96 #undef CONFIG_BOOTARGS
97
98 /* Ethernet stuff */
99 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
100 #define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
101 #define CONFIG_HAS_ETH1
102 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
103
104 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
105 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
106
107
108 #undef CONFIG_EXT_PHY
109 #define CONFIG_NET_MULTI 1
110
111 #define CONFIG_MII 1 /* MII PHY management */
112 #ifndef CONFIG_EXT_PHY
113 #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
114 #define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
115 #else
116 #define CONFIG_PHY_ADDR 2 /* PHY address */
117 #endif
118 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
119
120 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
121
122
123 /*
124 * BOOTP options
125 */
126 #define CONFIG_BOOTP_BOOTFILESIZE
127 #define CONFIG_BOOTP_BOOTPATH
128 #define CONFIG_BOOTP_GATEWAY
129 #define CONFIG_BOOTP_HOSTNAME
130
131
132 /*
133 * Command line configuration.
134 */
135 #include <config_cmd_default.h>
136
137 #define CONFIG_CMD_DHCP
138 #define CONFIG_CMD_ELF
139 #define CONFIG_CMD_EEPROM
140 #define CONFIG_CMD_I2C
141 #define CONFIG_CMD_IRQ
142 #define CONFIG_CMD_JFFS2
143 #define CONFIG_CMD_MII
144 #define CONFIG_CMD_NAND
145 #define CONFIG_CMD_NFS
146 #define CONFIG_CMD_SNTP
147
148
149 #define CONFIG_MAC_PARTITION
150 #define CONFIG_DOS_PARTITION
151
152 #undef CONFIG_WATCHDOG /* watchdog disabled */
153
154 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
155 #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
156
157 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
158
159 /*
160 * Miscellaneous configurable options
161 */
162 #define CFG_LONGHELP /* undef to save memory */
163 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
164
165 #define CFG_HUSH_PARSER /* use "hush" command parser */
166 #ifdef CFG_HUSH_PARSER
167 #define CFG_PROMPT_HUSH_PS2 "> "
168 #endif
169
170 #if defined(CONFIG_CMD_KGDB)
171 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
172 #else
173 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
174 #endif
175 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
176 #define CFG_MAXARGS 16 /* max number of command args */
177 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
178
179 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
180
181 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
182
183 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
184 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
185
186 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
187 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
188 #define CFG_BASE_BAUD 691200
189
190 /* The following table includes the supported baudrates */
191 #define CFG_BAUDRATE_TABLE \
192 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
193 57600, 115200, 230400, 460800, 921600 }
194
195 #define CFG_LOAD_ADDR 0x100000 /* default load address */
196 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
197
198 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
199
200 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
201
202 /*-----------------------------------------------------------------------
203 * NAND-FLASH stuff
204 *-----------------------------------------------------------------------
205 */
206 #define CFG_NAND0_BASE 0xFF400000
207 #define CFG_NAND1_BASE 0xFF000000
208 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
209 #define NAND_BIG_DELAY_US 25
210
211 /* For CATcenter there is only NAND on the module */
212 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
213 #define SECTORSIZE 512
214 #define NAND_NO_RB
215
216 #define ADDR_COLUMN 1
217 #define ADDR_PAGE 2
218 #define ADDR_COLUMN_PAGE 3
219
220 #define NAND_ChipID_UNKNOWN 0x00
221 #define NAND_MAX_FLOORS 1
222 #define NAND_MAX_CHIPS 1
223
224 #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
225 #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
226 #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
227 #define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
228
229 #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
230 #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
231 #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
232 #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
233
234
235 #define MACRO_NAND_DISABLE_CE(nandptr) do \
236 { \
237 switch((unsigned long)nandptr) \
238 { \
239 case CFG_NAND0_BASE: \
240 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
241 break; \
242 case CFG_NAND1_BASE: \
243 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
244 break; \
245 } \
246 } while(0)
247
248 #define MACRO_NAND_ENABLE_CE(nandptr) do \
249 { \
250 switch((unsigned long)nandptr) \
251 { \
252 case CFG_NAND0_BASE: \
253 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
254 break; \
255 case CFG_NAND1_BASE: \
256 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
257 break; \
258 } \
259 } while(0)
260
261 #define MACRO_NAND_CTL_CLRALE(nandptr) do \
262 { \
263 switch((unsigned long)nandptr) \
264 { \
265 case CFG_NAND0_BASE: \
266 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
267 break; \
268 case CFG_NAND1_BASE: \
269 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
270 break; \
271 } \
272 } while(0)
273
274 #define MACRO_NAND_CTL_SETALE(nandptr) do \
275 { \
276 switch((unsigned long)nandptr) \
277 { \
278 case CFG_NAND0_BASE: \
279 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
280 break; \
281 case CFG_NAND1_BASE: \
282 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
283 break; \
284 } \
285 } while(0)
286
287 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
288 { \
289 switch((unsigned long)nandptr) \
290 { \
291 case CFG_NAND0_BASE: \
292 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
293 break; \
294 case CFG_NAND1_BASE: \
295 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
296 break; \
297 } \
298 } while(0)
299
300 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
301 switch((unsigned long)nandptr) { \
302 case CFG_NAND0_BASE: \
303 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
304 break; \
305 case CFG_NAND1_BASE: \
306 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
307 break; \
308 } \
309 } while(0)
310
311 #ifdef NAND_NO_RB
312 /* constant delay (see also tR in the datasheet) */
313 #define NAND_WAIT_READY(nand) do { \
314 udelay(12); \
315 } while (0)
316 #else
317 /* use the R/B pin */
318 /* TBD */
319 #endif
320
321 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
322 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
323 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
324 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
325
326 /*-----------------------------------------------------------------------
327 * PCI stuff
328 *-----------------------------------------------------------------------
329 */
330 #if 0 /* No PCI on CATcenter */
331 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
332 #define PCI_HOST_FORCE 1 /* configure as pci host */
333 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
334
335 #define CONFIG_PCI /* include pci support */
336 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
337 #undef CONFIG_PCI_PNP /* do pci plug-and-play */
338 /* resource configuration */
339
340 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
341
342 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
343 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
344 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
345
346 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
347 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
348 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
349 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
350 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
351 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
352 #endif /* No PCI */
353
354 /*-----------------------------------------------------------------------
355 * Start addresses for the final memory configuration
356 * (Set up by the startup code)
357 * Please note that CFG_SDRAM_BASE _must_ start at 0
358 */
359 #define CFG_SDRAM_BASE 0x00000000
360 #define CFG_FLASH_BASE 0xFFFC0000
361 #define CFG_MONITOR_BASE CFG_FLASH_BASE
362 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
363 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
364
365 /*
366 * For booting Linux, the board info and command line data
367 * have to be in the first 8 MB of memory, since this is
368 * the maximum mapped by the Linux kernel during initialization.
369 */
370 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
371 /*-----------------------------------------------------------------------
372 * FLASH organization
373 */
374 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
375 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
376
377 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
378 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
379
380 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
381 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
382 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
383 /*
384 * The following defines are added for buggy IOP480 byte interface.
385 * All other boards should use the standard values (CPCI405 etc.)
386 */
387 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
388 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
389 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
390
391 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
392
393 /*-----------------------------------------------------------------------
394 * Environment Variable setup
395 */
396 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
397 #define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
398 #define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
399 #define CFG_ENV_ADDR_REDUND 0xFFFFA000
400 #define CFG_ENV_SIZE_REDUND 0x2000
401
402 #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
403 #define CFG_NVRAM_SIZE 242 /* NVRAM size */
404
405 /*-----------------------------------------------------------------------
406 * I2C EEPROM (CAT24WC16) for environment
407 */
408 #define CONFIG_HARD_I2C /* I2c with hardware support */
409 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
410 #define CFG_I2C_SLAVE 0x7F
411
412 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
413 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
414 /* mask of address bits that overflow into the "EEPROM chip address" */
415 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
416 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
417 /* 16 byte page write mode using*/
418 /* last 4 bits of the address */
419 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
420 #define CFG_EEPROM_PAGE_WRITE_ENABLE
421
422 /*-----------------------------------------------------------------------
423 * Cache Configuration
424 */
425 #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
426 /* have only 8kB, 16kB is save here */
427 #define CFG_CACHELINE_SIZE 32 /* ... */
428 #if defined(CONFIG_CMD_KGDB)
429 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
430 #endif
431
432 /*
433 * Init Memory Controller:
434 *
435 * BR0/1 and OR0/1 (FLASH)
436 */
437
438 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
439
440 /*-----------------------------------------------------------------------
441 * External Bus Controller (EBC) Setup
442 */
443
444 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
445 #define CFG_EBC_PB0AP 0x92015480
446 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
447
448 /* Memory Bank 1 (External SRAM) initialization */
449 /* Since this must replace NOR Flash, we use the same settings for CS0 */
450 #define CFG_EBC_PB1AP 0x92015480
451 #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
452
453 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
454 #define CFG_EBC_PB2AP 0x92015480
455 #define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
456
457 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
458 #define CFG_EBC_PB3AP 0x92015480
459 #define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
460
461 #ifdef CONFIG_PPCHAMELEON_SMI712
462 /*
463 * Video console (graphic: SMI LynxEM)
464 */
465 #define CONFIG_VIDEO
466 #define CONFIG_CFB_CONSOLE
467 #define CONFIG_VIDEO_SMI_LYNXEM
468 #define CONFIG_VIDEO_LOGO
469 /*#define CONFIG_VIDEO_BMP_LOGO*/
470 #define CONFIG_CONSOLE_EXTRA_INFO
471 #define CONFIG_VGA_AS_SINGLE_DEVICE
472 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
473 #define CFG_ISA_IO 0xE8000000
474 /* see also drivers/videomodes.c */
475 #define CFG_DEFAULT_VIDEO_MODE 0x303
476 #endif
477
478 /*-----------------------------------------------------------------------
479 * FPGA stuff
480 */
481 /* FPGA internal regs */
482 #define CFG_FPGA_MODE 0x00
483 #define CFG_FPGA_STATUS 0x02
484 #define CFG_FPGA_TS 0x04
485 #define CFG_FPGA_TS_LOW 0x06
486 #define CFG_FPGA_TS_CAP0 0x10
487 #define CFG_FPGA_TS_CAP0_LOW 0x12
488 #define CFG_FPGA_TS_CAP1 0x14
489 #define CFG_FPGA_TS_CAP1_LOW 0x16
490 #define CFG_FPGA_TS_CAP2 0x18
491 #define CFG_FPGA_TS_CAP2_LOW 0x1a
492 #define CFG_FPGA_TS_CAP3 0x1c
493 #define CFG_FPGA_TS_CAP3_LOW 0x1e
494
495 /* FPGA Mode Reg */
496 #define CFG_FPGA_MODE_CF_RESET 0x0001
497 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
498 #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
499 #define CFG_FPGA_MODE_TS_CLEAR 0x2000
500
501 /* FPGA Status Reg */
502 #define CFG_FPGA_STATUS_DIP0 0x0001
503 #define CFG_FPGA_STATUS_DIP1 0x0002
504 #define CFG_FPGA_STATUS_DIP2 0x0004
505 #define CFG_FPGA_STATUS_FLASH 0x0008
506 #define CFG_FPGA_STATUS_TS_IRQ 0x1000
507
508 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
509 #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
510
511 /* FPGA program pin configuration */
512 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
513 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
514 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
515 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
516 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
517
518 /*-----------------------------------------------------------------------
519 * Definitions for initial stack pointer and data area (in data cache)
520 */
521 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
522 #define CFG_TEMP_STACK_OCM 1
523
524 /* On Chip Memory location */
525 #define CFG_OCM_DATA_ADDR 0xF8000000
526 #define CFG_OCM_DATA_SIZE 0x1000
527 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
528 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
529
530 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
531 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
532 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
533
534 /*-----------------------------------------------------------------------
535 * Definitions for GPIO setup (PPC405EP specific)
536 *
537 * GPIO0[0] - External Bus Controller BLAST output
538 * GPIO0[1-9] - Instruction trace outputs -> GPIO
539 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
540 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
541 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
542 * GPIO0[24-27] - UART0 control signal inputs/outputs
543 * GPIO0[28-29] - UART1 data signal input/output
544 * GPIO0[30] - EMAC0 input
545 * GPIO0[31] - EMAC1 reject packet as output
546 */
547 #define CFG_GPIO0_OSRH 0x40000550
548 #define CFG_GPIO0_OSRL 0x00000110
549 #define CFG_GPIO0_ISR1H 0x00000000
550 /*#define CFG_GPIO0_ISR1L 0x15555445*/
551 #define CFG_GPIO0_ISR1L 0x15555444
552 #define CFG_GPIO0_TSRH 0x00000000
553 #define CFG_GPIO0_TSRL 0x00000000
554 #define CFG_GPIO0_TCR 0xF7FF8014
555
556 /*
557 * Internal Definitions
558 *
559 * Boot Flags
560 */
561 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
562 #define BOOTFLAG_WARM 0x02 /* Software reboot */
563
564
565 #define CONFIG_NO_SERIAL_EEPROM
566
567 /*--------------------------------------------------------------------*/
568
569 #ifdef CONFIG_NO_SERIAL_EEPROM
570
571 /*
572 !-----------------------------------------------------------------------
573 ! Defines for entry options.
574 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
575 ! are plugged in the board will be utilized as non-ECC DIMMs.
576 !-----------------------------------------------------------------------
577 */
578 #undef AUTO_MEMORY_CONFIG
579 #define DIMM_READ_ADDR 0xAB
580 #define DIMM_WRITE_ADDR 0xAA
581
582 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
583 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
584 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
585 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
586 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
587 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
588 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
589 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
590 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
591 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
592
593 /* Defines for CPC0_PLLMR1 Register fields */
594 #define PLL_ACTIVE 0x80000000
595 #define CPC0_PLLMR1_SSCS 0x80000000
596 #define PLL_RESET 0x40000000
597 #define CPC0_PLLMR1_PLLR 0x40000000
598 /* Feedback multiplier */
599 #define PLL_FBKDIV 0x00F00000
600 #define CPC0_PLLMR1_FBDV 0x00F00000
601 #define PLL_FBKDIV_16 0x00000000
602 #define PLL_FBKDIV_1 0x00100000
603 #define PLL_FBKDIV_2 0x00200000
604 #define PLL_FBKDIV_3 0x00300000
605 #define PLL_FBKDIV_4 0x00400000
606 #define PLL_FBKDIV_5 0x00500000
607 #define PLL_FBKDIV_6 0x00600000
608 #define PLL_FBKDIV_7 0x00700000
609 #define PLL_FBKDIV_8 0x00800000
610 #define PLL_FBKDIV_9 0x00900000
611 #define PLL_FBKDIV_10 0x00A00000
612 #define PLL_FBKDIV_11 0x00B00000
613 #define PLL_FBKDIV_12 0x00C00000
614 #define PLL_FBKDIV_13 0x00D00000
615 #define PLL_FBKDIV_14 0x00E00000
616 #define PLL_FBKDIV_15 0x00F00000
617 /* Forward A divisor */
618 #define PLL_FWDDIVA 0x00070000
619 #define CPC0_PLLMR1_FWDVA 0x00070000
620 #define PLL_FWDDIVA_8 0x00000000
621 #define PLL_FWDDIVA_7 0x00010000
622 #define PLL_FWDDIVA_6 0x00020000
623 #define PLL_FWDDIVA_5 0x00030000
624 #define PLL_FWDDIVA_4 0x00040000
625 #define PLL_FWDDIVA_3 0x00050000
626 #define PLL_FWDDIVA_2 0x00060000
627 #define PLL_FWDDIVA_1 0x00070000
628 /* Forward B divisor */
629 #define PLL_FWDDIVB 0x00007000
630 #define CPC0_PLLMR1_FWDVB 0x00007000
631 #define PLL_FWDDIVB_8 0x00000000
632 #define PLL_FWDDIVB_7 0x00001000
633 #define PLL_FWDDIVB_6 0x00002000
634 #define PLL_FWDDIVB_5 0x00003000
635 #define PLL_FWDDIVB_4 0x00004000
636 #define PLL_FWDDIVB_3 0x00005000
637 #define PLL_FWDDIVB_2 0x00006000
638 #define PLL_FWDDIVB_1 0x00007000
639 /* PLL tune bits */
640 #define PLL_TUNE_MASK 0x000003FF
641 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
642 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
643 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
644 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
645 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
646 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
647 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
648
649 /* Defines for CPC0_PLLMR0 Register fields */
650 /* CPU divisor */
651 #define PLL_CPUDIV 0x00300000
652 #define CPC0_PLLMR0_CCDV 0x00300000
653 #define PLL_CPUDIV_1 0x00000000
654 #define PLL_CPUDIV_2 0x00100000
655 #define PLL_CPUDIV_3 0x00200000
656 #define PLL_CPUDIV_4 0x00300000
657 /* PLB divisor */
658 #define PLL_PLBDIV 0x00030000
659 #define CPC0_PLLMR0_CBDV 0x00030000
660 #define PLL_PLBDIV_1 0x00000000
661 #define PLL_PLBDIV_2 0x00010000
662 #define PLL_PLBDIV_3 0x00020000
663 #define PLL_PLBDIV_4 0x00030000
664 /* OPB divisor */
665 #define PLL_OPBDIV 0x00003000
666 #define CPC0_PLLMR0_OPDV 0x00003000
667 #define PLL_OPBDIV_1 0x00000000
668 #define PLL_OPBDIV_2 0x00001000
669 #define PLL_OPBDIV_3 0x00002000
670 #define PLL_OPBDIV_4 0x00003000
671 /* EBC divisor */
672 #define PLL_EXTBUSDIV 0x00000300
673 #define CPC0_PLLMR0_EPDV 0x00000300
674 #define PLL_EXTBUSDIV_2 0x00000000
675 #define PLL_EXTBUSDIV_3 0x00000100
676 #define PLL_EXTBUSDIV_4 0x00000200
677 #define PLL_EXTBUSDIV_5 0x00000300
678 /* MAL divisor */
679 #define PLL_MALDIV 0x00000030
680 #define CPC0_PLLMR0_MPDV 0x00000030
681 #define PLL_MALDIV_1 0x00000000
682 #define PLL_MALDIV_2 0x00000010
683 #define PLL_MALDIV_3 0x00000020
684 #define PLL_MALDIV_4 0x00000030
685 /* PCI divisor */
686 #define PLL_PCIDIV 0x00000003
687 #define CPC0_PLLMR0_PPFD 0x00000003
688 #define PLL_PCIDIV_1 0x00000000
689 #define PLL_PCIDIV_2 0x00000001
690 #define PLL_PCIDIV_3 0x00000002
691 #define PLL_PCIDIV_4 0x00000003
692
693 #ifdef CONFIG_PPCHAMELEON_CLK_25
694 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
695 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
696 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
697 PLL_MALDIV_1 | PLL_PCIDIV_4)
698 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
699 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
700 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
701
702 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
703 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
704 PLL_MALDIV_1 | PLL_PCIDIV_4)
705 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
706 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
707 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
708
709 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
710 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
711 PLL_MALDIV_1 | PLL_PCIDIV_4)
712 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
713 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
714 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
715
716 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
717 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
718 PLL_MALDIV_1 | PLL_PCIDIV_2)
719 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
720 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
721 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
722
723 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
724
725 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
726 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
727 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
728 PLL_MALDIV_1 | PLL_PCIDIV_4)
729 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
730 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
731 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
732
733 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
734 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
735 PLL_MALDIV_1 | PLL_PCIDIV_4)
736 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
737 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
738 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
739
740 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
741 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
742 PLL_MALDIV_1 | PLL_PCIDIV_4)
743 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
744 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
745 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
746
747 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
748 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
749 PLL_MALDIV_1 | PLL_PCIDIV_2)
750 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
751 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
752 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
753
754 #else
755 #error "* External frequency (SysClk) not defined! *"
756 #endif
757
758 #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
759 /* Model HI */
760 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
761 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
762 #define CFG_OPB_FREQ 55555555
763 /* Model ME */
764 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
765 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
766 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
767 #define CFG_OPB_FREQ 66666666
768 #else
769 /* Model BA (default) */
770 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
771 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
772 #define CFG_OPB_FREQ 66666666
773 #endif
774
775 #endif /* CONFIG_NO_SERIAL_EEPROM */
776
777 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
778 #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
779
780 /*
781 * JFFS2 partitions
782 *
783 */
784 /* No command line, one static partition */
785 #undef CONFIG_JFFS2_CMDLINE
786 #define CONFIG_JFFS2_DEV "nand"
787 #define CONFIG_JFFS2_PART_SIZE 0x00200000
788 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
789
790 /* mtdparts command line support
791 *
792 * Note: fake mtd_id used, no linux mtd map file
793 */
794 /*
795 #define CONFIG_JFFS2_CMDLINE
796 #define MTDIDS_DEFAULT "nand0=catcenter"
797 #define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
798 */
799
800 #endif /* __CONFIG_H */
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