include/configs/CMS700.h

   1 /*
   2  * (C) Copyright 2005
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * CMS700.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_VOM405           1       /* ...on a VOM405 board         */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFFC8000
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  28
  29 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  30
  31 #define CONFIG_BAUDRATE         9600
  32 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  33
  34 #undef  CONFIG_BOOTARGS
  35 #undef  CONFIG_BOOTCOMMAND
  36
  37 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  38
  39 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  40
  41 #define CONFIG_PPC4xx_EMAC
  42 #undef  CONFIG_HAS_ETH1
  43
  44 #define CONFIG_MII              1       /* MII PHY management           */
  45 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  46 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  47 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  48
  49 /*
  50  * BOOTP options
  51  */
  52 #define CONFIG_BOOTP_SUBNETMASK
  53 #define CONFIG_BOOTP_GATEWAY
  54 #define CONFIG_BOOTP_HOSTNAME
  55 #define CONFIG_BOOTP_BOOTPATH
  56 #define CONFIG_BOOTP_DNS
  57 #define CONFIG_BOOTP_DNS2
  58 #define CONFIG_BOOTP_SEND_HOSTNAME
  59
  60
  61 /*
  62  * Command line configuration.
  63  */
  64 #include <config_cmd_default.h>
  65
  66 #define CONFIG_CMD_DHCP
  67 #define CONFIG_CMD_BSP
  68 #define CONFIG_CMD_ELF
  69 #define CONFIG_CMD_NAND
  70 #define CONFIG_CMD_I2C
  71 #define CONFIG_CMD_DATE
  72 #define CONFIG_CMD_MII
  73 #define CONFIG_CMD_PING
  74 #define CONFIG_CMD_EEPROM
  75
  76
  77 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  78
  79 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  80
  81 #undef  CONFIG_PRAM                     /* no "protected RAM"           */
  82
  83 /*
  84  * Miscellaneous configurable options
  85  */
  86 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  87 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  88
  89 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  90
  91 #if defined(CONFIG_CMD_KGDB)
  92 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  93 #else
  94 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  95 #endif
  96 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  97 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  98 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  99
 100 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 101
 102 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 103
 104 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 105 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 106
 107 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 108 #define CONFIG_SYS_NS16550
 109 #define CONFIG_SYS_NS16550_SERIAL
 110 #define CONFIG_SYS_NS16550_REG_SIZE     1
 111 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 112
 113 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 114 #define CONFIG_SYS_BASE_BAUD        691200
 115
 116 /* The following table includes the supported baudrates */
 117 #define CONFIG_SYS_BAUDRATE_TABLE       \
 118         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 119          57600, 115200, 230400, 460800, 921600 }
 120
 121 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 122 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 123
 124 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 125
 126 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 127
 128 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 129
 130 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 131
 132 /*-----------------------------------------------------------------------
 133  * RTC stuff
 134  *-----------------------------------------------------------------------
 135  */
 136 #define CONFIG_RTC_DS1337
 137 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 138
 139 /*-----------------------------------------------------------------------
 140  * NAND-FLASH stuff
 141  *-----------------------------------------------------------------------
 142  */
 143 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 144 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 145 #define NAND_BIG_DELAY_US       25
 146
 147 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 148 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 149 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 150 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 151
 152 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 153 #define CONFIG_SYS_NAND_QUIET          1
 154
 155 /*
 156  * For booting Linux, the board info and command line data
 157  * have to be in the first 8 MB of memory, since this is
 158  * the maximum mapped by the Linux kernel during initialization.
 159  */
 160 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 161 /*-----------------------------------------------------------------------
 162  * FLASH organization
 163  */
 164 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 165
 166 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 167 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 168
 169 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 170 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 171
 172 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 173 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 174 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 175 /*
 176  * The following defines are added for buggy IOP480 byte interface.
 177  * All other boards should use the standard values (CPCI405 etc.)
 178  */
 179 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 180 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 181 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 182
 183 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 184
 185 /*-----------------------------------------------------------------------
 186  * Start addresses for the final memory configuration
 187  * (Set up by the startup code)
 188  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 189  */
 190 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 191 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 192 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 193 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 194 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 195
 196 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 197 # define CONFIG_SYS_RAMBOOT             1
 198 #else
 199 # undef CONFIG_SYS_RAMBOOT
 200 #endif
 201
 202 /*-----------------------------------------------------------------------
 203  * Environment Variable setup
 204  */
 205 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 206 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 207 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 208                                    /* total size of a CAT24WC16 is 2048 bytes */
 209
 210 /*-----------------------------------------------------------------------
 211  * I2C EEPROM (CAT24WC16) for environment
 212  */
 213 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 214 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 215 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 216 #define CONFIG_SYS_I2C_SLAVE            0x7F
 217
 218 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 219 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 220 /* mask of address bits that overflow into the "EEPROM chip address"    */
 221 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 223                                         /* 16 byte page write mode using*/
 224                                         /* last 4 bits of the address   */
 225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 226
 227 #define CONFIG_SYS_EEPROM_WREN         1
 228
 229 /*-----------------------------------------------------------------------
 230  * External Bus Controller (EBC) Setup
 231  */
 232 #define CONFIG_SYS_PLD_BASE            0xf0000000
 233 #define CONFIG_SYS_NAND_BASE            0xF4000000  /* NAND FLASH Base Address          */
 234
 235 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 236 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 237 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 238
 239 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 240 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 241 #define CONFIG_SYS_EBC_PB1CR            0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 242
 243 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 244 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 245 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 246
 247 /*-----------------------------------------------------------------------
 248  * FPGA stuff
 249  */
 250 #define CONFIG_SYS_XSVF_DEFAULT_ADDR    0xfffc0000
 251
 252 /* FPGA program pin configuration */
 253 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* JTAG TMS pin (ppc output)     */
 254 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* JTAG TCK pin (ppc output)     */
 255 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 256 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* unused (ppc input)            */
 257 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 258
 259 /*-----------------------------------------------------------------------
 260  * Definitions for initial stack pointer and data area (in data cache)
 261  */
 262 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 263 #define CONFIG_SYS_TEMP_STACK_OCM         1
 264
 265 /* On Chip Memory location */
 266 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 267 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 268 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 269 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 270
 271 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 272 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 273
 274 /*-----------------------------------------------------------------------
 275  * Definitions for GPIO setup (PPC405EP specific)
 276  *
 277  * GPIO0[0]     - External Bus Controller BLAST output
 278  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 279  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 280  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 281  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 282  * GPIO0[24-27] - UART0 control signal inputs/outputs
 283  * GPIO0[28-29] - UART1 data signal input/output
 284  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 285  */
 286 /* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 287 /* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 288 /* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 289 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 290 #define CONFIG_SYS_GPIO0_OSRL           0x40000500  /*  0 ... 15 */
 291 #define CONFIG_SYS_GPIO0_OSRH           0x00000110  /* 16 ... 31 */
 292 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000  /*  0 ... 15 */
 293 #define CONFIG_SYS_GPIO0_ISR1H          0x14000045  /* 16 ... 31 */
 294 #define CONFIG_SYS_GPIO0_TSRL           0x00000000  /*  0 ... 15 */
 295 #define CONFIG_SYS_GPIO0_TSRH           0x00000000  /* 16 ... 31 */
 296 #define CONFIG_SYS_GPIO0_TCR            0xF7FE0014  /*  0 ... 31 */
 297
 298 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 8)    /* GPIO8 */
 299 #define CONFIG_SYS_PLD_RESET            (0x80000000 >> 12)   /* GPIO12 */
 300
 301 /*
 302  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 303  * This value will be set if iic boot eprom is disabled.
 304  */
 305 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 306 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 307
 308 #endif  /* __CONFIG_H */