include/configs/CMS700.h

   1 /*
   2  * (C) Copyright 2005
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * CMS700.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_VOM405           1       /* ...on a VOM405 board         */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  41 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  44
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  47
  48 #undef  CONFIG_BOOTARGS
  49 #undef  CONFIG_BOOTCOMMAND
  50
  51 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  52
  53 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  54
  55 #define CONFIG_PPC4xx_EMAC
  56 #define CONFIG_NET_MULTI        1
  57 #undef  CONFIG_HAS_ETH1
  58
  59 #define CONFIG_MII              1       /* MII PHY management           */
  60 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  61 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  62 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  63
  64 /*
  65  * BOOTP options
  66  */
  67 #define CONFIG_BOOTP_SUBNETMASK
  68 #define CONFIG_BOOTP_GATEWAY
  69 #define CONFIG_BOOTP_HOSTNAME
  70 #define CONFIG_BOOTP_BOOTPATH
  71 #define CONFIG_BOOTP_DNS
  72 #define CONFIG_BOOTP_DNS2
  73 #define CONFIG_BOOTP_SEND_HOSTNAME
  74
  75
  76 /*
  77  * Command line configuration.
  78  */
  79 #include <config_cmd_default.h>
  80
  81 #define CONFIG_CMD_DHCP
  82 #define CONFIG_CMD_BSP
  83 #define CONFIG_CMD_ELF
  84 #define CONFIG_CMD_NAND
  85 #define CONFIG_CMD_I2C
  86 #define CONFIG_CMD_DATE
  87 #define CONFIG_CMD_MII
  88 #define CONFIG_CMD_PING
  89 #define CONFIG_CMD_EEPROM
  90
  91
  92 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  93
  94 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  95
  96 #undef  CONFIG_PRAM                     /* no "protected RAM"           */
  97
  98 /*
  99  * Miscellaneous configurable options
 100  */
 101 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 102 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 103
 104 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 105 #ifdef  CONFIG_SYS_HUSH_PARSER
 106 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 107 #endif
 108
 109 #if defined(CONFIG_CMD_KGDB)
 110 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 111 #else
 112 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 113 #endif
 114 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 115 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 116 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 117
 118 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 119
 120 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 121
 122 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 123 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 124
 125 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 126 #define CONFIG_SYS_BASE_BAUD        691200
 127 #define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 128
 129 /* The following table includes the supported baudrates */
 130 #define CONFIG_SYS_BAUDRATE_TABLE       \
 131         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 132          57600, 115200, 230400, 460800, 921600 }
 133
 134 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 135 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 136
 137 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 138
 139 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 140
 141 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 142
 143 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 144
 145 /*-----------------------------------------------------------------------
 146  * RTC stuff
 147  *-----------------------------------------------------------------------
 148  */
 149 #define CONFIG_RTC_DS1337
 150 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 151
 152 /*-----------------------------------------------------------------------
 153  * NAND-FLASH stuff
 154  *-----------------------------------------------------------------------
 155  */
 156 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 157 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 158 #define NAND_BIG_DELAY_US       25
 159
 160 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 161 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 162 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 163 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 164
 165 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 166 #define CONFIG_SYS_NAND_QUIET          1
 167
 168 /*
 169  * For booting Linux, the board info and command line data
 170  * have to be in the first 8 MB of memory, since this is
 171  * the maximum mapped by the Linux kernel during initialization.
 172  */
 173 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 174 /*-----------------------------------------------------------------------
 175  * FLASH organization
 176  */
 177 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 178
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 180 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 181
 182 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 183 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 184
 185 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 186 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 187 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 188 /*
 189  * The following defines are added for buggy IOP480 byte interface.
 190  * All other boards should use the standard values (CPCI405 etc.)
 191  */
 192 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 193 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 194 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 195
 196 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 197
 198 /*-----------------------------------------------------------------------
 199  * Start addresses for the final memory configuration
 200  * (Set up by the startup code)
 201  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 202  */
 203 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 204 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 205 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE
 206 #define CONFIG_SYS_MONITOR_LEN          (~(TEXT_BASE) + 1)
 207 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 208
 209 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 210 # define CONFIG_SYS_RAMBOOT             1
 211 #else
 212 # undef CONFIG_SYS_RAMBOOT
 213 #endif
 214
 215 /*-----------------------------------------------------------------------
 216  * Environment Variable setup
 217  */
 218 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 219 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 220 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 221                                    /* total size of a CAT24WC16 is 2048 bytes */
 222
 223 /*-----------------------------------------------------------------------
 224  * I2C EEPROM (CAT24WC16) for environment
 225  */
 226 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 227 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 228 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 229 #define CONFIG_SYS_I2C_SLAVE            0x7F
 230
 231 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 233 /* mask of address bits that overflow into the "EEPROM chip address"    */
 234 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 236                                         /* 16 byte page write mode using*/
 237                                         /* last 4 bits of the address   */
 238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 239
 240 #define CONFIG_SYS_EEPROM_WREN         1
 241
 242 /*-----------------------------------------------------------------------
 243  * External Bus Controller (EBC) Setup
 244  */
 245 #define CONFIG_SYS_PLD_BASE            0xf0000000
 246 #define CONFIG_SYS_NAND_BASE            0xF4000000  /* NAND FLASH Base Address          */
 247
 248 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 249 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 250 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 251
 252 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 253 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 254 #define CONFIG_SYS_EBC_PB1CR            0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 255
 256 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 257 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 258 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 259
 260 /*-----------------------------------------------------------------------
 261  * FPGA stuff
 262  */
 263 #define CONFIG_SYS_XSVF_DEFAULT_ADDR    0xfffc0000
 264
 265 /* FPGA program pin configuration */
 266 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* JTAG TMS pin (ppc output)     */
 267 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* JTAG TCK pin (ppc output)     */
 268 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 269 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* unused (ppc input)            */
 270 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 271
 272 /*-----------------------------------------------------------------------
 273  * Definitions for initial stack pointer and data area (in data cache)
 274  */
 275 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 276 #define CONFIG_SYS_TEMP_STACK_OCM         1
 277
 278 /* On Chip Memory location */
 279 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 280 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 281 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 282 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
 283
 284 #define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 285 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 286 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 287
 288 /*-----------------------------------------------------------------------
 289  * Definitions for GPIO setup (PPC405EP specific)
 290  *
 291  * GPIO0[0]     - External Bus Controller BLAST output
 292  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 293  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 294  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 295  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 296  * GPIO0[24-27] - UART0 control signal inputs/outputs
 297  * GPIO0[28-29] - UART1 data signal input/output
 298  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 299  */
 300 /* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 301 /* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 302 /* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 303 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 304 #define CONFIG_SYS_GPIO0_OSRH           0x40000500  /*  0 ... 15 */
 305 #define CONFIG_SYS_GPIO0_OSRL           0x00000110  /* 16 ... 31 */
 306 #define CONFIG_SYS_GPIO0_ISR1H          0x00000000  /*  0 ... 15 */
 307 #define CONFIG_SYS_GPIO0_ISR1L          0x14000045  /* 16 ... 31 */
 308 #define CONFIG_SYS_GPIO0_TSRH           0x00000000  /*  0 ... 15 */
 309 #define CONFIG_SYS_GPIO0_TSRL           0x00000000  /* 16 ... 31 */
 310 #define CONFIG_SYS_GPIO0_TCR            0xF7FE0014  /*  0 ... 31 */
 311
 312 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 8)    /* GPIO8 */
 313 #define CONFIG_SYS_PLD_RESET            (0x80000000 >> 12)   /* GPIO12 */
 314
 315 /*
 316  * Internal Definitions
 317  *
 318  * Boot Flags
 319  */
 320 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 321 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 322
 323 /*
 324  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 325  * This value will be set if iic boot eprom is disabled.
 326  */
 327 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 328 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 329
 330 #endif  /* __CONFIG_H */