include/configs/CPC45.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  *
  26  * Configuration settings for the CPC45 board.
  27  *
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 /*
  33  * board/config.h - configuration options, board specific
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_MPC824X          1
  45 #define CONFIG_MPC8245          1
  46 #define CONFIG_CPC45            1
  47
  48 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  49
  50 #define CONFIG_CONS_INDEX       1
  51 #define CONFIG_BAUDRATE         9600
  52 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  53
  54 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  55
  56 #define CONFIG_BOOTDELAY        5
  57
  58 /*
  59  * BOOTP options
  60  */
  61 #define CONFIG_BOOTP_SUBNETMASK
  62 #define CONFIG_BOOTP_GATEWAY
  63 #define CONFIG_BOOTP_HOSTNAME
  64 #define CONFIG_BOOTP_BOOTPATH
  65
  66 #define CONFIG_BOOTP_BOOTFILESIZE
  67
  68
  69 /*
  70  * Command line configuration.
  71  */
  72 #include <config_cmd_default.h>
  73
  74 #define CONFIG_CMD_BEDBUG
  75 #define CONFIG_CMD_DATE
  76 #define CONFIG_CMD_DHCP
  77 #define CONFIG_CMD_EEPROM
  78 #define CONFIG_CMD_EXT2
  79 #define CONFIG_CMD_FAT
  80 #define CONFIG_CMD_FLASH
  81 #define CONFIG_CMD_I2C
  82 #define CONFIG_CMD_IDE
  83 #define CONFIG_CMD_NFS
  84 #define CONFIG_CMD_PCI
  85 #define CONFIG_CMD_PING
  86 #define CONFIG_CMD_SDRAM
  87 #define CONFIG_CMD_SNTP
  88
  89
  90 /*
  91  * Miscellaneous configurable options
  92  */
  93 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  94 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  95 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  96
  97 #if 1
  98 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
  99 #endif
 100 #ifdef  CONFIG_SYS_HUSH_PARSER
 101 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 102 #endif
 103
 104 /* Print Buffer Size
 105  */
 106 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 107
 108 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 109 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 110 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
 111
 112 /*-----------------------------------------------------------------------
 113  * Start addresses for the final memory configuration
 114  * (Set up by the startup code)
 115  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 116  */
 117
 118 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 119
 120 #if defined(CONFIG_BOOT_ROM)
 121 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 122 #else
 123 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 124 #endif
 125
 126 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 127
 128 #define CONFIG_SYS_EUMB_ADDR            0xFCE00000
 129
 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 131
 132 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 133 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 134
 135 #define CONFIG_SYS_MEMTEST_START        0x00004000      /* memtest works on             */
 136 #define CONFIG_SYS_MEMTEST_END          0x02000000      /* 0 ... 32 MB in DRAM          */
 137
 138 /* Maximum amount of RAM.
 139  */
 140 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
 141
 142
 143 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 144 #undef CONFIG_SYS_RAMBOOT
 145 #else
 146 #define CONFIG_SYS_RAMBOOT
 147 #endif
 148
 149
 150 /*-----------------------------------------------------------------------
 151  * Definitions for initial stack pointer and data area
 152  */
 153
 154 /* Size in bytes reserved for initial data
 155  */
 156 #define CONFIG_SYS_GBL_DATA_SIZE        128
 157
 158 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 159 #define CONFIG_SYS_INIT_RAM_END 0x1000
 160 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 161
 162 /*
 163  * NS16550 Configuration
 164  */
 165 #define CONFIG_SYS_NS16550
 166 #define CONFIG_SYS_NS16550_SERIAL
 167
 168 #define CONFIG_SYS_NS16550_REG_SIZE     1
 169
 170 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 171
 172 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 173 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
 174 #define DUART_DCR               (CONFIG_SYS_EUMB_ADDR + 0x4511)
 175
 176 /*
 177  * I2C configuration
 178  */
 179 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 180
 181 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 182 #define CONFIG_SYS_I2C_SLAVE            0x7F
 183
 184 /*
 185  * RTC configuration
 186  */
 187 #define CONFIG_RTC_PCF8563
 188 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 189
 190 /*
 191  * EEPROM configuration
 192  */
 193 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 194 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 195 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 196 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 197 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 198
 199 /*
 200  * Low Level Configuration Settings
 201  * (address mappings, register initial values, etc.)
 202  * You should know what you are doing if you make changes here.
 203  * For the detail description refer to the MPC8240 user's manual.
 204  */
 205
 206 #define CONFIG_SYS_CLK_FREQ     33000000
 207 #define CONFIG_SYS_HZ                   1000
 208
 209
 210 /* Bit-field values for MCCR1.
 211  */
 212 #define CONFIG_SYS_ROMNAL               0
 213 #define CONFIG_SYS_ROMFAL               8
 214
 215 #define CONFIG_SYS_BANK0_ROW            0       /* SDRAM bank 7-0 row address */
 216 #define CONFIG_SYS_BANK1_ROW            0
 217 #define CONFIG_SYS_BANK2_ROW            0
 218 #define CONFIG_SYS_BANK3_ROW            0
 219 #define CONFIG_SYS_BANK4_ROW            0
 220 #define CONFIG_SYS_BANK5_ROW            0
 221 #define CONFIG_SYS_BANK6_ROW            0
 222 #define CONFIG_SYS_BANK7_ROW            0
 223
 224 /* Bit-field values for MCCR2.
 225  */
 226
 227 #define CONFIG_SYS_REFINT               0x2ec
 228
 229 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 230  */
 231 #define CONFIG_SYS_BSTOPRE              160
 232
 233 /* Bit-field values for MCCR3.
 234  */
 235 #define CONFIG_SYS_REFREC               2       /* Refresh to activate interval         */
 236 #define CONFIG_SYS_RDLAT                0       /* Data latancy from read command       */
 237
 238 /* Bit-field values for MCCR4.
 239  */
 240 #define CONFIG_SYS_PRETOACT             2       /* Precharge to activate interval       */
 241 #define CONFIG_SYS_ACTTOPRE             5       /* Activate to Precharge interval       */
 242 #define CONFIG_SYS_SDMODE_CAS_LAT       2       /* SDMODE CAS latancy                   */
 243 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE wrap type                     */
 244 #define CONFIG_SYS_SDMODE_BURSTLEN      2       /* SDMODE Burst length                  */
 245 #define CONFIG_SYS_ACTORW               2
 246 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 247 #define CONFIG_SYS_EXTROM               0
 248 #define CONFIG_SYS_REGDIMM              0
 249
 250 /* Memory bank settings.
 251  * Only bits 20-29 are actually used from these vales to set the
 252  * start/end addresses. The upper two bits will always be 0, and the lower
 253  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 254  * address. Refer to the MPC8240 book.
 255  */
 256
 257 #define CONFIG_SYS_BANK0_START          0x00000000
 258 #define CONFIG_SYS_BANK0_END            (CONFIG_SYS_MAX_RAM_SIZE - 1)
 259 #define CONFIG_SYS_BANK0_ENABLE 1
 260 #define CONFIG_SYS_BANK1_START          0x3ff00000
 261 #define CONFIG_SYS_BANK1_END            0x3fffffff
 262 #define CONFIG_SYS_BANK1_ENABLE 0
 263 #define CONFIG_SYS_BANK2_START          0x3ff00000
 264 #define CONFIG_SYS_BANK2_END            0x3fffffff
 265 #define CONFIG_SYS_BANK2_ENABLE 0
 266 #define CONFIG_SYS_BANK3_START          0x3ff00000
 267 #define CONFIG_SYS_BANK3_END            0x3fffffff
 268 #define CONFIG_SYS_BANK3_ENABLE 0
 269 #define CONFIG_SYS_BANK4_START          0x3ff00000
 270 #define CONFIG_SYS_BANK4_END            0x3fffffff
 271 #define CONFIG_SYS_BANK4_ENABLE 0
 272 #define CONFIG_SYS_BANK5_START          0x3ff00000
 273 #define CONFIG_SYS_BANK5_END            0x3fffffff
 274 #define CONFIG_SYS_BANK5_ENABLE 0
 275 #define CONFIG_SYS_BANK6_START          0x3ff00000
 276 #define CONFIG_SYS_BANK6_END            0x3fffffff
 277 #define CONFIG_SYS_BANK6_ENABLE 0
 278 #define CONFIG_SYS_BANK7_START          0x3ff00000
 279 #define CONFIG_SYS_BANK7_END            0x3fffffff
 280 #define CONFIG_SYS_BANK7_ENABLE 0
 281
 282 #define CONFIG_SYS_ODCR         0xff
 283 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 284                                         /* currently accessed page in memory    */
 285                                         /* see 8240 book for details            */
 286
 287 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 288 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 289
 290 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 291 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 292
 293 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 294 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 295
 296 #define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 297 #define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
 298
 299 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 300 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 301 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 302 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 303 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 304 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 305 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 306 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 307
 308 /*
 309  * For booting Linux, the board info and command line data
 310  * have to be in the first 8 MB of memory, since this is
 311  * the maximum mapped by the Linux kernel during initialization.
 312  */
 313 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 314
 315 /*-----------------------------------------------------------------------
 316  * FLASH organization
 317  */
 318 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* Max number of flash banks            */
 319 #define CONFIG_SYS_MAX_FLASH_SECT       39      /* Max number of sectors in one bank    */
 320 #define INTEL_ID_28F160F3T      0x88F388F3      /*  16M = 1M x 16 top boot sector       */
 321 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 322 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 323
 324         /* Warining: environment is not EMBEDDED in the ppcboot code.
 325          * It's stored in flash separately.
 326          */
 327 #define CONFIG_ENV_IS_IN_FLASH      1
 328
 329 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x7F8000)
 330 #define CONFIG_ENV_SIZE         0x4000  /* Size of the Environment              */
 331 #define CONFIG_ENV_OFFSET               0       /* starting right at the beginning      */
 332 #define CONFIG_ENV_SECT_SIZE    0x8000 /* Size of the Environment Sector        */
 333
 334 /*-----------------------------------------------------------------------
 335  * Cache Configuration
 336  */
 337 #define CONFIG_SYS_CACHELINE_SIZE       32
 338 #if defined(CONFIG_CMD_KGDB)
 339 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 340 #endif
 341
 342 /*----------------------------------------------------------------------*/
 343 /* CPC45 Memory Map                                                     */
 344 /*----------------------------------------------------------------------*/
 345 #define SRAM_BASE       0x80000000      /* SRAM base address            */
 346 #define SRAM_END        0x801FFFFF
 347 #define ST16552_A_BASE  0x80200000      /* ST16552 channel A            */
 348 #define ST16552_B_BASE  0x80400000      /* ST16552 channel A            */
 349 #define BCSR_BASE       0x80600000      /* board control / status registers */
 350 #define DISPLAY_BASE    0x80600040      /* DISPLAY base                 */
 351 #define PCMCIA_MEM_BASE 0x83000000      /* PCMCIA memory window base    */
 352 #define PCMCIA_IO_BASE  0xFE000000      /* PCMCIA IO window base        */
 353
 354 #define CONFIG_SYS_SRAM_BASE    SRAM_BASE
 355 #define CONFIG_SYS_SRAM_SIZE    (SRAM_END - SRAM_BASE + 1)
 356
 357 /*---------------------------------------------------------------------*/
 358 /* CPC45 Control/Status Registers                                      */
 359 /*---------------------------------------------------------------------*/
 360 #define IRQ_ENA_1               *((volatile uchar*)(BCSR_BASE + 0x00))
 361 #define IRQ_STAT_1              *((volatile uchar*)(BCSR_BASE + 0x01))
 362 #define IRQ_ENA_2               *((volatile uchar*)(BCSR_BASE + 0x02))
 363 #define IRQ_STAT_2              *((volatile uchar*)(BCSR_BASE + 0x03))
 364 #define BOARD_CTRL              *((volatile uchar*)(BCSR_BASE + 0x04))
 365 #define BOARD_STAT              *((volatile uchar*)(BCSR_BASE + 0x05))
 366 #define WDG_START               *((volatile uchar*)(BCSR_BASE + 0x06))
 367 #define WDG_PRESTOP             *((volatile uchar*)(BCSR_BASE + 0x06))
 368 #define WDG_STOP                *((volatile uchar*)(BCSR_BASE + 0x06))
 369 #define BOARD_REV               *((volatile uchar*)(BCSR_BASE + 0x07))
 370
 371 /* IRQ_ENA_1 bit definitions */
 372 #define I_ENA_1_IERA    0x80            /* INTA enable                  */
 373 #define I_ENA_1_IERB    0x40            /* INTB enable                  */
 374 #define I_ENA_1_IERC    0x20            /* INTC enable                  */
 375 #define I_ENA_1_IERD    0x10            /* INTD enable                  */
 376
 377 /* IRQ_STAT_1 bit definitions */
 378 #define I_STAT_1_INTA   0x80            /* INTA status                  */
 379 #define I_STAT_1_INTB   0x40            /* INTB status                  */
 380 #define I_STAT_1_INTC   0x20            /* INTC status                  */
 381 #define I_STAT_1_INTD   0x10            /* INTD status                  */
 382
 383 /* IRQ_ENA_2 bit definitions */
 384 #define I_ENA_2_IEAB    0x80            /* ABORT IRQ enable             */
 385 #define I_ENA_2_IEK1    0x40            /* KEY1 IRQ enable              */
 386 #define I_ENA_2_IEK2    0x20            /* KEY2 IRQ enable              */
 387 #define I_ENA_2_IERT    0x10            /* RTC IRQ enable               */
 388 #define I_ENA_2_IESM    0x08            /* LM81 IRQ enable              */
 389 #define I_ENA_2_IEDG    0x04            /* DEGENERATING IRQ enable      */
 390 #define I_ENA_2_IES2    0x02            /* ST16552/B IRQ enable         */
 391 #define I_ENA_2_IES1    0x01            /* ST16552/A IRQ enable         */
 392
 393 /* IRQ_STAT_2 bit definitions */
 394 #define I_STAT_2_ABO    0x80            /* ABORT IRQ status             */
 395 #define I_STAT_2_KY1    0x40            /* KEY1 IRQ status              */
 396 #define I_STAT_2_KY2    0x20            /* KEY2 IRQ status              */
 397 #define I_STAT_2_RTC    0x10            /* RTC IRQ status               */
 398 #define I_STAT_2_SMN    0x08            /* LM81 IRQ status              */
 399 #define I_STAT_2_DEG    0x04            /* DEGENERATING IRQ status      */
 400 #define I_STAT_2_SIO2   0x02            /* ST16552/B IRQ status         */
 401 #define I_STAT_2_SIO1   0x01            /* ST16552/A IRQ status         */
 402
 403 /* BOARD_CTRL bit definitions */
 404 #define USER_LEDS               2                       /* 2 user LEDs  */
 405
 406 #if (USER_LEDS == 4)
 407 #define B_CTRL_WRSE             0x80
 408 #define B_CTRL_KRSE             0x40
 409 #define B_CTRL_FWRE             0x20            /* Flash write enable           */
 410 #define B_CTRL_FWPT             0x10            /* Flash write protect          */
 411 #define B_CTRL_LED3             0x08            /* LED 3 control                */
 412 #define B_CTRL_LED2             0x04            /* LED 2 control                */
 413 #define B_CTRL_LED1             0x02            /* LED 1 control                */
 414 #define B_CTRL_LED0             0x01            /* LED 0 control                */
 415 #else
 416 #define B_CTRL_WRSE             0x80
 417 #define B_CTRL_KRSE             0x40
 418 #define B_CTRL_FWRE_1           0x20            /* Flash write enable           */
 419 #define B_CTRL_FWPT_1           0x10            /* Flash write protect          */
 420 #define B_CTRL_LED1             0x08            /* LED 1 control                */
 421 #define B_CTRL_LED0             0x04            /* LED 0 control                */
 422 #define B_CTRL_FWRE_0           0x02            /* Flash write enable           */
 423 #define B_CTRL_FWPT_0           0x01            /* Flash write protect          */
 424 #endif
 425
 426 /* BOARD_STAT bit definitions */
 427 #define B_STAT_WDGE             0x80
 428 #define B_STAT_WDGS             0x40
 429 #define B_STAT_WRST             0x20
 430 #define B_STAT_KRST             0x10
 431 #define B_STAT_CSW3             0x08            /* sitch bit 3 status           */
 432 #define B_STAT_CSW2             0x04            /* sitch bit 2 status           */
 433 #define B_STAT_CSW1             0x02            /* sitch bit 1 status           */
 434 #define B_STAT_CSW0             0x01            /* sitch bit 0 status           */
 435
 436 /*---------------------------------------------------------------------*/
 437 /* Display addresses                                                   */
 438 /*---------------------------------------------------------------------*/
 439 #define DISP_UDC_RAM    (DISPLAY_BASE + 0x08)   /* UDC RAM             */
 440 #define DISP_CHR_RAM    (DISPLAY_BASE + 0x18)   /* character Ram       */
 441 #define DISP_FLASH      (DISPLAY_BASE + 0x20)   /* Flash Ram           */
 442
 443 #define DISP_UDC_ADR    *((volatile uchar*)(DISPLAY_BASE + 0x00))       /* UDC Address Reg.    */
 444 #define DISP_CWORD      *((volatile uchar*)(DISPLAY_BASE + 0x10))       /* Control Word Reg.   */
 445
 446 #define DISP_DIG0       *((volatile uchar*)(DISP_CHR_RAM + 0x00))       /* Digit 0 address     */
 447 #define DISP_DIG1       *((volatile uchar*)(DISP_CHR_RAM + 0x01))       /* Digit 0 address     */
 448 #define DISP_DIG2       *((volatile uchar*)(DISP_CHR_RAM + 0x02))       /* Digit 0 address     */
 449 #define DISP_DIG3       *((volatile uchar*)(DISP_CHR_RAM + 0x03))       /* Digit 0 address     */
 450 #define DISP_DIG4       *((volatile uchar*)(DISP_CHR_RAM + 0x04))       /* Digit 0 address     */
 451 #define DISP_DIG5       *((volatile uchar*)(DISP_CHR_RAM + 0x05))       /* Digit 0 address     */
 452 #define DISP_DIG6       *((volatile uchar*)(DISP_CHR_RAM + 0x06))       /* Digit 0 address     */
 453 #define DISP_DIG7       *((volatile uchar*)(DISP_CHR_RAM + 0x07))       /* Digit 0 address     */
 454
 455
 456 /*-----------------------------------------------------------------------
 457  * PCI stuff
 458  *-----------------------------------------------------------------------
 459  */
 460 #define CONFIG_PCI                      /* include pci support                  */
 461 #define CONFIG_SYS_EARLY_PCI_INIT
 462 #undef  CONFIG_PCI_PNP
 463 #undef  CONFIG_PCI_SCAN_SHOW
 464
 465 #define CONFIG_NET_MULTI                /* Multi ethernet cards support         */
 466
 467 #define CONFIG_EEPRO100
 468 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
 469
 470 #define PCI_ENET0_IOADDR        0x82000000
 471 #define PCI_ENET0_MEMADDR       0x82000000
 472 #define PCI_PLX9030_IOADDR      0x82100000
 473 #define PCI_PLX9030_MEMADDR     0x82100000
 474
 475 /*-----------------------------------------------------------------------
 476  * PCMCIA stuff
 477  *-----------------------------------------------------------------------
 478  */
 479
 480 #define CONFIG_I82365
 481
 482 #define CONFIG_SYS_PCMCIA_MEM_ADDR      PCMCIA_MEM_BASE
 483 #define CONFIG_SYS_PCMCIA_MEM_SIZE      0x1000
 484
 485 #define CONFIG_PCMCIA_SLOT_A
 486
 487 /*-----------------------------------------------------------------------
 488  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 489  *-----------------------------------------------------------------------
 490  */
 491
 492 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 493
 494 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 495 #undef  CONFIG_IDE_RESET                /* reset for IDE not supported  */
 496 #define CONFIG_IDE_LED                  /* LED   for IDE is  supported  */
 497
 498 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 499 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 500
 501 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 502
 503 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 504
 505 #define CONFIG_SYS_ATA_DATA_OFFSET      CONFIG_SYS_PCMCIA_MEM_SIZE
 506
 507 /* Offset for normal register accesses  */
 508 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 509
 510 /* Offset for alternate registers       */
 511 #define CONFIG_SYS_ATA_ALT_OFFSET       (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
 512
 513 #define CONFIG_DOS_PARTITION
 514
 515 #endif  /* __CONFIG_H */