include/configs/CPC45.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  *
  26  * Configuration settings for the CPC45 board.
  27  *
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 /*
  33  * board/config.h - configuration options, board specific
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_MPC824X          1
  45 #define CONFIG_MPC8245          1
  46 #define CONFIG_CPC45            1
  47
  48 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  49
  50 #define CONFIG_CONS_INDEX       1
  51 #define CONFIG_BAUDRATE         9600
  52
  53 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  54
  55 #define CONFIG_BOOTDELAY        5
  56
  57 /*
  58  * BOOTP options
  59  */
  60 #define CONFIG_BOOTP_SUBNETMASK
  61 #define CONFIG_BOOTP_GATEWAY
  62 #define CONFIG_BOOTP_HOSTNAME
  63 #define CONFIG_BOOTP_BOOTPATH
  64
  65 #define CONFIG_BOOTP_BOOTFILESIZE
  66
  67
  68 /*
  69  * Command line configuration.
  70  */
  71 #include <config_cmd_default.h>
  72
  73 #define CONFIG_CMD_BEDBUG
  74 #define CONFIG_CMD_DATE
  75 #define CONFIG_CMD_DHCP
  76 #define CONFIG_CMD_EEPROM
  77 #define CONFIG_CMD_EXT2
  78 #define CONFIG_CMD_FAT
  79 #define CONFIG_CMD_FLASH
  80 #define CONFIG_CMD_I2C
  81 #define CONFIG_CMD_IDE
  82 #define CONFIG_CMD_NFS
  83 #define CONFIG_CMD_PCI
  84 #define CONFIG_CMD_PING
  85 #define CONFIG_CMD_SDRAM
  86 #define CONFIG_CMD_SNTP
  87
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  93 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  94 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  95
  96 #if 1
  97 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
  98 #endif
  99
 100 /* Print Buffer Size
 101  */
 102 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 103
 104 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 105 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 106 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
 107
 108 /*-----------------------------------------------------------------------
 109  * Start addresses for the final memory configuration
 110  * (Set up by the startup code)
 111  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 112  */
 113
 114 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 115
 116 #if defined(CONFIG_BOOT_ROM)
 117 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 118 #else
 119 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 120 #endif
 121
 122 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 123
 124 #define CONFIG_SYS_EUMB_ADDR            0xFCE00000
 125
 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 127
 128 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 129 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 130
 131 #define CONFIG_SYS_MEMTEST_START        0x00004000      /* memtest works on             */
 132 #define CONFIG_SYS_MEMTEST_END          0x02000000      /* 0 ... 32 MB in DRAM          */
 133
 134 /* Maximum amount of RAM.
 135  */
 136 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
 137
 138
 139 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 140 #undef CONFIG_SYS_RAMBOOT
 141 #else
 142 #define CONFIG_SYS_RAMBOOT
 143 #endif
 144
 145
 146 /*-----------------------------------------------------------------------
 147  * Definitions for initial stack pointer and data area
 148  */
 149
 150 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 151 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 152 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 153
 154 /*
 155  * NS16550 Configuration
 156  */
 157 #define CONFIG_SYS_NS16550
 158 #define CONFIG_SYS_NS16550_SERIAL
 159
 160 #define CONFIG_SYS_NS16550_REG_SIZE     1
 161
 162 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 163
 164 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 165 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
 166 #define DUART_DCR               (CONFIG_SYS_EUMB_ADDR + 0x4511)
 167
 168 /*
 169  * I2C configuration
 170  */
 171 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 172
 173 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 174 #define CONFIG_SYS_I2C_SLAVE            0x7F
 175
 176 /*
 177  * RTC configuration
 178  */
 179 #define CONFIG_RTC_PCF8563
 180 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 181
 182 /*
 183  * EEPROM configuration
 184  */
 185 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 186 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 187 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 188 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 189 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 190
 191 /*
 192  * Low Level Configuration Settings
 193  * (address mappings, register initial values, etc.)
 194  * You should know what you are doing if you make changes here.
 195  * For the detail description refer to the MPC8240 user's manual.
 196  */
 197
 198 #define CONFIG_SYS_CLK_FREQ     33000000
 199 #define CONFIG_SYS_HZ                   1000
 200
 201
 202 /* Bit-field values for MCCR1.
 203  */
 204 #define CONFIG_SYS_ROMNAL               0
 205 #define CONFIG_SYS_ROMFAL               8
 206
 207 #define CONFIG_SYS_BANK0_ROW            0       /* SDRAM bank 7-0 row address */
 208 #define CONFIG_SYS_BANK1_ROW            0
 209 #define CONFIG_SYS_BANK2_ROW            0
 210 #define CONFIG_SYS_BANK3_ROW            0
 211 #define CONFIG_SYS_BANK4_ROW            0
 212 #define CONFIG_SYS_BANK5_ROW            0
 213 #define CONFIG_SYS_BANK6_ROW            0
 214 #define CONFIG_SYS_BANK7_ROW            0
 215
 216 /* Bit-field values for MCCR2.
 217  */
 218
 219 #define CONFIG_SYS_REFINT               0x2ec
 220
 221 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 222  */
 223 #define CONFIG_SYS_BSTOPRE              160
 224
 225 /* Bit-field values for MCCR3.
 226  */
 227 #define CONFIG_SYS_REFREC               2       /* Refresh to activate interval         */
 228 #define CONFIG_SYS_RDLAT                0       /* Data latancy from read command       */
 229
 230 /* Bit-field values for MCCR4.
 231  */
 232 #define CONFIG_SYS_PRETOACT             2       /* Precharge to activate interval       */
 233 #define CONFIG_SYS_ACTTOPRE             5       /* Activate to Precharge interval       */
 234 #define CONFIG_SYS_SDMODE_CAS_LAT       2       /* SDMODE CAS latancy                   */
 235 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE wrap type                     */
 236 #define CONFIG_SYS_SDMODE_BURSTLEN      2       /* SDMODE Burst length                  */
 237 #define CONFIG_SYS_ACTORW               2
 238 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 239 #define CONFIG_SYS_EXTROM               0
 240 #define CONFIG_SYS_REGDIMM              0
 241
 242 /* Memory bank settings.
 243  * Only bits 20-29 are actually used from these vales to set the
 244  * start/end addresses. The upper two bits will always be 0, and the lower
 245  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 246  * address. Refer to the MPC8240 book.
 247  */
 248
 249 #define CONFIG_SYS_BANK0_START          0x00000000
 250 #define CONFIG_SYS_BANK0_END            (CONFIG_SYS_MAX_RAM_SIZE - 1)
 251 #define CONFIG_SYS_BANK0_ENABLE 1
 252 #define CONFIG_SYS_BANK1_START          0x3ff00000
 253 #define CONFIG_SYS_BANK1_END            0x3fffffff
 254 #define CONFIG_SYS_BANK1_ENABLE 0
 255 #define CONFIG_SYS_BANK2_START          0x3ff00000
 256 #define CONFIG_SYS_BANK2_END            0x3fffffff
 257 #define CONFIG_SYS_BANK2_ENABLE 0
 258 #define CONFIG_SYS_BANK3_START          0x3ff00000
 259 #define CONFIG_SYS_BANK3_END            0x3fffffff
 260 #define CONFIG_SYS_BANK3_ENABLE 0
 261 #define CONFIG_SYS_BANK4_START          0x3ff00000
 262 #define CONFIG_SYS_BANK4_END            0x3fffffff
 263 #define CONFIG_SYS_BANK4_ENABLE 0
 264 #define CONFIG_SYS_BANK5_START          0x3ff00000
 265 #define CONFIG_SYS_BANK5_END            0x3fffffff
 266 #define CONFIG_SYS_BANK5_ENABLE 0
 267 #define CONFIG_SYS_BANK6_START          0x3ff00000
 268 #define CONFIG_SYS_BANK6_END            0x3fffffff
 269 #define CONFIG_SYS_BANK6_ENABLE 0
 270 #define CONFIG_SYS_BANK7_START          0x3ff00000
 271 #define CONFIG_SYS_BANK7_END            0x3fffffff
 272 #define CONFIG_SYS_BANK7_ENABLE 0
 273
 274 #define CONFIG_SYS_ODCR         0xff
 275 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 276                                         /* currently accessed page in memory    */
 277                                         /* see 8240 book for details            */
 278
 279 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 280 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 281
 282 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 283 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 284
 285 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 286 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 287
 288 #define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 289 #define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
 290
 291 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 292 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 293 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 294 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 295 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 296 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 297 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 298 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 299
 300 /*
 301  * For booting Linux, the board info and command line data
 302  * have to be in the first 8 MB of memory, since this is
 303  * the maximum mapped by the Linux kernel during initialization.
 304  */
 305 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 306
 307 /*-----------------------------------------------------------------------
 308  * FLASH organization
 309  */
 310 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* Max number of flash banks            */
 311 #define CONFIG_SYS_MAX_FLASH_SECT       39      /* Max number of sectors in one bank    */
 312 #define INTEL_ID_28F160F3T      0x88F388F3      /*  16M = 1M x 16 top boot sector       */
 313 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 314 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 315
 316         /* Warining: environment is not EMBEDDED in the ppcboot code.
 317          * It's stored in flash separately.
 318          */
 319 #define CONFIG_ENV_IS_IN_FLASH      1
 320
 321 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x7F8000)
 322 #define CONFIG_ENV_SIZE         0x4000  /* Size of the Environment              */
 323 #define CONFIG_ENV_OFFSET               0       /* starting right at the beginning      */
 324 #define CONFIG_ENV_SECT_SIZE    0x8000 /* Size of the Environment Sector        */
 325
 326 /*-----------------------------------------------------------------------
 327  * Cache Configuration
 328  */
 329 #define CONFIG_SYS_CACHELINE_SIZE       32
 330 #if defined(CONFIG_CMD_KGDB)
 331 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 332 #endif
 333
 334 /*----------------------------------------------------------------------*/
 335 /* CPC45 Memory Map                                                     */
 336 /*----------------------------------------------------------------------*/
 337 #define SRAM_BASE       0x80000000      /* SRAM base address            */
 338 #define SRAM_END        0x801FFFFF
 339 #define ST16552_A_BASE  0x80200000      /* ST16552 channel A            */
 340 #define ST16552_B_BASE  0x80400000      /* ST16552 channel A            */
 341 #define BCSR_BASE       0x80600000      /* board control / status registers */
 342 #define DISPLAY_BASE    0x80600040      /* DISPLAY base                 */
 343 #define PCMCIA_MEM_BASE 0x83000000      /* PCMCIA memory window base    */
 344 #define PCMCIA_IO_BASE  0xFE000000      /* PCMCIA IO window base        */
 345
 346 #define CONFIG_SYS_SRAM_BASE    SRAM_BASE
 347 #define CONFIG_SYS_SRAM_SIZE    (SRAM_END - SRAM_BASE + 1)
 348
 349 /*---------------------------------------------------------------------*/
 350 /* CPC45 Control/Status Registers                                      */
 351 /*---------------------------------------------------------------------*/
 352 #define IRQ_ENA_1               *((volatile uchar*)(BCSR_BASE + 0x00))
 353 #define IRQ_STAT_1              *((volatile uchar*)(BCSR_BASE + 0x01))
 354 #define IRQ_ENA_2               *((volatile uchar*)(BCSR_BASE + 0x02))
 355 #define IRQ_STAT_2              *((volatile uchar*)(BCSR_BASE + 0x03))
 356 #define BOARD_CTRL              *((volatile uchar*)(BCSR_BASE + 0x04))
 357 #define BOARD_STAT              *((volatile uchar*)(BCSR_BASE + 0x05))
 358 #define WDG_START               *((volatile uchar*)(BCSR_BASE + 0x06))
 359 #define WDG_PRESTOP             *((volatile uchar*)(BCSR_BASE + 0x06))
 360 #define WDG_STOP                *((volatile uchar*)(BCSR_BASE + 0x06))
 361 #define BOARD_REV               *((volatile uchar*)(BCSR_BASE + 0x07))
 362
 363 /* IRQ_ENA_1 bit definitions */
 364 #define I_ENA_1_IERA    0x80            /* INTA enable                  */
 365 #define I_ENA_1_IERB    0x40            /* INTB enable                  */
 366 #define I_ENA_1_IERC    0x20            /* INTC enable                  */
 367 #define I_ENA_1_IERD    0x10            /* INTD enable                  */
 368
 369 /* IRQ_STAT_1 bit definitions */
 370 #define I_STAT_1_INTA   0x80            /* INTA status                  */
 371 #define I_STAT_1_INTB   0x40            /* INTB status                  */
 372 #define I_STAT_1_INTC   0x20            /* INTC status                  */
 373 #define I_STAT_1_INTD   0x10            /* INTD status                  */
 374
 375 /* IRQ_ENA_2 bit definitions */
 376 #define I_ENA_2_IEAB    0x80            /* ABORT IRQ enable             */
 377 #define I_ENA_2_IEK1    0x40            /* KEY1 IRQ enable              */
 378 #define I_ENA_2_IEK2    0x20            /* KEY2 IRQ enable              */
 379 #define I_ENA_2_IERT    0x10            /* RTC IRQ enable               */
 380 #define I_ENA_2_IESM    0x08            /* LM81 IRQ enable              */
 381 #define I_ENA_2_IEDG    0x04            /* DEGENERATING IRQ enable      */
 382 #define I_ENA_2_IES2    0x02            /* ST16552/B IRQ enable         */
 383 #define I_ENA_2_IES1    0x01            /* ST16552/A IRQ enable         */
 384
 385 /* IRQ_STAT_2 bit definitions */
 386 #define I_STAT_2_ABO    0x80            /* ABORT IRQ status             */
 387 #define I_STAT_2_KY1    0x40            /* KEY1 IRQ status              */
 388 #define I_STAT_2_KY2    0x20            /* KEY2 IRQ status              */
 389 #define I_STAT_2_RTC    0x10            /* RTC IRQ status               */
 390 #define I_STAT_2_SMN    0x08            /* LM81 IRQ status              */
 391 #define I_STAT_2_DEG    0x04            /* DEGENERATING IRQ status      */
 392 #define I_STAT_2_SIO2   0x02            /* ST16552/B IRQ status         */
 393 #define I_STAT_2_SIO1   0x01            /* ST16552/A IRQ status         */
 394
 395 /* BOARD_CTRL bit definitions */
 396 #define USER_LEDS               2                       /* 2 user LEDs  */
 397
 398 #if (USER_LEDS == 4)
 399 #define B_CTRL_WRSE             0x80
 400 #define B_CTRL_KRSE             0x40
 401 #define B_CTRL_FWRE             0x20            /* Flash write enable           */
 402 #define B_CTRL_FWPT             0x10            /* Flash write protect          */
 403 #define B_CTRL_LED3             0x08            /* LED 3 control                */
 404 #define B_CTRL_LED2             0x04            /* LED 2 control                */
 405 #define B_CTRL_LED1             0x02            /* LED 1 control                */
 406 #define B_CTRL_LED0             0x01            /* LED 0 control                */
 407 #else
 408 #define B_CTRL_WRSE             0x80
 409 #define B_CTRL_KRSE             0x40
 410 #define B_CTRL_FWRE_1           0x20            /* Flash write enable           */
 411 #define B_CTRL_FWPT_1           0x10            /* Flash write protect          */
 412 #define B_CTRL_LED1             0x08            /* LED 1 control                */
 413 #define B_CTRL_LED0             0x04            /* LED 0 control                */
 414 #define B_CTRL_FWRE_0           0x02            /* Flash write enable           */
 415 #define B_CTRL_FWPT_0           0x01            /* Flash write protect          */
 416 #endif
 417
 418 /* BOARD_STAT bit definitions */
 419 #define B_STAT_WDGE             0x80
 420 #define B_STAT_WDGS             0x40
 421 #define B_STAT_WRST             0x20
 422 #define B_STAT_KRST             0x10
 423 #define B_STAT_CSW3             0x08            /* sitch bit 3 status           */
 424 #define B_STAT_CSW2             0x04            /* sitch bit 2 status           */
 425 #define B_STAT_CSW1             0x02            /* sitch bit 1 status           */
 426 #define B_STAT_CSW0             0x01            /* sitch bit 0 status           */
 427
 428 /*---------------------------------------------------------------------*/
 429 /* Display addresses                                                   */
 430 /*---------------------------------------------------------------------*/
 431 #define DISP_UDC_RAM    (DISPLAY_BASE + 0x08)   /* UDC RAM             */
 432 #define DISP_CHR_RAM    (DISPLAY_BASE + 0x18)   /* character Ram       */
 433 #define DISP_FLASH      (DISPLAY_BASE + 0x20)   /* Flash Ram           */
 434
 435 #define DISP_UDC_ADR    *((volatile uchar*)(DISPLAY_BASE + 0x00))       /* UDC Address Reg.    */
 436 #define DISP_CWORD      *((volatile uchar*)(DISPLAY_BASE + 0x10))       /* Control Word Reg.   */
 437
 438 #define DISP_DIG0       *((volatile uchar*)(DISP_CHR_RAM + 0x00))       /* Digit 0 address     */
 439 #define DISP_DIG1       *((volatile uchar*)(DISP_CHR_RAM + 0x01))       /* Digit 0 address     */
 440 #define DISP_DIG2       *((volatile uchar*)(DISP_CHR_RAM + 0x02))       /* Digit 0 address     */
 441 #define DISP_DIG3       *((volatile uchar*)(DISP_CHR_RAM + 0x03))       /* Digit 0 address     */
 442 #define DISP_DIG4       *((volatile uchar*)(DISP_CHR_RAM + 0x04))       /* Digit 0 address     */
 443 #define DISP_DIG5       *((volatile uchar*)(DISP_CHR_RAM + 0x05))       /* Digit 0 address     */
 444 #define DISP_DIG6       *((volatile uchar*)(DISP_CHR_RAM + 0x06))       /* Digit 0 address     */
 445 #define DISP_DIG7       *((volatile uchar*)(DISP_CHR_RAM + 0x07))       /* Digit 0 address     */
 446
 447
 448 /*-----------------------------------------------------------------------
 449  * PCI stuff
 450  *-----------------------------------------------------------------------
 451  */
 452 #define CONFIG_PCI                      /* include pci support                  */
 453 #define CONFIG_SYS_EARLY_PCI_INIT
 454 #undef  CONFIG_PCI_PNP
 455 #undef  CONFIG_PCI_SCAN_SHOW
 456
 457
 458 #define CONFIG_EEPRO100
 459 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
 460
 461 #define PCI_ENET0_IOADDR        0x82000000
 462 #define PCI_ENET0_MEMADDR       0x82000000
 463 #define PCI_PLX9030_IOADDR      0x82100000
 464 #define PCI_PLX9030_MEMADDR     0x82100000
 465
 466 /*-----------------------------------------------------------------------
 467  * PCMCIA stuff
 468  *-----------------------------------------------------------------------
 469  */
 470
 471 #define CONFIG_I82365
 472
 473 #define CONFIG_SYS_PCMCIA_MEM_ADDR      PCMCIA_MEM_BASE
 474 #define CONFIG_SYS_PCMCIA_MEM_SIZE      0x1000
 475
 476 #define CONFIG_PCMCIA_SLOT_A
 477
 478 /*-----------------------------------------------------------------------
 479  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 480  *-----------------------------------------------------------------------
 481  */
 482
 483 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 484 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 485
 486 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 487 #undef  CONFIG_IDE_RESET                /* reset for IDE not supported  */
 488 #define CONFIG_IDE_LED                  /* LED   for IDE is  supported  */
 489
 490 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 491 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 492
 493 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 494
 495 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 496
 497 #define CONFIG_SYS_ATA_DATA_OFFSET      CONFIG_SYS_PCMCIA_MEM_SIZE
 498
 499 /* Offset for normal register accesses  */
 500 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 501
 502 /* Offset for alternate registers       */
 503 #define CONFIG_SYS_ATA_ALT_OFFSET       (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
 504
 505 #define CONFIG_DOS_PARTITION
 506
 507 #endif  /* __CONFIG_H */